RTOS 1.0
stm32f429xx.h
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32
33#ifndef __STM32F429xx_H
34#define __STM32F429xx_H
35
36#ifdef __cplusplus
37extern "C" {
38#endif /* __cplusplus */
39
43
47#define __CM4_REV 0x0001U
48#define __MPU_PRESENT 1U
49#define __NVIC_PRIO_BITS 4U
50#define __Vendor_SysTickConfig 0U
51#define __FPU_PRESENT 1U
52
56
60
65typedef enum
66{
67 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
76 /****** STM32 specific Interrupt Numbers **********************************************************************/
95 ADC_IRQn = 18,
125 FMC_IRQn = 48,
138 ETH_IRQn = 61,
157 FPU_IRQn = 81,
167} IRQn_Type;
168
172
173#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
174#include "system_stm32f4xx.h"
175#include <stdint.h>
176
180
184
185typedef struct
186{
187 __IO uint32_t SR;
188 __IO uint32_t CR1;
189 __IO uint32_t CR2;
190 __IO uint32_t SMPR1;
191 __IO uint32_t SMPR2;
192 __IO uint32_t JOFR1;
193 __IO uint32_t JOFR2;
194 __IO uint32_t JOFR3;
195 __IO uint32_t JOFR4;
196 __IO uint32_t HTR;
197 __IO uint32_t LTR;
198 __IO uint32_t SQR1;
199 __IO uint32_t SQR2;
200 __IO uint32_t SQR3;
201 __IO uint32_t JSQR;
202 __IO uint32_t JDR1;
203 __IO uint32_t JDR2;
204 __IO uint32_t JDR3;
205 __IO uint32_t JDR4;
206 __IO uint32_t DR;
208
209typedef struct
210{
211 __IO uint32_t CSR;
212 __IO uint32_t CCR;
213 __IO uint32_t CDR;
216
217
221
222typedef struct
223{
224 __IO uint32_t TIR;
225 __IO uint32_t TDTR;
226 __IO uint32_t TDLR;
227 __IO uint32_t TDHR;
229
233
234typedef struct
235{
236 __IO uint32_t RIR;
237 __IO uint32_t RDTR;
238 __IO uint32_t RDLR;
239 __IO uint32_t RDHR;
241
245
246typedef struct
247{
248 __IO uint32_t FR1;
249 __IO uint32_t FR2;
251
255
256typedef struct
257{
258 __IO uint32_t MCR;
259 __IO uint32_t MSR;
260 __IO uint32_t TSR;
261 __IO uint32_t RF0R;
262 __IO uint32_t RF1R;
263 __IO uint32_t IER;
264 __IO uint32_t ESR;
265 __IO uint32_t BTR;
266 uint32_t RESERVED0[88];
267 CAN_TxMailBox_TypeDef sTxMailBox[3];
268 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
269 uint32_t RESERVED1[12];
270 __IO uint32_t FMR;
271 __IO uint32_t FM1R;
272 uint32_t RESERVED2;
273 __IO uint32_t FS1R;
274 uint32_t RESERVED3;
275 __IO uint32_t FFA1R;
276 uint32_t RESERVED4;
277 __IO uint32_t FA1R;
278 uint32_t RESERVED5[8];
279 CAN_FilterRegister_TypeDef sFilterRegister[28];
281
285
286typedef struct
287{
288 __IO uint32_t DR;
289 __IO uint8_t IDR;
290 uint8_t RESERVED0;
291 uint16_t RESERVED1;
292 __IO uint32_t CR;
294
298
299typedef struct
300{
301 __IO uint32_t CR;
302 __IO uint32_t SWTRIGR;
303 __IO uint32_t DHR12R1;
304 __IO uint32_t DHR12L1;
305 __IO uint32_t DHR8R1;
306 __IO uint32_t DHR12R2;
307 __IO uint32_t DHR12L2;
308 __IO uint32_t DHR8R2;
309 __IO uint32_t DHR12RD;
310 __IO uint32_t DHR12LD;
311 __IO uint32_t DHR8RD;
312 __IO uint32_t DOR1;
313 __IO uint32_t DOR2;
314 __IO uint32_t SR;
316
320
321typedef struct
322{
323 __IO uint32_t IDCODE;
324 __IO uint32_t CR;
325 __IO uint32_t APB1FZ;
326 __IO uint32_t APB2FZ;
328
332
333typedef struct
334{
335 __IO uint32_t CR;
336 __IO uint32_t SR;
337 __IO uint32_t RISR;
338 __IO uint32_t IER;
339 __IO uint32_t MISR;
340 __IO uint32_t ICR;
341 __IO uint32_t ESCR;
342 __IO uint32_t ESUR;
343 __IO uint32_t CWSTRTR;
344 __IO uint32_t CWSIZER;
345 __IO uint32_t DR;
347
351
352typedef struct
353{
354 __IO uint32_t CR;
355 __IO uint32_t NDTR;
356 __IO uint32_t PAR;
357 __IO uint32_t M0AR;
358 __IO uint32_t M1AR;
359 __IO uint32_t FCR;
361
362typedef struct
363{
364 __IO uint32_t LISR;
365 __IO uint32_t HISR;
366 __IO uint32_t LIFCR;
367 __IO uint32_t HIFCR;
369
373
374typedef struct
375{
376 __IO uint32_t CR;
377 __IO uint32_t ISR;
378 __IO uint32_t IFCR;
379 __IO uint32_t FGMAR;
380 __IO uint32_t FGOR;
381 __IO uint32_t BGMAR;
382 __IO uint32_t BGOR;
383 __IO uint32_t FGPFCCR;
384 __IO uint32_t FGCOLR;
385 __IO uint32_t BGPFCCR;
386 __IO uint32_t BGCOLR;
387 __IO uint32_t FGCMAR;
388 __IO uint32_t BGCMAR;
389 __IO uint32_t OPFCCR;
390 __IO uint32_t OCOLR;
391 __IO uint32_t OMAR;
392 __IO uint32_t OOR;
393 __IO uint32_t NLR;
394 __IO uint32_t LWR;
395 __IO uint32_t AMTCR;
396 uint32_t RESERVED[236];
397 __IO uint32_t FGCLUT[256];
398 __IO uint32_t BGCLUT[256];
400
404
405typedef struct
406{
407 __IO uint32_t MACCR;
408 __IO uint32_t MACFFR;
409 __IO uint32_t MACHTHR;
410 __IO uint32_t MACHTLR;
411 __IO uint32_t MACMIIAR;
412 __IO uint32_t MACMIIDR;
413 __IO uint32_t MACFCR;
414 __IO uint32_t MACVLANTR; /* 8 */
415 uint32_t RESERVED0[2];
416 __IO uint32_t MACRWUFFR; /* 11 */
417 __IO uint32_t MACPMTCSR;
418 uint32_t RESERVED1;
419 __IO uint32_t MACDBGR;
420 __IO uint32_t MACSR; /* 15 */
421 __IO uint32_t MACIMR;
422 __IO uint32_t MACA0HR;
423 __IO uint32_t MACA0LR;
424 __IO uint32_t MACA1HR;
425 __IO uint32_t MACA1LR;
426 __IO uint32_t MACA2HR;
427 __IO uint32_t MACA2LR;
428 __IO uint32_t MACA3HR;
429 __IO uint32_t MACA3LR; /* 24 */
430 uint32_t RESERVED2[40];
431 __IO uint32_t MMCCR; /* 65 */
432 __IO uint32_t MMCRIR;
433 __IO uint32_t MMCTIR;
434 __IO uint32_t MMCRIMR;
435 __IO uint32_t MMCTIMR; /* 69 */
436 uint32_t RESERVED3[14];
437 __IO uint32_t MMCTGFSCCR; /* 84 */
438 __IO uint32_t MMCTGFMSCCR;
439 uint32_t RESERVED4[5];
440 __IO uint32_t MMCTGFCR;
441 uint32_t RESERVED5[10];
442 __IO uint32_t MMCRFCECR;
443 __IO uint32_t MMCRFAECR;
444 uint32_t RESERVED6[10];
445 __IO uint32_t MMCRGUFCR;
446 uint32_t RESERVED7[334];
447 __IO uint32_t PTPTSCR;
448 __IO uint32_t PTPSSIR;
449 __IO uint32_t PTPTSHR;
450 __IO uint32_t PTPTSLR;
451 __IO uint32_t PTPTSHUR;
452 __IO uint32_t PTPTSLUR;
453 __IO uint32_t PTPTSAR;
454 __IO uint32_t PTPTTHR;
455 __IO uint32_t PTPTTLR;
456 __IO uint32_t RESERVED8;
457 __IO uint32_t PTPTSSR;
458 uint32_t RESERVED9[565];
459 __IO uint32_t DMABMR;
460 __IO uint32_t DMATPDR;
461 __IO uint32_t DMARPDR;
462 __IO uint32_t DMARDLAR;
463 __IO uint32_t DMATDLAR;
464 __IO uint32_t DMASR;
465 __IO uint32_t DMAOMR;
466 __IO uint32_t DMAIER;
467 __IO uint32_t DMAMFBOCR;
468 __IO uint32_t DMARSWTR;
469 uint32_t RESERVED10[8];
470 __IO uint32_t DMACHTDR;
471 __IO uint32_t DMACHRDR;
472 __IO uint32_t DMACHTBAR;
473 __IO uint32_t DMACHRBAR;
475
479
480typedef struct
481{
482 __IO uint32_t IMR;
483 __IO uint32_t EMR;
484 __IO uint32_t RTSR;
485 __IO uint32_t FTSR;
486 __IO uint32_t SWIER;
487 __IO uint32_t PR;
489
493
494typedef struct
495{
496 __IO uint32_t ACR;
497 __IO uint32_t KEYR;
498 __IO uint32_t OPTKEYR;
499 __IO uint32_t SR;
500 __IO uint32_t CR;
501 __IO uint32_t OPTCR;
502 __IO uint32_t OPTCR1;
504
508
509typedef struct
510{
511 __IO uint32_t BTCR[8];
513
517
518typedef struct
519{
520 __IO uint32_t BWTR[7];
525
526typedef struct
527{
528 __IO uint32_t PCR2;
529 __IO uint32_t SR2;
530 __IO uint32_t PMEM2;
531 __IO uint32_t PATT2;
532 uint32_t RESERVED0;
533 __IO uint32_t ECCR2;
534 uint32_t RESERVED1;
535 uint32_t RESERVED2;
536 __IO uint32_t PCR3;
537 __IO uint32_t SR3;
538 __IO uint32_t PMEM3;
539 __IO uint32_t PATT3;
540 uint32_t RESERVED3;
541 __IO uint32_t ECCR3;
543
547
548typedef struct
549{
550 __IO uint32_t PCR4;
551 __IO uint32_t SR4;
552 __IO uint32_t PMEM4;
553 __IO uint32_t PATT4;
554 __IO uint32_t PIO4;
556
560
561typedef struct
562{
563 __IO uint32_t SDCR[2];
564 __IO uint32_t SDTR[2];
565 __IO uint32_t SDCMR;
566 __IO uint32_t SDRTR;
567 __IO uint32_t SDSR;
569
573
574typedef struct
575{
576 __IO uint32_t MODER;
577 __IO uint32_t OTYPER;
578 __IO uint32_t OSPEEDR;
579 __IO uint32_t PUPDR;
580 __IO uint32_t IDR;
581 __IO uint32_t ODR;
582 __IO uint32_t BSRR;
583 __IO uint32_t LCKR;
584 __IO uint32_t AFR[2];
586
590
591typedef struct
592{
593 __IO uint32_t MEMRMP;
594 __IO uint32_t PMC;
595 __IO uint32_t EXTICR[4];
596 uint32_t RESERVED[2];
597 __IO uint32_t CMPCR;
599
603
604typedef struct
605{
606 __IO uint32_t CR1;
607 __IO uint32_t CR2;
608 __IO uint32_t OAR1;
609 __IO uint32_t OAR2;
610 __IO uint32_t DR;
611 __IO uint32_t SR1;
612 __IO uint32_t SR2;
613 __IO uint32_t CCR;
614 __IO uint32_t TRISE;
615 __IO uint32_t FLTR;
617
621
622typedef struct
623{
624 __IO uint32_t KR;
625 __IO uint32_t PR;
626 __IO uint32_t RLR;
627 __IO uint32_t SR;
629
633
634typedef struct
635{
636 uint32_t RESERVED0[2];
637 __IO uint32_t SSCR;
638 __IO uint32_t BPCR;
639 __IO uint32_t AWCR;
640 __IO uint32_t TWCR;
641 __IO uint32_t GCR;
642 uint32_t RESERVED1[2];
643 __IO uint32_t SRCR;
644 uint32_t RESERVED2[1];
645 __IO uint32_t BCCR;
646 uint32_t RESERVED3[1];
647 __IO uint32_t IER;
648 __IO uint32_t ISR;
649 __IO uint32_t ICR;
650 __IO uint32_t LIPCR;
651 __IO uint32_t CPSR;
652 __IO uint32_t CDSR;
654
658
659typedef struct
660{
661 __IO uint32_t CR;
662 __IO uint32_t WHPCR;
663 __IO uint32_t WVPCR;
664 __IO uint32_t CKCR;
665 __IO uint32_t PFCR;
666 __IO uint32_t CACR;
667 __IO uint32_t DCCR;
668 __IO uint32_t BFCR;
669 uint32_t RESERVED0[2];
670 __IO uint32_t CFBAR;
671 __IO uint32_t CFBLR;
672 __IO uint32_t CFBLNR;
673 uint32_t RESERVED1[3];
674 __IO uint32_t CLUTWR;
676
680
681typedef struct
682{
683 __IO uint32_t CR;
684 __IO uint32_t CSR;
686
690
691typedef struct
692{
693 __IO uint32_t CR;
694 __IO uint32_t PLLCFGR;
695 __IO uint32_t CFGR;
696 __IO uint32_t CIR;
697 __IO uint32_t AHB1RSTR;
698 __IO uint32_t AHB2RSTR;
699 __IO uint32_t AHB3RSTR;
700 uint32_t RESERVED0;
701 __IO uint32_t APB1RSTR;
702 __IO uint32_t APB2RSTR;
703 uint32_t RESERVED1[2];
704 __IO uint32_t AHB1ENR;
705 __IO uint32_t AHB2ENR;
706 __IO uint32_t AHB3ENR;
707 uint32_t RESERVED2;
708 __IO uint32_t APB1ENR;
709 __IO uint32_t APB2ENR;
710 uint32_t RESERVED3[2];
711 __IO uint32_t AHB1LPENR;
712 __IO uint32_t AHB2LPENR;
713 __IO uint32_t AHB3LPENR;
714 uint32_t RESERVED4;
715 __IO uint32_t APB1LPENR;
716 __IO uint32_t APB2LPENR;
717 uint32_t RESERVED5[2];
718 __IO uint32_t BDCR;
719 __IO uint32_t CSR;
720 uint32_t RESERVED6[2];
721 __IO uint32_t SSCGR;
722 __IO uint32_t PLLI2SCFGR;
723 __IO uint32_t PLLSAICFGR;
724 __IO uint32_t DCKCFGR;
726
730
731typedef struct
732{
733 __IO uint32_t TR;
734 __IO uint32_t DR;
735 __IO uint32_t CR;
736 __IO uint32_t ISR;
737 __IO uint32_t PRER;
738 __IO uint32_t WUTR;
739 __IO uint32_t CALIBR;
740 __IO uint32_t ALRMAR;
741 __IO uint32_t ALRMBR;
742 __IO uint32_t WPR;
743 __IO uint32_t SSR;
744 __IO uint32_t SHIFTR;
745 __IO uint32_t TSTR;
746 __IO uint32_t TSDR;
747 __IO uint32_t TSSSR;
748 __IO uint32_t CALR;
749 __IO uint32_t TAFCR;
750 __IO uint32_t ALRMASSR;
751 __IO uint32_t ALRMBSSR;
752 uint32_t RESERVED7;
753 __IO uint32_t BKP0R;
754 __IO uint32_t BKP1R;
755 __IO uint32_t BKP2R;
756 __IO uint32_t BKP3R;
757 __IO uint32_t BKP4R;
758 __IO uint32_t BKP5R;
759 __IO uint32_t BKP6R;
760 __IO uint32_t BKP7R;
761 __IO uint32_t BKP8R;
762 __IO uint32_t BKP9R;
763 __IO uint32_t BKP10R;
764 __IO uint32_t BKP11R;
765 __IO uint32_t BKP12R;
766 __IO uint32_t BKP13R;
767 __IO uint32_t BKP14R;
768 __IO uint32_t BKP15R;
769 __IO uint32_t BKP16R;
770 __IO uint32_t BKP17R;
771 __IO uint32_t BKP18R;
772 __IO uint32_t BKP19R;
774
778
779typedef struct
780{
781 __IO uint32_t GCR;
783
784typedef struct
785{
786 __IO uint32_t CR1;
787 __IO uint32_t CR2;
788 __IO uint32_t FRCR;
789 __IO uint32_t SLOTR;
790 __IO uint32_t IMR;
791 __IO uint32_t SR;
792 __IO uint32_t CLRFR;
793 __IO uint32_t DR;
795
799
800typedef struct
801{
802 __IO uint32_t POWER;
803 __IO uint32_t CLKCR;
804 __IO uint32_t ARG;
805 __IO uint32_t CMD;
806 __IO const uint32_t RESPCMD;
807 __IO const uint32_t RESP1;
808 __IO const uint32_t RESP2;
809 __IO const uint32_t RESP3;
810 __IO const uint32_t RESP4;
811 __IO uint32_t DTIMER;
812 __IO uint32_t DLEN;
813 __IO uint32_t DCTRL;
814 __IO const uint32_t DCOUNT;
815 __IO const uint32_t STA;
816 __IO uint32_t ICR;
817 __IO uint32_t MASK;
818 uint32_t RESERVED0[2];
819 __IO const uint32_t FIFOCNT;
820 uint32_t RESERVED1[13];
821 __IO uint32_t FIFO;
823
827
828typedef struct
829{
830 __IO uint32_t CR1;
831 __IO uint32_t CR2;
832 __IO uint32_t SR;
833 __IO uint32_t DR;
834 __IO uint32_t CRCPR;
835 __IO uint32_t RXCRCR;
836 __IO uint32_t TXCRCR;
837 __IO uint32_t I2SCFGR;
838 __IO uint32_t I2SPR;
840
841
845
846typedef struct
847{
848 __IO uint32_t CR1;
849 __IO uint32_t CR2;
850 __IO uint32_t SMCR;
851 __IO uint32_t DIER;
852 __IO uint32_t SR;
853 __IO uint32_t EGR;
854 __IO uint32_t CCMR1;
855 __IO uint32_t CCMR2;
856 __IO uint32_t CCER;
857 __IO uint32_t CNT;
858 __IO uint32_t PSC;
859 __IO uint32_t ARR;
860 __IO uint32_t RCR;
861 __IO uint32_t CCR1;
862 __IO uint32_t CCR2;
863 __IO uint32_t CCR3;
864 __IO uint32_t CCR4;
865 __IO uint32_t BDTR;
866 __IO uint32_t DCR;
867 __IO uint32_t DMAR;
868 __IO uint32_t OR;
870
874
875typedef struct
876{
877 __IO uint32_t SR;
878 __IO uint32_t DR;
879 __IO uint32_t BRR;
880 __IO uint32_t CR1;
881 __IO uint32_t CR2;
882 __IO uint32_t CR3;
883 __IO uint32_t GTPR;
885
889
890typedef struct
891{
892 __IO uint32_t CR;
893 __IO uint32_t CFR;
894 __IO uint32_t SR;
896
900
901typedef struct
902{
903 __IO uint32_t CR;
904 __IO uint32_t SR;
905 __IO uint32_t DR;
907
911typedef struct
912{
913 __IO uint32_t GOTGCTL;
914 __IO uint32_t GOTGINT;
915 __IO uint32_t GAHBCFG;
916 __IO uint32_t GUSBCFG;
917 __IO uint32_t GRSTCTL;
918 __IO uint32_t GINTSTS;
919 __IO uint32_t GINTMSK;
920 __IO uint32_t GRXSTSR;
921 __IO uint32_t GRXSTSP;
922 __IO uint32_t GRXFSIZ;
923 __IO uint32_t DIEPTXF0_HNPTXFSIZ;
924 __IO uint32_t HNPTXSTS;
925 uint32_t Reserved30[2];
926 __IO uint32_t GCCFG;
927 __IO uint32_t CID;
928 uint32_t Reserved40[48];
929 __IO uint32_t HPTXFSIZ;
930 __IO uint32_t DIEPTXF[0x0F];
932
936typedef struct
937{
938 __IO uint32_t DCFG;
939 __IO uint32_t DCTL;
940 __IO uint32_t DSTS;
941 uint32_t Reserved0C;
942 __IO uint32_t DIEPMSK;
943 __IO uint32_t DOEPMSK;
944 __IO uint32_t DAINT;
945 __IO uint32_t DAINTMSK;
946 uint32_t Reserved20;
947 uint32_t Reserved9;
948 __IO uint32_t DVBUSDIS;
949 __IO uint32_t DVBUSPULSE;
950 __IO uint32_t DTHRCTL;
951 __IO uint32_t DIEPEMPMSK;
952 __IO uint32_t DEACHINT;
953 __IO uint32_t DEACHMSK;
954 uint32_t Reserved40;
955 __IO uint32_t DINEP1MSK;
956 uint32_t Reserved44[15];
957 __IO uint32_t DOUTEP1MSK;
959
963typedef struct
964{
965 __IO uint32_t DIEPCTL;
966 uint32_t Reserved04;
967 __IO uint32_t DIEPINT;
968 uint32_t Reserved0C;
969 __IO uint32_t DIEPTSIZ;
970 __IO uint32_t DIEPDMA;
971 __IO uint32_t DTXFSTS;
972 uint32_t Reserved18;
974
978typedef struct
979{
980 __IO uint32_t DOEPCTL;
981 uint32_t Reserved04;
982 __IO uint32_t DOEPINT;
983 uint32_t Reserved0C;
984 __IO uint32_t DOEPTSIZ;
985 __IO uint32_t DOEPDMA;
986 uint32_t Reserved18[2];
988
992typedef struct
993{
994 __IO uint32_t HCFG;
995 __IO uint32_t HFIR;
996 __IO uint32_t HFNUM;
997 uint32_t Reserved40C;
998 __IO uint32_t HPTXSTS;
999 __IO uint32_t HAINT;
1000 __IO uint32_t HAINTMSK;
1002
1006typedef struct
1007{
1008 __IO uint32_t HCCHAR;
1009 __IO uint32_t HCSPLT;
1010 __IO uint32_t HCINT;
1011 __IO uint32_t HCINTMSK;
1012 __IO uint32_t HCTSIZ;
1013 __IO uint32_t HCDMA;
1014 uint32_t Reserved[2];
1016
1020
1024#define FLASH_BASE 0x08000000UL
1025#define CCMDATARAM_BASE 0x10000000UL
1026#define SRAM1_BASE 0x20000000UL
1027#define SRAM2_BASE 0x2001C000UL
1028#define SRAM3_BASE 0x20020000UL
1029#define PERIPH_BASE 0x40000000UL
1030#define BKPSRAM_BASE 0x40024000UL
1031#define FMC_R_BASE 0xA0000000UL
1032#define SRAM1_BB_BASE 0x22000000UL
1033#define SRAM2_BB_BASE 0x22380000UL
1034#define SRAM3_BB_BASE 0x22400000UL
1035#define PERIPH_BB_BASE 0x42000000UL
1036#define BKPSRAM_BB_BASE 0x42480000UL
1037#define FLASH_END 0x081FFFFFUL
1038#define FLASH_OTP_BASE 0x1FFF7800UL
1039#define FLASH_OTP_END 0x1FFF7A0FUL
1040#define CCMDATARAM_END 0x1000FFFFUL
1041
1042/* Legacy defines */
1043#define SRAM_BASE SRAM1_BASE
1044#define SRAM_BB_BASE SRAM1_BB_BASE
1045
1047#define APB1PERIPH_BASE PERIPH_BASE
1048#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
1049#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
1050#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000UL)
1051
1053#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL)
1054#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL)
1055#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL)
1056#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL)
1057#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL)
1058#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL)
1059#define TIM12_BASE (APB1PERIPH_BASE + 0x1800UL)
1060#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00UL)
1061#define TIM14_BASE (APB1PERIPH_BASE + 0x2000UL)
1062#define RTC_BASE (APB1PERIPH_BASE + 0x2800UL)
1063#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL)
1064#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL)
1065#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400UL)
1066#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL)
1067#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL)
1068#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000UL)
1069#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL)
1070#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL)
1071#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL)
1072#define UART5_BASE (APB1PERIPH_BASE + 0x5000UL)
1073#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL)
1074#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL)
1075#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL)
1076#define CAN1_BASE (APB1PERIPH_BASE + 0x6400UL)
1077#define CAN2_BASE (APB1PERIPH_BASE + 0x6800UL)
1078#define PWR_BASE (APB1PERIPH_BASE + 0x7000UL)
1079#define DAC_BASE (APB1PERIPH_BASE + 0x7400UL)
1080#define UART7_BASE (APB1PERIPH_BASE + 0x7800UL)
1081#define UART8_BASE (APB1PERIPH_BASE + 0x7C00UL)
1082
1084#define TIM1_BASE (APB2PERIPH_BASE + 0x0000UL)
1085#define TIM8_BASE (APB2PERIPH_BASE + 0x0400UL)
1086#define USART1_BASE (APB2PERIPH_BASE + 0x1000UL)
1087#define USART6_BASE (APB2PERIPH_BASE + 0x1400UL)
1088#define ADC1_BASE (APB2PERIPH_BASE + 0x2000UL)
1089#define ADC2_BASE (APB2PERIPH_BASE + 0x2100UL)
1090#define ADC3_BASE (APB2PERIPH_BASE + 0x2200UL)
1091#define ADC123_COMMON_BASE (APB2PERIPH_BASE + 0x2300UL)
1092/* Legacy define */
1093#define ADC_BASE ADC123_COMMON_BASE
1094#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00UL)
1095#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL)
1096#define SPI4_BASE (APB2PERIPH_BASE + 0x3400UL)
1097#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800UL)
1098#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00UL)
1099#define TIM9_BASE (APB2PERIPH_BASE + 0x4000UL)
1100#define TIM10_BASE (APB2PERIPH_BASE + 0x4400UL)
1101#define TIM11_BASE (APB2PERIPH_BASE + 0x4800UL)
1102#define SPI5_BASE (APB2PERIPH_BASE + 0x5000UL)
1103#define SPI6_BASE (APB2PERIPH_BASE + 0x5400UL)
1104#define SAI1_BASE (APB2PERIPH_BASE + 0x5800UL)
1105#define SAI1_Block_A_BASE (SAI1_BASE + 0x004UL)
1106#define SAI1_Block_B_BASE (SAI1_BASE + 0x024UL)
1107#define LTDC_BASE (APB2PERIPH_BASE + 0x6800UL)
1108#define LTDC_Layer1_BASE (LTDC_BASE + 0x84UL)
1109#define LTDC_Layer2_BASE (LTDC_BASE + 0x104UL)
1110
1112#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000UL)
1113#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400UL)
1114#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800UL)
1115#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00UL)
1116#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000UL)
1117#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400UL)
1118#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800UL)
1119#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00UL)
1120#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000UL)
1121#define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400UL)
1122#define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800UL)
1123#define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL)
1124#define RCC_BASE (AHB1PERIPH_BASE + 0x3800UL)
1125#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00UL)
1126#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000UL)
1127#define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL)
1128#define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL)
1129#define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL)
1130#define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL)
1131#define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL)
1132#define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL)
1133#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL)
1134#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL)
1135#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400UL)
1136#define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL)
1137#define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL)
1138#define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL)
1139#define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL)
1140#define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL)
1141#define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL)
1142#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL)
1143#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL)
1144#define ETH_BASE (AHB1PERIPH_BASE + 0x8000UL)
1145#define ETH_MAC_BASE (ETH_BASE)
1146#define ETH_MMC_BASE (ETH_BASE + 0x0100UL)
1147#define ETH_PTP_BASE (ETH_BASE + 0x0700UL)
1148#define ETH_DMA_BASE (ETH_BASE + 0x1000UL)
1149#define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000UL)
1150
1152#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000UL)
1153#define RNG_BASE (AHB2PERIPH_BASE + 0x60800UL)
1154
1156#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL)
1157#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL)
1158#define FMC_Bank2_3_R_BASE (FMC_R_BASE + 0x0060UL)
1159#define FMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0UL)
1160#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140UL)
1161
1162
1164#define DBGMCU_BASE 0xE0042000UL
1166#define USB_OTG_HS_PERIPH_BASE 0x40040000UL
1167#define USB_OTG_FS_PERIPH_BASE 0x50000000UL
1168
1169#define USB_OTG_GLOBAL_BASE 0x000UL
1170#define USB_OTG_DEVICE_BASE 0x800UL
1171#define USB_OTG_IN_ENDPOINT_BASE 0x900UL
1172#define USB_OTG_OUT_ENDPOINT_BASE 0xB00UL
1173#define USB_OTG_EP_REG_SIZE 0x20UL
1174#define USB_OTG_HOST_BASE 0x400UL
1175#define USB_OTG_HOST_PORT_BASE 0x440UL
1176#define USB_OTG_HOST_CHANNEL_BASE 0x500UL
1177#define USB_OTG_HOST_CHANNEL_SIZE 0x20UL
1178#define USB_OTG_PCGCCTL_BASE 0xE00UL
1179#define USB_OTG_FIFO_BASE 0x1000UL
1180#define USB_OTG_FIFO_SIZE 0x1000UL
1181
1182#define UID_BASE 0x1FFF7A10UL
1183#define FLASHSIZE_BASE 0x1FFF7A22UL
1184#define PACKAGE_BASE 0x1FFF7BF0UL
1188
1192#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
1193#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
1194#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
1195#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
1196#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
1197#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
1198#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
1199#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
1200#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
1201#define RTC ((RTC_TypeDef *) RTC_BASE)
1202#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
1203#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
1204#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
1205#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
1206#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
1207#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
1208#define USART2 ((USART_TypeDef *) USART2_BASE)
1209#define USART3 ((USART_TypeDef *) USART3_BASE)
1210#define UART4 ((USART_TypeDef *) UART4_BASE)
1211#define UART5 ((USART_TypeDef *) UART5_BASE)
1212#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
1213#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
1214#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
1215#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
1216#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
1217#define PWR ((PWR_TypeDef *) PWR_BASE)
1218#define DAC1 ((DAC_TypeDef *) DAC_BASE)
1219#define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
1220#define UART7 ((USART_TypeDef *) UART7_BASE)
1221#define UART8 ((USART_TypeDef *) UART8_BASE)
1222#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
1223#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
1224#define USART1 ((USART_TypeDef *) USART1_BASE)
1225#define USART6 ((USART_TypeDef *) USART6_BASE)
1226#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
1227#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
1228#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
1229#define ADC123_COMMON ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)
1230/* Legacy define */
1231#define ADC ADC123_COMMON
1232#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
1233#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
1234#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
1235#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
1236#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
1237#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
1238#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
1239#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
1240#define SPI5 ((SPI_TypeDef *) SPI5_BASE)
1241#define SPI6 ((SPI_TypeDef *) SPI6_BASE)
1242#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
1243#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
1244#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
1245#define LTDC ((LTDC_TypeDef *)LTDC_BASE)
1246#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
1247#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
1248#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
1249#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
1250#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
1251#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
1252#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
1253#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
1254#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
1255#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
1256#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
1257#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
1258#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
1259#define CRC ((CRC_TypeDef *) CRC_BASE)
1260#define RCC ((RCC_TypeDef *) RCC_BASE)
1261#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
1262#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
1263#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
1264#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
1265#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
1266#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
1267#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
1268#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
1269#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
1270#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
1271#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
1272#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
1273#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
1274#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
1275#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
1276#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
1277#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
1278#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
1279#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
1280#define ETH ((ETH_TypeDef *) ETH_BASE)
1281#define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
1282#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
1283#define RNG ((RNG_TypeDef *) RNG_BASE)
1284#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
1285#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
1286#define FMC_Bank2_3 ((FMC_Bank2_3_TypeDef *) FMC_Bank2_3_R_BASE)
1287#define FMC_Bank4 ((FMC_Bank4_TypeDef *) FMC_Bank4_R_BASE)
1288#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
1289#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
1290#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
1291#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
1292
1296
1300
1304#define LSI_STARTUP_TIME 40U
1308
1312
1313/******************************************************************************/
1314/* Peripheral Registers_Bits_Definition */
1315/******************************************************************************/
1316
1317/******************************************************************************/
1318/* */
1319/* Analog to Digital Converter */
1320/* */
1321/******************************************************************************/
1322/*
1323 * @brief Specific device feature definitions (not present on all devices in the STM32F4 series)
1324 */
1325#define ADC_MULTIMODE_SUPPORT
1326
1327/******************** Bit definition for ADC_SR register ********************/
1328#define ADC_SR_AWD_Pos (0U)
1329#define ADC_SR_AWD_Msk (0x1UL << ADC_SR_AWD_Pos)
1330#define ADC_SR_AWD ADC_SR_AWD_Msk
1331#define ADC_SR_EOC_Pos (1U)
1332#define ADC_SR_EOC_Msk (0x1UL << ADC_SR_EOC_Pos)
1333#define ADC_SR_EOC ADC_SR_EOC_Msk
1334#define ADC_SR_JEOC_Pos (2U)
1335#define ADC_SR_JEOC_Msk (0x1UL << ADC_SR_JEOC_Pos)
1336#define ADC_SR_JEOC ADC_SR_JEOC_Msk
1337#define ADC_SR_JSTRT_Pos (3U)
1338#define ADC_SR_JSTRT_Msk (0x1UL << ADC_SR_JSTRT_Pos)
1339#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk
1340#define ADC_SR_STRT_Pos (4U)
1341#define ADC_SR_STRT_Msk (0x1UL << ADC_SR_STRT_Pos)
1342#define ADC_SR_STRT ADC_SR_STRT_Msk
1343#define ADC_SR_OVR_Pos (5U)
1344#define ADC_SR_OVR_Msk (0x1UL << ADC_SR_OVR_Pos)
1345#define ADC_SR_OVR ADC_SR_OVR_Msk
1346
1347/******************* Bit definition for ADC_CR1 register ********************/
1348#define ADC_CR1_AWDCH_Pos (0U)
1349#define ADC_CR1_AWDCH_Msk (0x1FUL << ADC_CR1_AWDCH_Pos)
1350#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk
1351#define ADC_CR1_AWDCH_0 (0x01UL << ADC_CR1_AWDCH_Pos)
1352#define ADC_CR1_AWDCH_1 (0x02UL << ADC_CR1_AWDCH_Pos)
1353#define ADC_CR1_AWDCH_2 (0x04UL << ADC_CR1_AWDCH_Pos)
1354#define ADC_CR1_AWDCH_3 (0x08UL << ADC_CR1_AWDCH_Pos)
1355#define ADC_CR1_AWDCH_4 (0x10UL << ADC_CR1_AWDCH_Pos)
1356#define ADC_CR1_EOCIE_Pos (5U)
1357#define ADC_CR1_EOCIE_Msk (0x1UL << ADC_CR1_EOCIE_Pos)
1358#define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk
1359#define ADC_CR1_AWDIE_Pos (6U)
1360#define ADC_CR1_AWDIE_Msk (0x1UL << ADC_CR1_AWDIE_Pos)
1361#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk
1362#define ADC_CR1_JEOCIE_Pos (7U)
1363#define ADC_CR1_JEOCIE_Msk (0x1UL << ADC_CR1_JEOCIE_Pos)
1364#define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk
1365#define ADC_CR1_SCAN_Pos (8U)
1366#define ADC_CR1_SCAN_Msk (0x1UL << ADC_CR1_SCAN_Pos)
1367#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk
1368#define ADC_CR1_AWDSGL_Pos (9U)
1369#define ADC_CR1_AWDSGL_Msk (0x1UL << ADC_CR1_AWDSGL_Pos)
1370#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk
1371#define ADC_CR1_JAUTO_Pos (10U)
1372#define ADC_CR1_JAUTO_Msk (0x1UL << ADC_CR1_JAUTO_Pos)
1373#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk
1374#define ADC_CR1_DISCEN_Pos (11U)
1375#define ADC_CR1_DISCEN_Msk (0x1UL << ADC_CR1_DISCEN_Pos)
1376#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk
1377#define ADC_CR1_JDISCEN_Pos (12U)
1378#define ADC_CR1_JDISCEN_Msk (0x1UL << ADC_CR1_JDISCEN_Pos)
1379#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk
1380#define ADC_CR1_DISCNUM_Pos (13U)
1381#define ADC_CR1_DISCNUM_Msk (0x7UL << ADC_CR1_DISCNUM_Pos)
1382#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk
1383#define ADC_CR1_DISCNUM_0 (0x1UL << ADC_CR1_DISCNUM_Pos)
1384#define ADC_CR1_DISCNUM_1 (0x2UL << ADC_CR1_DISCNUM_Pos)
1385#define ADC_CR1_DISCNUM_2 (0x4UL << ADC_CR1_DISCNUM_Pos)
1386#define ADC_CR1_JAWDEN_Pos (22U)
1387#define ADC_CR1_JAWDEN_Msk (0x1UL << ADC_CR1_JAWDEN_Pos)
1388#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk
1389#define ADC_CR1_AWDEN_Pos (23U)
1390#define ADC_CR1_AWDEN_Msk (0x1UL << ADC_CR1_AWDEN_Pos)
1391#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk
1392#define ADC_CR1_RES_Pos (24U)
1393#define ADC_CR1_RES_Msk (0x3UL << ADC_CR1_RES_Pos)
1394#define ADC_CR1_RES ADC_CR1_RES_Msk
1395#define ADC_CR1_RES_0 (0x1UL << ADC_CR1_RES_Pos)
1396#define ADC_CR1_RES_1 (0x2UL << ADC_CR1_RES_Pos)
1397#define ADC_CR1_OVRIE_Pos (26U)
1398#define ADC_CR1_OVRIE_Msk (0x1UL << ADC_CR1_OVRIE_Pos)
1399#define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk
1400
1401/******************* Bit definition for ADC_CR2 register ********************/
1402#define ADC_CR2_ADON_Pos (0U)
1403#define ADC_CR2_ADON_Msk (0x1UL << ADC_CR2_ADON_Pos)
1404#define ADC_CR2_ADON ADC_CR2_ADON_Msk
1405#define ADC_CR2_CONT_Pos (1U)
1406#define ADC_CR2_CONT_Msk (0x1UL << ADC_CR2_CONT_Pos)
1407#define ADC_CR2_CONT ADC_CR2_CONT_Msk
1408#define ADC_CR2_DMA_Pos (8U)
1409#define ADC_CR2_DMA_Msk (0x1UL << ADC_CR2_DMA_Pos)
1410#define ADC_CR2_DMA ADC_CR2_DMA_Msk
1411#define ADC_CR2_DDS_Pos (9U)
1412#define ADC_CR2_DDS_Msk (0x1UL << ADC_CR2_DDS_Pos)
1413#define ADC_CR2_DDS ADC_CR2_DDS_Msk
1414#define ADC_CR2_EOCS_Pos (10U)
1415#define ADC_CR2_EOCS_Msk (0x1UL << ADC_CR2_EOCS_Pos)
1416#define ADC_CR2_EOCS ADC_CR2_EOCS_Msk
1417#define ADC_CR2_ALIGN_Pos (11U)
1418#define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos)
1419#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk
1420#define ADC_CR2_JEXTSEL_Pos (16U)
1421#define ADC_CR2_JEXTSEL_Msk (0xFUL << ADC_CR2_JEXTSEL_Pos)
1422#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk
1423#define ADC_CR2_JEXTSEL_0 (0x1UL << ADC_CR2_JEXTSEL_Pos)
1424#define ADC_CR2_JEXTSEL_1 (0x2UL << ADC_CR2_JEXTSEL_Pos)
1425#define ADC_CR2_JEXTSEL_2 (0x4UL << ADC_CR2_JEXTSEL_Pos)
1426#define ADC_CR2_JEXTSEL_3 (0x8UL << ADC_CR2_JEXTSEL_Pos)
1427#define ADC_CR2_JEXTEN_Pos (20U)
1428#define ADC_CR2_JEXTEN_Msk (0x3UL << ADC_CR2_JEXTEN_Pos)
1429#define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk
1430#define ADC_CR2_JEXTEN_0 (0x1UL << ADC_CR2_JEXTEN_Pos)
1431#define ADC_CR2_JEXTEN_1 (0x2UL << ADC_CR2_JEXTEN_Pos)
1432#define ADC_CR2_JSWSTART_Pos (22U)
1433#define ADC_CR2_JSWSTART_Msk (0x1UL << ADC_CR2_JSWSTART_Pos)
1434#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk
1435#define ADC_CR2_EXTSEL_Pos (24U)
1436#define ADC_CR2_EXTSEL_Msk (0xFUL << ADC_CR2_EXTSEL_Pos)
1437#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk
1438#define ADC_CR2_EXTSEL_0 (0x1UL << ADC_CR2_EXTSEL_Pos)
1439#define ADC_CR2_EXTSEL_1 (0x2UL << ADC_CR2_EXTSEL_Pos)
1440#define ADC_CR2_EXTSEL_2 (0x4UL << ADC_CR2_EXTSEL_Pos)
1441#define ADC_CR2_EXTSEL_3 (0x8UL << ADC_CR2_EXTSEL_Pos)
1442#define ADC_CR2_EXTEN_Pos (28U)
1443#define ADC_CR2_EXTEN_Msk (0x3UL << ADC_CR2_EXTEN_Pos)
1444#define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk
1445#define ADC_CR2_EXTEN_0 (0x1UL << ADC_CR2_EXTEN_Pos)
1446#define ADC_CR2_EXTEN_1 (0x2UL << ADC_CR2_EXTEN_Pos)
1447#define ADC_CR2_SWSTART_Pos (30U)
1448#define ADC_CR2_SWSTART_Msk (0x1UL << ADC_CR2_SWSTART_Pos)
1449#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk
1450
1451/****************** Bit definition for ADC_SMPR1 register *******************/
1452#define ADC_SMPR1_SMP10_Pos (0U)
1453#define ADC_SMPR1_SMP10_Msk (0x7UL << ADC_SMPR1_SMP10_Pos)
1454#define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk
1455#define ADC_SMPR1_SMP10_0 (0x1UL << ADC_SMPR1_SMP10_Pos)
1456#define ADC_SMPR1_SMP10_1 (0x2UL << ADC_SMPR1_SMP10_Pos)
1457#define ADC_SMPR1_SMP10_2 (0x4UL << ADC_SMPR1_SMP10_Pos)
1458#define ADC_SMPR1_SMP11_Pos (3U)
1459#define ADC_SMPR1_SMP11_Msk (0x7UL << ADC_SMPR1_SMP11_Pos)
1460#define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk
1461#define ADC_SMPR1_SMP11_0 (0x1UL << ADC_SMPR1_SMP11_Pos)
1462#define ADC_SMPR1_SMP11_1 (0x2UL << ADC_SMPR1_SMP11_Pos)
1463#define ADC_SMPR1_SMP11_2 (0x4UL << ADC_SMPR1_SMP11_Pos)
1464#define ADC_SMPR1_SMP12_Pos (6U)
1465#define ADC_SMPR1_SMP12_Msk (0x7UL << ADC_SMPR1_SMP12_Pos)
1466#define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk
1467#define ADC_SMPR1_SMP12_0 (0x1UL << ADC_SMPR1_SMP12_Pos)
1468#define ADC_SMPR1_SMP12_1 (0x2UL << ADC_SMPR1_SMP12_Pos)
1469#define ADC_SMPR1_SMP12_2 (0x4UL << ADC_SMPR1_SMP12_Pos)
1470#define ADC_SMPR1_SMP13_Pos (9U)
1471#define ADC_SMPR1_SMP13_Msk (0x7UL << ADC_SMPR1_SMP13_Pos)
1472#define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk
1473#define ADC_SMPR1_SMP13_0 (0x1UL << ADC_SMPR1_SMP13_Pos)
1474#define ADC_SMPR1_SMP13_1 (0x2UL << ADC_SMPR1_SMP13_Pos)
1475#define ADC_SMPR1_SMP13_2 (0x4UL << ADC_SMPR1_SMP13_Pos)
1476#define ADC_SMPR1_SMP14_Pos (12U)
1477#define ADC_SMPR1_SMP14_Msk (0x7UL << ADC_SMPR1_SMP14_Pos)
1478#define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk
1479#define ADC_SMPR1_SMP14_0 (0x1UL << ADC_SMPR1_SMP14_Pos)
1480#define ADC_SMPR1_SMP14_1 (0x2UL << ADC_SMPR1_SMP14_Pos)
1481#define ADC_SMPR1_SMP14_2 (0x4UL << ADC_SMPR1_SMP14_Pos)
1482#define ADC_SMPR1_SMP15_Pos (15U)
1483#define ADC_SMPR1_SMP15_Msk (0x7UL << ADC_SMPR1_SMP15_Pos)
1484#define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk
1485#define ADC_SMPR1_SMP15_0 (0x1UL << ADC_SMPR1_SMP15_Pos)
1486#define ADC_SMPR1_SMP15_1 (0x2UL << ADC_SMPR1_SMP15_Pos)
1487#define ADC_SMPR1_SMP15_2 (0x4UL << ADC_SMPR1_SMP15_Pos)
1488#define ADC_SMPR1_SMP16_Pos (18U)
1489#define ADC_SMPR1_SMP16_Msk (0x7UL << ADC_SMPR1_SMP16_Pos)
1490#define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk
1491#define ADC_SMPR1_SMP16_0 (0x1UL << ADC_SMPR1_SMP16_Pos)
1492#define ADC_SMPR1_SMP16_1 (0x2UL << ADC_SMPR1_SMP16_Pos)
1493#define ADC_SMPR1_SMP16_2 (0x4UL << ADC_SMPR1_SMP16_Pos)
1494#define ADC_SMPR1_SMP17_Pos (21U)
1495#define ADC_SMPR1_SMP17_Msk (0x7UL << ADC_SMPR1_SMP17_Pos)
1496#define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk
1497#define ADC_SMPR1_SMP17_0 (0x1UL << ADC_SMPR1_SMP17_Pos)
1498#define ADC_SMPR1_SMP17_1 (0x2UL << ADC_SMPR1_SMP17_Pos)
1499#define ADC_SMPR1_SMP17_2 (0x4UL << ADC_SMPR1_SMP17_Pos)
1500#define ADC_SMPR1_SMP18_Pos (24U)
1501#define ADC_SMPR1_SMP18_Msk (0x7UL << ADC_SMPR1_SMP18_Pos)
1502#define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk
1503#define ADC_SMPR1_SMP18_0 (0x1UL << ADC_SMPR1_SMP18_Pos)
1504#define ADC_SMPR1_SMP18_1 (0x2UL << ADC_SMPR1_SMP18_Pos)
1505#define ADC_SMPR1_SMP18_2 (0x4UL << ADC_SMPR1_SMP18_Pos)
1506
1507/****************** Bit definition for ADC_SMPR2 register *******************/
1508#define ADC_SMPR2_SMP0_Pos (0U)
1509#define ADC_SMPR2_SMP0_Msk (0x7UL << ADC_SMPR2_SMP0_Pos)
1510#define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk
1511#define ADC_SMPR2_SMP0_0 (0x1UL << ADC_SMPR2_SMP0_Pos)
1512#define ADC_SMPR2_SMP0_1 (0x2UL << ADC_SMPR2_SMP0_Pos)
1513#define ADC_SMPR2_SMP0_2 (0x4UL << ADC_SMPR2_SMP0_Pos)
1514#define ADC_SMPR2_SMP1_Pos (3U)
1515#define ADC_SMPR2_SMP1_Msk (0x7UL << ADC_SMPR2_SMP1_Pos)
1516#define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk
1517#define ADC_SMPR2_SMP1_0 (0x1UL << ADC_SMPR2_SMP1_Pos)
1518#define ADC_SMPR2_SMP1_1 (0x2UL << ADC_SMPR2_SMP1_Pos)
1519#define ADC_SMPR2_SMP1_2 (0x4UL << ADC_SMPR2_SMP1_Pos)
1520#define ADC_SMPR2_SMP2_Pos (6U)
1521#define ADC_SMPR2_SMP2_Msk (0x7UL << ADC_SMPR2_SMP2_Pos)
1522#define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk
1523#define ADC_SMPR2_SMP2_0 (0x1UL << ADC_SMPR2_SMP2_Pos)
1524#define ADC_SMPR2_SMP2_1 (0x2UL << ADC_SMPR2_SMP2_Pos)
1525#define ADC_SMPR2_SMP2_2 (0x4UL << ADC_SMPR2_SMP2_Pos)
1526#define ADC_SMPR2_SMP3_Pos (9U)
1527#define ADC_SMPR2_SMP3_Msk (0x7UL << ADC_SMPR2_SMP3_Pos)
1528#define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk
1529#define ADC_SMPR2_SMP3_0 (0x1UL << ADC_SMPR2_SMP3_Pos)
1530#define ADC_SMPR2_SMP3_1 (0x2UL << ADC_SMPR2_SMP3_Pos)
1531#define ADC_SMPR2_SMP3_2 (0x4UL << ADC_SMPR2_SMP3_Pos)
1532#define ADC_SMPR2_SMP4_Pos (12U)
1533#define ADC_SMPR2_SMP4_Msk (0x7UL << ADC_SMPR2_SMP4_Pos)
1534#define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk
1535#define ADC_SMPR2_SMP4_0 (0x1UL << ADC_SMPR2_SMP4_Pos)
1536#define ADC_SMPR2_SMP4_1 (0x2UL << ADC_SMPR2_SMP4_Pos)
1537#define ADC_SMPR2_SMP4_2 (0x4UL << ADC_SMPR2_SMP4_Pos)
1538#define ADC_SMPR2_SMP5_Pos (15U)
1539#define ADC_SMPR2_SMP5_Msk (0x7UL << ADC_SMPR2_SMP5_Pos)
1540#define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk
1541#define ADC_SMPR2_SMP5_0 (0x1UL << ADC_SMPR2_SMP5_Pos)
1542#define ADC_SMPR2_SMP5_1 (0x2UL << ADC_SMPR2_SMP5_Pos)
1543#define ADC_SMPR2_SMP5_2 (0x4UL << ADC_SMPR2_SMP5_Pos)
1544#define ADC_SMPR2_SMP6_Pos (18U)
1545#define ADC_SMPR2_SMP6_Msk (0x7UL << ADC_SMPR2_SMP6_Pos)
1546#define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk
1547#define ADC_SMPR2_SMP6_0 (0x1UL << ADC_SMPR2_SMP6_Pos)
1548#define ADC_SMPR2_SMP6_1 (0x2UL << ADC_SMPR2_SMP6_Pos)
1549#define ADC_SMPR2_SMP6_2 (0x4UL << ADC_SMPR2_SMP6_Pos)
1550#define ADC_SMPR2_SMP7_Pos (21U)
1551#define ADC_SMPR2_SMP7_Msk (0x7UL << ADC_SMPR2_SMP7_Pos)
1552#define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk
1553#define ADC_SMPR2_SMP7_0 (0x1UL << ADC_SMPR2_SMP7_Pos)
1554#define ADC_SMPR2_SMP7_1 (0x2UL << ADC_SMPR2_SMP7_Pos)
1555#define ADC_SMPR2_SMP7_2 (0x4UL << ADC_SMPR2_SMP7_Pos)
1556#define ADC_SMPR2_SMP8_Pos (24U)
1557#define ADC_SMPR2_SMP8_Msk (0x7UL << ADC_SMPR2_SMP8_Pos)
1558#define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk
1559#define ADC_SMPR2_SMP8_0 (0x1UL << ADC_SMPR2_SMP8_Pos)
1560#define ADC_SMPR2_SMP8_1 (0x2UL << ADC_SMPR2_SMP8_Pos)
1561#define ADC_SMPR2_SMP8_2 (0x4UL << ADC_SMPR2_SMP8_Pos)
1562#define ADC_SMPR2_SMP9_Pos (27U)
1563#define ADC_SMPR2_SMP9_Msk (0x7UL << ADC_SMPR2_SMP9_Pos)
1564#define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk
1565#define ADC_SMPR2_SMP9_0 (0x1UL << ADC_SMPR2_SMP9_Pos)
1566#define ADC_SMPR2_SMP9_1 (0x2UL << ADC_SMPR2_SMP9_Pos)
1567#define ADC_SMPR2_SMP9_2 (0x4UL << ADC_SMPR2_SMP9_Pos)
1568
1569/****************** Bit definition for ADC_JOFR1 register *******************/
1570#define ADC_JOFR1_JOFFSET1_Pos (0U)
1571#define ADC_JOFR1_JOFFSET1_Msk (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos)
1572#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk
1573
1574/****************** Bit definition for ADC_JOFR2 register *******************/
1575#define ADC_JOFR2_JOFFSET2_Pos (0U)
1576#define ADC_JOFR2_JOFFSET2_Msk (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos)
1577#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk
1578
1579/****************** Bit definition for ADC_JOFR3 register *******************/
1580#define ADC_JOFR3_JOFFSET3_Pos (0U)
1581#define ADC_JOFR3_JOFFSET3_Msk (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos)
1582#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk
1583
1584/****************** Bit definition for ADC_JOFR4 register *******************/
1585#define ADC_JOFR4_JOFFSET4_Pos (0U)
1586#define ADC_JOFR4_JOFFSET4_Msk (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos)
1587#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk
1588
1589/******************* Bit definition for ADC_HTR register ********************/
1590#define ADC_HTR_HT_Pos (0U)
1591#define ADC_HTR_HT_Msk (0xFFFUL << ADC_HTR_HT_Pos)
1592#define ADC_HTR_HT ADC_HTR_HT_Msk
1593
1594/******************* Bit definition for ADC_LTR register ********************/
1595#define ADC_LTR_LT_Pos (0U)
1596#define ADC_LTR_LT_Msk (0xFFFUL << ADC_LTR_LT_Pos)
1597#define ADC_LTR_LT ADC_LTR_LT_Msk
1598
1599/******************* Bit definition for ADC_SQR1 register *******************/
1600#define ADC_SQR1_SQ13_Pos (0U)
1601#define ADC_SQR1_SQ13_Msk (0x1FUL << ADC_SQR1_SQ13_Pos)
1602#define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk
1603#define ADC_SQR1_SQ13_0 (0x01UL << ADC_SQR1_SQ13_Pos)
1604#define ADC_SQR1_SQ13_1 (0x02UL << ADC_SQR1_SQ13_Pos)
1605#define ADC_SQR1_SQ13_2 (0x04UL << ADC_SQR1_SQ13_Pos)
1606#define ADC_SQR1_SQ13_3 (0x08UL << ADC_SQR1_SQ13_Pos)
1607#define ADC_SQR1_SQ13_4 (0x10UL << ADC_SQR1_SQ13_Pos)
1608#define ADC_SQR1_SQ14_Pos (5U)
1609#define ADC_SQR1_SQ14_Msk (0x1FUL << ADC_SQR1_SQ14_Pos)
1610#define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk
1611#define ADC_SQR1_SQ14_0 (0x01UL << ADC_SQR1_SQ14_Pos)
1612#define ADC_SQR1_SQ14_1 (0x02UL << ADC_SQR1_SQ14_Pos)
1613#define ADC_SQR1_SQ14_2 (0x04UL << ADC_SQR1_SQ14_Pos)
1614#define ADC_SQR1_SQ14_3 (0x08UL << ADC_SQR1_SQ14_Pos)
1615#define ADC_SQR1_SQ14_4 (0x10UL << ADC_SQR1_SQ14_Pos)
1616#define ADC_SQR1_SQ15_Pos (10U)
1617#define ADC_SQR1_SQ15_Msk (0x1FUL << ADC_SQR1_SQ15_Pos)
1618#define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk
1619#define ADC_SQR1_SQ15_0 (0x01UL << ADC_SQR1_SQ15_Pos)
1620#define ADC_SQR1_SQ15_1 (0x02UL << ADC_SQR1_SQ15_Pos)
1621#define ADC_SQR1_SQ15_2 (0x04UL << ADC_SQR1_SQ15_Pos)
1622#define ADC_SQR1_SQ15_3 (0x08UL << ADC_SQR1_SQ15_Pos)
1623#define ADC_SQR1_SQ15_4 (0x10UL << ADC_SQR1_SQ15_Pos)
1624#define ADC_SQR1_SQ16_Pos (15U)
1625#define ADC_SQR1_SQ16_Msk (0x1FUL << ADC_SQR1_SQ16_Pos)
1626#define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk
1627#define ADC_SQR1_SQ16_0 (0x01UL << ADC_SQR1_SQ16_Pos)
1628#define ADC_SQR1_SQ16_1 (0x02UL << ADC_SQR1_SQ16_Pos)
1629#define ADC_SQR1_SQ16_2 (0x04UL << ADC_SQR1_SQ16_Pos)
1630#define ADC_SQR1_SQ16_3 (0x08UL << ADC_SQR1_SQ16_Pos)
1631#define ADC_SQR1_SQ16_4 (0x10UL << ADC_SQR1_SQ16_Pos)
1632#define ADC_SQR1_L_Pos (20U)
1633#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos)
1634#define ADC_SQR1_L ADC_SQR1_L_Msk
1635#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos)
1636#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos)
1637#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos)
1638#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos)
1639
1640/******************* Bit definition for ADC_SQR2 register *******************/
1641#define ADC_SQR2_SQ7_Pos (0U)
1642#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos)
1643#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk
1644#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos)
1645#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos)
1646#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos)
1647#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos)
1648#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos)
1649#define ADC_SQR2_SQ8_Pos (5U)
1650#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos)
1651#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk
1652#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos)
1653#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos)
1654#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos)
1655#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos)
1656#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos)
1657#define ADC_SQR2_SQ9_Pos (10U)
1658#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos)
1659#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk
1660#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos)
1661#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos)
1662#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos)
1663#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos)
1664#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos)
1665#define ADC_SQR2_SQ10_Pos (15U)
1666#define ADC_SQR2_SQ10_Msk (0x1FUL << ADC_SQR2_SQ10_Pos)
1667#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk
1668#define ADC_SQR2_SQ10_0 (0x01UL << ADC_SQR2_SQ10_Pos)
1669#define ADC_SQR2_SQ10_1 (0x02UL << ADC_SQR2_SQ10_Pos)
1670#define ADC_SQR2_SQ10_2 (0x04UL << ADC_SQR2_SQ10_Pos)
1671#define ADC_SQR2_SQ10_3 (0x08UL << ADC_SQR2_SQ10_Pos)
1672#define ADC_SQR2_SQ10_4 (0x10UL << ADC_SQR2_SQ10_Pos)
1673#define ADC_SQR2_SQ11_Pos (20U)
1674#define ADC_SQR2_SQ11_Msk (0x1FUL << ADC_SQR2_SQ11_Pos)
1675#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk
1676#define ADC_SQR2_SQ11_0 (0x01UL << ADC_SQR2_SQ11_Pos)
1677#define ADC_SQR2_SQ11_1 (0x02UL << ADC_SQR2_SQ11_Pos)
1678#define ADC_SQR2_SQ11_2 (0x04UL << ADC_SQR2_SQ11_Pos)
1679#define ADC_SQR2_SQ11_3 (0x08UL << ADC_SQR2_SQ11_Pos)
1680#define ADC_SQR2_SQ11_4 (0x10UL << ADC_SQR2_SQ11_Pos)
1681#define ADC_SQR2_SQ12_Pos (25U)
1682#define ADC_SQR2_SQ12_Msk (0x1FUL << ADC_SQR2_SQ12_Pos)
1683#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk
1684#define ADC_SQR2_SQ12_0 (0x01UL << ADC_SQR2_SQ12_Pos)
1685#define ADC_SQR2_SQ12_1 (0x02UL << ADC_SQR2_SQ12_Pos)
1686#define ADC_SQR2_SQ12_2 (0x04UL << ADC_SQR2_SQ12_Pos)
1687#define ADC_SQR2_SQ12_3 (0x08UL << ADC_SQR2_SQ12_Pos)
1688#define ADC_SQR2_SQ12_4 (0x10UL << ADC_SQR2_SQ12_Pos)
1689
1690/******************* Bit definition for ADC_SQR3 register *******************/
1691#define ADC_SQR3_SQ1_Pos (0U)
1692#define ADC_SQR3_SQ1_Msk (0x1FUL << ADC_SQR3_SQ1_Pos)
1693#define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk
1694#define ADC_SQR3_SQ1_0 (0x01UL << ADC_SQR3_SQ1_Pos)
1695#define ADC_SQR3_SQ1_1 (0x02UL << ADC_SQR3_SQ1_Pos)
1696#define ADC_SQR3_SQ1_2 (0x04UL << ADC_SQR3_SQ1_Pos)
1697#define ADC_SQR3_SQ1_3 (0x08UL << ADC_SQR3_SQ1_Pos)
1698#define ADC_SQR3_SQ1_4 (0x10UL << ADC_SQR3_SQ1_Pos)
1699#define ADC_SQR3_SQ2_Pos (5U)
1700#define ADC_SQR3_SQ2_Msk (0x1FUL << ADC_SQR3_SQ2_Pos)
1701#define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk
1702#define ADC_SQR3_SQ2_0 (0x01UL << ADC_SQR3_SQ2_Pos)
1703#define ADC_SQR3_SQ2_1 (0x02UL << ADC_SQR3_SQ2_Pos)
1704#define ADC_SQR3_SQ2_2 (0x04UL << ADC_SQR3_SQ2_Pos)
1705#define ADC_SQR3_SQ2_3 (0x08UL << ADC_SQR3_SQ2_Pos)
1706#define ADC_SQR3_SQ2_4 (0x10UL << ADC_SQR3_SQ2_Pos)
1707#define ADC_SQR3_SQ3_Pos (10U)
1708#define ADC_SQR3_SQ3_Msk (0x1FUL << ADC_SQR3_SQ3_Pos)
1709#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk
1710#define ADC_SQR3_SQ3_0 (0x01UL << ADC_SQR3_SQ3_Pos)
1711#define ADC_SQR3_SQ3_1 (0x02UL << ADC_SQR3_SQ3_Pos)
1712#define ADC_SQR3_SQ3_2 (0x04UL << ADC_SQR3_SQ3_Pos)
1713#define ADC_SQR3_SQ3_3 (0x08UL << ADC_SQR3_SQ3_Pos)
1714#define ADC_SQR3_SQ3_4 (0x10UL << ADC_SQR3_SQ3_Pos)
1715#define ADC_SQR3_SQ4_Pos (15U)
1716#define ADC_SQR3_SQ4_Msk (0x1FUL << ADC_SQR3_SQ4_Pos)
1717#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk
1718#define ADC_SQR3_SQ4_0 (0x01UL << ADC_SQR3_SQ4_Pos)
1719#define ADC_SQR3_SQ4_1 (0x02UL << ADC_SQR3_SQ4_Pos)
1720#define ADC_SQR3_SQ4_2 (0x04UL << ADC_SQR3_SQ4_Pos)
1721#define ADC_SQR3_SQ4_3 (0x08UL << ADC_SQR3_SQ4_Pos)
1722#define ADC_SQR3_SQ4_4 (0x10UL << ADC_SQR3_SQ4_Pos)
1723#define ADC_SQR3_SQ5_Pos (20U)
1724#define ADC_SQR3_SQ5_Msk (0x1FUL << ADC_SQR3_SQ5_Pos)
1725#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk
1726#define ADC_SQR3_SQ5_0 (0x01UL << ADC_SQR3_SQ5_Pos)
1727#define ADC_SQR3_SQ5_1 (0x02UL << ADC_SQR3_SQ5_Pos)
1728#define ADC_SQR3_SQ5_2 (0x04UL << ADC_SQR3_SQ5_Pos)
1729#define ADC_SQR3_SQ5_3 (0x08UL << ADC_SQR3_SQ5_Pos)
1730#define ADC_SQR3_SQ5_4 (0x10UL << ADC_SQR3_SQ5_Pos)
1731#define ADC_SQR3_SQ6_Pos (25U)
1732#define ADC_SQR3_SQ6_Msk (0x1FUL << ADC_SQR3_SQ6_Pos)
1733#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk
1734#define ADC_SQR3_SQ6_0 (0x01UL << ADC_SQR3_SQ6_Pos)
1735#define ADC_SQR3_SQ6_1 (0x02UL << ADC_SQR3_SQ6_Pos)
1736#define ADC_SQR3_SQ6_2 (0x04UL << ADC_SQR3_SQ6_Pos)
1737#define ADC_SQR3_SQ6_3 (0x08UL << ADC_SQR3_SQ6_Pos)
1738#define ADC_SQR3_SQ6_4 (0x10UL << ADC_SQR3_SQ6_Pos)
1739
1740/******************* Bit definition for ADC_JSQR register *******************/
1741#define ADC_JSQR_JSQ1_Pos (0U)
1742#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos)
1743#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk
1744#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos)
1745#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos)
1746#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos)
1747#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos)
1748#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos)
1749#define ADC_JSQR_JSQ2_Pos (5U)
1750#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos)
1751#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk
1752#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos)
1753#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos)
1754#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos)
1755#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos)
1756#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos)
1757#define ADC_JSQR_JSQ3_Pos (10U)
1758#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos)
1759#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk
1760#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos)
1761#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos)
1762#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos)
1763#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos)
1764#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos)
1765#define ADC_JSQR_JSQ4_Pos (15U)
1766#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos)
1767#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk
1768#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos)
1769#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos)
1770#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos)
1771#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos)
1772#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos)
1773#define ADC_JSQR_JL_Pos (20U)
1774#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos)
1775#define ADC_JSQR_JL ADC_JSQR_JL_Msk
1776#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos)
1777#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos)
1778
1779/******************* Bit definition for ADC_JDR1 register *******************/
1780#define ADC_JDR1_JDATA_Pos (0U)
1781#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos)
1782#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk
1783
1784/******************* Bit definition for ADC_JDR2 register *******************/
1785#define ADC_JDR2_JDATA_Pos (0U)
1786#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos)
1787#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk
1788
1789/******************* Bit definition for ADC_JDR3 register *******************/
1790#define ADC_JDR3_JDATA_Pos (0U)
1791#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos)
1792#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk
1793
1794/******************* Bit definition for ADC_JDR4 register *******************/
1795#define ADC_JDR4_JDATA_Pos (0U)
1796#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos)
1797#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk
1798
1799/******************** Bit definition for ADC_DR register ********************/
1800#define ADC_DR_DATA_Pos (0U)
1801#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos)
1802#define ADC_DR_DATA ADC_DR_DATA_Msk
1803#define ADC_DR_ADC2DATA_Pos (16U)
1804#define ADC_DR_ADC2DATA_Msk (0xFFFFUL << ADC_DR_ADC2DATA_Pos)
1805#define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk
1806
1807/******************* Bit definition for ADC_CSR register ********************/
1808#define ADC_CSR_AWD1_Pos (0U)
1809#define ADC_CSR_AWD1_Msk (0x1UL << ADC_CSR_AWD1_Pos)
1810#define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk
1811#define ADC_CSR_EOC1_Pos (1U)
1812#define ADC_CSR_EOC1_Msk (0x1UL << ADC_CSR_EOC1_Pos)
1813#define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk
1814#define ADC_CSR_JEOC1_Pos (2U)
1815#define ADC_CSR_JEOC1_Msk (0x1UL << ADC_CSR_JEOC1_Pos)
1816#define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk
1817#define ADC_CSR_JSTRT1_Pos (3U)
1818#define ADC_CSR_JSTRT1_Msk (0x1UL << ADC_CSR_JSTRT1_Pos)
1819#define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk
1820#define ADC_CSR_STRT1_Pos (4U)
1821#define ADC_CSR_STRT1_Msk (0x1UL << ADC_CSR_STRT1_Pos)
1822#define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk
1823#define ADC_CSR_OVR1_Pos (5U)
1824#define ADC_CSR_OVR1_Msk (0x1UL << ADC_CSR_OVR1_Pos)
1825#define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk
1826#define ADC_CSR_AWD2_Pos (8U)
1827#define ADC_CSR_AWD2_Msk (0x1UL << ADC_CSR_AWD2_Pos)
1828#define ADC_CSR_AWD2 ADC_CSR_AWD2_Msk
1829#define ADC_CSR_EOC2_Pos (9U)
1830#define ADC_CSR_EOC2_Msk (0x1UL << ADC_CSR_EOC2_Pos)
1831#define ADC_CSR_EOC2 ADC_CSR_EOC2_Msk
1832#define ADC_CSR_JEOC2_Pos (10U)
1833#define ADC_CSR_JEOC2_Msk (0x1UL << ADC_CSR_JEOC2_Pos)
1834#define ADC_CSR_JEOC2 ADC_CSR_JEOC2_Msk
1835#define ADC_CSR_JSTRT2_Pos (11U)
1836#define ADC_CSR_JSTRT2_Msk (0x1UL << ADC_CSR_JSTRT2_Pos)
1837#define ADC_CSR_JSTRT2 ADC_CSR_JSTRT2_Msk
1838#define ADC_CSR_STRT2_Pos (12U)
1839#define ADC_CSR_STRT2_Msk (0x1UL << ADC_CSR_STRT2_Pos)
1840#define ADC_CSR_STRT2 ADC_CSR_STRT2_Msk
1841#define ADC_CSR_OVR2_Pos (13U)
1842#define ADC_CSR_OVR2_Msk (0x1UL << ADC_CSR_OVR2_Pos)
1843#define ADC_CSR_OVR2 ADC_CSR_OVR2_Msk
1844#define ADC_CSR_AWD3_Pos (16U)
1845#define ADC_CSR_AWD3_Msk (0x1UL << ADC_CSR_AWD3_Pos)
1846#define ADC_CSR_AWD3 ADC_CSR_AWD3_Msk
1847#define ADC_CSR_EOC3_Pos (17U)
1848#define ADC_CSR_EOC3_Msk (0x1UL << ADC_CSR_EOC3_Pos)
1849#define ADC_CSR_EOC3 ADC_CSR_EOC3_Msk
1850#define ADC_CSR_JEOC3_Pos (18U)
1851#define ADC_CSR_JEOC3_Msk (0x1UL << ADC_CSR_JEOC3_Pos)
1852#define ADC_CSR_JEOC3 ADC_CSR_JEOC3_Msk
1853#define ADC_CSR_JSTRT3_Pos (19U)
1854#define ADC_CSR_JSTRT3_Msk (0x1UL << ADC_CSR_JSTRT3_Pos)
1855#define ADC_CSR_JSTRT3 ADC_CSR_JSTRT3_Msk
1856#define ADC_CSR_STRT3_Pos (20U)
1857#define ADC_CSR_STRT3_Msk (0x1UL << ADC_CSR_STRT3_Pos)
1858#define ADC_CSR_STRT3 ADC_CSR_STRT3_Msk
1859#define ADC_CSR_OVR3_Pos (21U)
1860#define ADC_CSR_OVR3_Msk (0x1UL << ADC_CSR_OVR3_Pos)
1861#define ADC_CSR_OVR3 ADC_CSR_OVR3_Msk
1862
1863/* Legacy defines */
1864#define ADC_CSR_DOVR1 ADC_CSR_OVR1
1865#define ADC_CSR_DOVR2 ADC_CSR_OVR2
1866#define ADC_CSR_DOVR3 ADC_CSR_OVR3
1867
1868/******************* Bit definition for ADC_CCR register ********************/
1869#define ADC_CCR_MULTI_Pos (0U)
1870#define ADC_CCR_MULTI_Msk (0x1FUL << ADC_CCR_MULTI_Pos)
1871#define ADC_CCR_MULTI ADC_CCR_MULTI_Msk
1872#define ADC_CCR_MULTI_0 (0x01UL << ADC_CCR_MULTI_Pos)
1873#define ADC_CCR_MULTI_1 (0x02UL << ADC_CCR_MULTI_Pos)
1874#define ADC_CCR_MULTI_2 (0x04UL << ADC_CCR_MULTI_Pos)
1875#define ADC_CCR_MULTI_3 (0x08UL << ADC_CCR_MULTI_Pos)
1876#define ADC_CCR_MULTI_4 (0x10UL << ADC_CCR_MULTI_Pos)
1877#define ADC_CCR_DELAY_Pos (8U)
1878#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos)
1879#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk
1880#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos)
1881#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos)
1882#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos)
1883#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos)
1884#define ADC_CCR_DDS_Pos (13U)
1885#define ADC_CCR_DDS_Msk (0x1UL << ADC_CCR_DDS_Pos)
1886#define ADC_CCR_DDS ADC_CCR_DDS_Msk
1887#define ADC_CCR_DMA_Pos (14U)
1888#define ADC_CCR_DMA_Msk (0x3UL << ADC_CCR_DMA_Pos)
1889#define ADC_CCR_DMA ADC_CCR_DMA_Msk
1890#define ADC_CCR_DMA_0 (0x1UL << ADC_CCR_DMA_Pos)
1891#define ADC_CCR_DMA_1 (0x2UL << ADC_CCR_DMA_Pos)
1892#define ADC_CCR_ADCPRE_Pos (16U)
1893#define ADC_CCR_ADCPRE_Msk (0x3UL << ADC_CCR_ADCPRE_Pos)
1894#define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk
1895#define ADC_CCR_ADCPRE_0 (0x1UL << ADC_CCR_ADCPRE_Pos)
1896#define ADC_CCR_ADCPRE_1 (0x2UL << ADC_CCR_ADCPRE_Pos)
1897#define ADC_CCR_VBATE_Pos (22U)
1898#define ADC_CCR_VBATE_Msk (0x1UL << ADC_CCR_VBATE_Pos)
1899#define ADC_CCR_VBATE ADC_CCR_VBATE_Msk
1900#define ADC_CCR_TSVREFE_Pos (23U)
1901#define ADC_CCR_TSVREFE_Msk (0x1UL << ADC_CCR_TSVREFE_Pos)
1902#define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk
1903
1904/******************* Bit definition for ADC_CDR register ********************/
1905#define ADC_CDR_DATA1_Pos (0U)
1906#define ADC_CDR_DATA1_Msk (0xFFFFUL << ADC_CDR_DATA1_Pos)
1907#define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk
1908#define ADC_CDR_DATA2_Pos (16U)
1909#define ADC_CDR_DATA2_Msk (0xFFFFUL << ADC_CDR_DATA2_Pos)
1910#define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk
1911
1912/* Legacy defines */
1913#define ADC_CDR_RDATA_MST ADC_CDR_DATA1
1914#define ADC_CDR_RDATA_SLV ADC_CDR_DATA2
1915
1916/******************************************************************************/
1917/* */
1918/* Controller Area Network */
1919/* */
1920/******************************************************************************/
1922/******************* Bit definition for CAN_MCR register ********************/
1923#define CAN_MCR_INRQ_Pos (0U)
1924#define CAN_MCR_INRQ_Msk (0x1UL << CAN_MCR_INRQ_Pos)
1925#define CAN_MCR_INRQ CAN_MCR_INRQ_Msk
1926#define CAN_MCR_SLEEP_Pos (1U)
1927#define CAN_MCR_SLEEP_Msk (0x1UL << CAN_MCR_SLEEP_Pos)
1928#define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk
1929#define CAN_MCR_TXFP_Pos (2U)
1930#define CAN_MCR_TXFP_Msk (0x1UL << CAN_MCR_TXFP_Pos)
1931#define CAN_MCR_TXFP CAN_MCR_TXFP_Msk
1932#define CAN_MCR_RFLM_Pos (3U)
1933#define CAN_MCR_RFLM_Msk (0x1UL << CAN_MCR_RFLM_Pos)
1934#define CAN_MCR_RFLM CAN_MCR_RFLM_Msk
1935#define CAN_MCR_NART_Pos (4U)
1936#define CAN_MCR_NART_Msk (0x1UL << CAN_MCR_NART_Pos)
1937#define CAN_MCR_NART CAN_MCR_NART_Msk
1938#define CAN_MCR_AWUM_Pos (5U)
1939#define CAN_MCR_AWUM_Msk (0x1UL << CAN_MCR_AWUM_Pos)
1940#define CAN_MCR_AWUM CAN_MCR_AWUM_Msk
1941#define CAN_MCR_ABOM_Pos (6U)
1942#define CAN_MCR_ABOM_Msk (0x1UL << CAN_MCR_ABOM_Pos)
1943#define CAN_MCR_ABOM CAN_MCR_ABOM_Msk
1944#define CAN_MCR_TTCM_Pos (7U)
1945#define CAN_MCR_TTCM_Msk (0x1UL << CAN_MCR_TTCM_Pos)
1946#define CAN_MCR_TTCM CAN_MCR_TTCM_Msk
1947#define CAN_MCR_RESET_Pos (15U)
1948#define CAN_MCR_RESET_Msk (0x1UL << CAN_MCR_RESET_Pos)
1949#define CAN_MCR_RESET CAN_MCR_RESET_Msk
1950#define CAN_MCR_DBF_Pos (16U)
1951#define CAN_MCR_DBF_Msk (0x1UL << CAN_MCR_DBF_Pos)
1952#define CAN_MCR_DBF CAN_MCR_DBF_Msk
1953/******************* Bit definition for CAN_MSR register ********************/
1954#define CAN_MSR_INAK_Pos (0U)
1955#define CAN_MSR_INAK_Msk (0x1UL << CAN_MSR_INAK_Pos)
1956#define CAN_MSR_INAK CAN_MSR_INAK_Msk
1957#define CAN_MSR_SLAK_Pos (1U)
1958#define CAN_MSR_SLAK_Msk (0x1UL << CAN_MSR_SLAK_Pos)
1959#define CAN_MSR_SLAK CAN_MSR_SLAK_Msk
1960#define CAN_MSR_ERRI_Pos (2U)
1961#define CAN_MSR_ERRI_Msk (0x1UL << CAN_MSR_ERRI_Pos)
1962#define CAN_MSR_ERRI CAN_MSR_ERRI_Msk
1963#define CAN_MSR_WKUI_Pos (3U)
1964#define CAN_MSR_WKUI_Msk (0x1UL << CAN_MSR_WKUI_Pos)
1965#define CAN_MSR_WKUI CAN_MSR_WKUI_Msk
1966#define CAN_MSR_SLAKI_Pos (4U)
1967#define CAN_MSR_SLAKI_Msk (0x1UL << CAN_MSR_SLAKI_Pos)
1968#define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk
1969#define CAN_MSR_TXM_Pos (8U)
1970#define CAN_MSR_TXM_Msk (0x1UL << CAN_MSR_TXM_Pos)
1971#define CAN_MSR_TXM CAN_MSR_TXM_Msk
1972#define CAN_MSR_RXM_Pos (9U)
1973#define CAN_MSR_RXM_Msk (0x1UL << CAN_MSR_RXM_Pos)
1974#define CAN_MSR_RXM CAN_MSR_RXM_Msk
1975#define CAN_MSR_SAMP_Pos (10U)
1976#define CAN_MSR_SAMP_Msk (0x1UL << CAN_MSR_SAMP_Pos)
1977#define CAN_MSR_SAMP CAN_MSR_SAMP_Msk
1978#define CAN_MSR_RX_Pos (11U)
1979#define CAN_MSR_RX_Msk (0x1UL << CAN_MSR_RX_Pos)
1980#define CAN_MSR_RX CAN_MSR_RX_Msk
1981
1982/******************* Bit definition for CAN_TSR register ********************/
1983#define CAN_TSR_RQCP0_Pos (0U)
1984#define CAN_TSR_RQCP0_Msk (0x1UL << CAN_TSR_RQCP0_Pos)
1985#define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk
1986#define CAN_TSR_TXOK0_Pos (1U)
1987#define CAN_TSR_TXOK0_Msk (0x1UL << CAN_TSR_TXOK0_Pos)
1988#define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk
1989#define CAN_TSR_ALST0_Pos (2U)
1990#define CAN_TSR_ALST0_Msk (0x1UL << CAN_TSR_ALST0_Pos)
1991#define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk
1992#define CAN_TSR_TERR0_Pos (3U)
1993#define CAN_TSR_TERR0_Msk (0x1UL << CAN_TSR_TERR0_Pos)
1994#define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk
1995#define CAN_TSR_ABRQ0_Pos (7U)
1996#define CAN_TSR_ABRQ0_Msk (0x1UL << CAN_TSR_ABRQ0_Pos)
1997#define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk
1998#define CAN_TSR_RQCP1_Pos (8U)
1999#define CAN_TSR_RQCP1_Msk (0x1UL << CAN_TSR_RQCP1_Pos)
2000#define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk
2001#define CAN_TSR_TXOK1_Pos (9U)
2002#define CAN_TSR_TXOK1_Msk (0x1UL << CAN_TSR_TXOK1_Pos)
2003#define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk
2004#define CAN_TSR_ALST1_Pos (10U)
2005#define CAN_TSR_ALST1_Msk (0x1UL << CAN_TSR_ALST1_Pos)
2006#define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk
2007#define CAN_TSR_TERR1_Pos (11U)
2008#define CAN_TSR_TERR1_Msk (0x1UL << CAN_TSR_TERR1_Pos)
2009#define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk
2010#define CAN_TSR_ABRQ1_Pos (15U)
2011#define CAN_TSR_ABRQ1_Msk (0x1UL << CAN_TSR_ABRQ1_Pos)
2012#define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk
2013#define CAN_TSR_RQCP2_Pos (16U)
2014#define CAN_TSR_RQCP2_Msk (0x1UL << CAN_TSR_RQCP2_Pos)
2015#define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk
2016#define CAN_TSR_TXOK2_Pos (17U)
2017#define CAN_TSR_TXOK2_Msk (0x1UL << CAN_TSR_TXOK2_Pos)
2018#define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk
2019#define CAN_TSR_ALST2_Pos (18U)
2020#define CAN_TSR_ALST2_Msk (0x1UL << CAN_TSR_ALST2_Pos)
2021#define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk
2022#define CAN_TSR_TERR2_Pos (19U)
2023#define CAN_TSR_TERR2_Msk (0x1UL << CAN_TSR_TERR2_Pos)
2024#define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk
2025#define CAN_TSR_ABRQ2_Pos (23U)
2026#define CAN_TSR_ABRQ2_Msk (0x1UL << CAN_TSR_ABRQ2_Pos)
2027#define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk
2028#define CAN_TSR_CODE_Pos (24U)
2029#define CAN_TSR_CODE_Msk (0x3UL << CAN_TSR_CODE_Pos)
2030#define CAN_TSR_CODE CAN_TSR_CODE_Msk
2031
2032#define CAN_TSR_TME_Pos (26U)
2033#define CAN_TSR_TME_Msk (0x7UL << CAN_TSR_TME_Pos)
2034#define CAN_TSR_TME CAN_TSR_TME_Msk
2035#define CAN_TSR_TME0_Pos (26U)
2036#define CAN_TSR_TME0_Msk (0x1UL << CAN_TSR_TME0_Pos)
2037#define CAN_TSR_TME0 CAN_TSR_TME0_Msk
2038#define CAN_TSR_TME1_Pos (27U)
2039#define CAN_TSR_TME1_Msk (0x1UL << CAN_TSR_TME1_Pos)
2040#define CAN_TSR_TME1 CAN_TSR_TME1_Msk
2041#define CAN_TSR_TME2_Pos (28U)
2042#define CAN_TSR_TME2_Msk (0x1UL << CAN_TSR_TME2_Pos)
2043#define CAN_TSR_TME2 CAN_TSR_TME2_Msk
2044
2045#define CAN_TSR_LOW_Pos (29U)
2046#define CAN_TSR_LOW_Msk (0x7UL << CAN_TSR_LOW_Pos)
2047#define CAN_TSR_LOW CAN_TSR_LOW_Msk
2048#define CAN_TSR_LOW0_Pos (29U)
2049#define CAN_TSR_LOW0_Msk (0x1UL << CAN_TSR_LOW0_Pos)
2050#define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk
2051#define CAN_TSR_LOW1_Pos (30U)
2052#define CAN_TSR_LOW1_Msk (0x1UL << CAN_TSR_LOW1_Pos)
2053#define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk
2054#define CAN_TSR_LOW2_Pos (31U)
2055#define CAN_TSR_LOW2_Msk (0x1UL << CAN_TSR_LOW2_Pos)
2056#define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk
2057
2058/******************* Bit definition for CAN_RF0R register *******************/
2059#define CAN_RF0R_FMP0_Pos (0U)
2060#define CAN_RF0R_FMP0_Msk (0x3UL << CAN_RF0R_FMP0_Pos)
2061#define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk
2062#define CAN_RF0R_FULL0_Pos (3U)
2063#define CAN_RF0R_FULL0_Msk (0x1UL << CAN_RF0R_FULL0_Pos)
2064#define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk
2065#define CAN_RF0R_FOVR0_Pos (4U)
2066#define CAN_RF0R_FOVR0_Msk (0x1UL << CAN_RF0R_FOVR0_Pos)
2067#define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk
2068#define CAN_RF0R_RFOM0_Pos (5U)
2069#define CAN_RF0R_RFOM0_Msk (0x1UL << CAN_RF0R_RFOM0_Pos)
2070#define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk
2071
2072/******************* Bit definition for CAN_RF1R register *******************/
2073#define CAN_RF1R_FMP1_Pos (0U)
2074#define CAN_RF1R_FMP1_Msk (0x3UL << CAN_RF1R_FMP1_Pos)
2075#define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk
2076#define CAN_RF1R_FULL1_Pos (3U)
2077#define CAN_RF1R_FULL1_Msk (0x1UL << CAN_RF1R_FULL1_Pos)
2078#define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk
2079#define CAN_RF1R_FOVR1_Pos (4U)
2080#define CAN_RF1R_FOVR1_Msk (0x1UL << CAN_RF1R_FOVR1_Pos)
2081#define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk
2082#define CAN_RF1R_RFOM1_Pos (5U)
2083#define CAN_RF1R_RFOM1_Msk (0x1UL << CAN_RF1R_RFOM1_Pos)
2084#define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk
2085
2086/******************** Bit definition for CAN_IER register *******************/
2087#define CAN_IER_TMEIE_Pos (0U)
2088#define CAN_IER_TMEIE_Msk (0x1UL << CAN_IER_TMEIE_Pos)
2089#define CAN_IER_TMEIE CAN_IER_TMEIE_Msk
2090#define CAN_IER_FMPIE0_Pos (1U)
2091#define CAN_IER_FMPIE0_Msk (0x1UL << CAN_IER_FMPIE0_Pos)
2092#define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk
2093#define CAN_IER_FFIE0_Pos (2U)
2094#define CAN_IER_FFIE0_Msk (0x1UL << CAN_IER_FFIE0_Pos)
2095#define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk
2096#define CAN_IER_FOVIE0_Pos (3U)
2097#define CAN_IER_FOVIE0_Msk (0x1UL << CAN_IER_FOVIE0_Pos)
2098#define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk
2099#define CAN_IER_FMPIE1_Pos (4U)
2100#define CAN_IER_FMPIE1_Msk (0x1UL << CAN_IER_FMPIE1_Pos)
2101#define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk
2102#define CAN_IER_FFIE1_Pos (5U)
2103#define CAN_IER_FFIE1_Msk (0x1UL << CAN_IER_FFIE1_Pos)
2104#define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk
2105#define CAN_IER_FOVIE1_Pos (6U)
2106#define CAN_IER_FOVIE1_Msk (0x1UL << CAN_IER_FOVIE1_Pos)
2107#define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk
2108#define CAN_IER_EWGIE_Pos (8U)
2109#define CAN_IER_EWGIE_Msk (0x1UL << CAN_IER_EWGIE_Pos)
2110#define CAN_IER_EWGIE CAN_IER_EWGIE_Msk
2111#define CAN_IER_EPVIE_Pos (9U)
2112#define CAN_IER_EPVIE_Msk (0x1UL << CAN_IER_EPVIE_Pos)
2113#define CAN_IER_EPVIE CAN_IER_EPVIE_Msk
2114#define CAN_IER_BOFIE_Pos (10U)
2115#define CAN_IER_BOFIE_Msk (0x1UL << CAN_IER_BOFIE_Pos)
2116#define CAN_IER_BOFIE CAN_IER_BOFIE_Msk
2117#define CAN_IER_LECIE_Pos (11U)
2118#define CAN_IER_LECIE_Msk (0x1UL << CAN_IER_LECIE_Pos)
2119#define CAN_IER_LECIE CAN_IER_LECIE_Msk
2120#define CAN_IER_ERRIE_Pos (15U)
2121#define CAN_IER_ERRIE_Msk (0x1UL << CAN_IER_ERRIE_Pos)
2122#define CAN_IER_ERRIE CAN_IER_ERRIE_Msk
2123#define CAN_IER_WKUIE_Pos (16U)
2124#define CAN_IER_WKUIE_Msk (0x1UL << CAN_IER_WKUIE_Pos)
2125#define CAN_IER_WKUIE CAN_IER_WKUIE_Msk
2126#define CAN_IER_SLKIE_Pos (17U)
2127#define CAN_IER_SLKIE_Msk (0x1UL << CAN_IER_SLKIE_Pos)
2128#define CAN_IER_SLKIE CAN_IER_SLKIE_Msk
2129#define CAN_IER_EWGIE_Pos (8U)
2130
2131/******************** Bit definition for CAN_ESR register *******************/
2132#define CAN_ESR_EWGF_Pos (0U)
2133#define CAN_ESR_EWGF_Msk (0x1UL << CAN_ESR_EWGF_Pos)
2134#define CAN_ESR_EWGF CAN_ESR_EWGF_Msk
2135#define CAN_ESR_EPVF_Pos (1U)
2136#define CAN_ESR_EPVF_Msk (0x1UL << CAN_ESR_EPVF_Pos)
2137#define CAN_ESR_EPVF CAN_ESR_EPVF_Msk
2138#define CAN_ESR_BOFF_Pos (2U)
2139#define CAN_ESR_BOFF_Msk (0x1UL << CAN_ESR_BOFF_Pos)
2140#define CAN_ESR_BOFF CAN_ESR_BOFF_Msk
2141
2142#define CAN_ESR_LEC_Pos (4U)
2143#define CAN_ESR_LEC_Msk (0x7UL << CAN_ESR_LEC_Pos)
2144#define CAN_ESR_LEC CAN_ESR_LEC_Msk
2145#define CAN_ESR_LEC_0 (0x1UL << CAN_ESR_LEC_Pos)
2146#define CAN_ESR_LEC_1 (0x2UL << CAN_ESR_LEC_Pos)
2147#define CAN_ESR_LEC_2 (0x4UL << CAN_ESR_LEC_Pos)
2148
2149#define CAN_ESR_TEC_Pos (16U)
2150#define CAN_ESR_TEC_Msk (0xFFUL << CAN_ESR_TEC_Pos)
2151#define CAN_ESR_TEC CAN_ESR_TEC_Msk
2152#define CAN_ESR_REC_Pos (24U)
2153#define CAN_ESR_REC_Msk (0xFFUL << CAN_ESR_REC_Pos)
2154#define CAN_ESR_REC CAN_ESR_REC_Msk
2155
2156/******************* Bit definition for CAN_BTR register ********************/
2157#define CAN_BTR_BRP_Pos (0U)
2158#define CAN_BTR_BRP_Msk (0x3FFUL << CAN_BTR_BRP_Pos)
2159#define CAN_BTR_BRP CAN_BTR_BRP_Msk
2160#define CAN_BTR_TS1_Pos (16U)
2161#define CAN_BTR_TS1_Msk (0xFUL << CAN_BTR_TS1_Pos)
2162#define CAN_BTR_TS1 CAN_BTR_TS1_Msk
2163#define CAN_BTR_TS1_0 (0x1UL << CAN_BTR_TS1_Pos)
2164#define CAN_BTR_TS1_1 (0x2UL << CAN_BTR_TS1_Pos)
2165#define CAN_BTR_TS1_2 (0x4UL << CAN_BTR_TS1_Pos)
2166#define CAN_BTR_TS1_3 (0x8UL << CAN_BTR_TS1_Pos)
2167#define CAN_BTR_TS2_Pos (20U)
2168#define CAN_BTR_TS2_Msk (0x7UL << CAN_BTR_TS2_Pos)
2169#define CAN_BTR_TS2 CAN_BTR_TS2_Msk
2170#define CAN_BTR_TS2_0 (0x1UL << CAN_BTR_TS2_Pos)
2171#define CAN_BTR_TS2_1 (0x2UL << CAN_BTR_TS2_Pos)
2172#define CAN_BTR_TS2_2 (0x4UL << CAN_BTR_TS2_Pos)
2173#define CAN_BTR_SJW_Pos (24U)
2174#define CAN_BTR_SJW_Msk (0x3UL << CAN_BTR_SJW_Pos)
2175#define CAN_BTR_SJW CAN_BTR_SJW_Msk
2176#define CAN_BTR_SJW_0 (0x1UL << CAN_BTR_SJW_Pos)
2177#define CAN_BTR_SJW_1 (0x2UL << CAN_BTR_SJW_Pos)
2178#define CAN_BTR_LBKM_Pos (30U)
2179#define CAN_BTR_LBKM_Msk (0x1UL << CAN_BTR_LBKM_Pos)
2180#define CAN_BTR_LBKM CAN_BTR_LBKM_Msk
2181#define CAN_BTR_SILM_Pos (31U)
2182#define CAN_BTR_SILM_Msk (0x1UL << CAN_BTR_SILM_Pos)
2183#define CAN_BTR_SILM CAN_BTR_SILM_Msk
2184
2185
2187/****************** Bit definition for CAN_TI0R register ********************/
2188#define CAN_TI0R_TXRQ_Pos (0U)
2189#define CAN_TI0R_TXRQ_Msk (0x1UL << CAN_TI0R_TXRQ_Pos)
2190#define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk
2191#define CAN_TI0R_RTR_Pos (1U)
2192#define CAN_TI0R_RTR_Msk (0x1UL << CAN_TI0R_RTR_Pos)
2193#define CAN_TI0R_RTR CAN_TI0R_RTR_Msk
2194#define CAN_TI0R_IDE_Pos (2U)
2195#define CAN_TI0R_IDE_Msk (0x1UL << CAN_TI0R_IDE_Pos)
2196#define CAN_TI0R_IDE CAN_TI0R_IDE_Msk
2197#define CAN_TI0R_EXID_Pos (3U)
2198#define CAN_TI0R_EXID_Msk (0x3FFFFUL << CAN_TI0R_EXID_Pos)
2199#define CAN_TI0R_EXID CAN_TI0R_EXID_Msk
2200#define CAN_TI0R_STID_Pos (21U)
2201#define CAN_TI0R_STID_Msk (0x7FFUL << CAN_TI0R_STID_Pos)
2202#define CAN_TI0R_STID CAN_TI0R_STID_Msk
2203
2204/****************** Bit definition for CAN_TDT0R register *******************/
2205#define CAN_TDT0R_DLC_Pos (0U)
2206#define CAN_TDT0R_DLC_Msk (0xFUL << CAN_TDT0R_DLC_Pos)
2207#define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk
2208#define CAN_TDT0R_TGT_Pos (8U)
2209#define CAN_TDT0R_TGT_Msk (0x1UL << CAN_TDT0R_TGT_Pos)
2210#define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk
2211#define CAN_TDT0R_TIME_Pos (16U)
2212#define CAN_TDT0R_TIME_Msk (0xFFFFUL << CAN_TDT0R_TIME_Pos)
2213#define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk
2214
2215/****************** Bit definition for CAN_TDL0R register *******************/
2216#define CAN_TDL0R_DATA0_Pos (0U)
2217#define CAN_TDL0R_DATA0_Msk (0xFFUL << CAN_TDL0R_DATA0_Pos)
2218#define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk
2219#define CAN_TDL0R_DATA1_Pos (8U)
2220#define CAN_TDL0R_DATA1_Msk (0xFFUL << CAN_TDL0R_DATA1_Pos)
2221#define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk
2222#define CAN_TDL0R_DATA2_Pos (16U)
2223#define CAN_TDL0R_DATA2_Msk (0xFFUL << CAN_TDL0R_DATA2_Pos)
2224#define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk
2225#define CAN_TDL0R_DATA3_Pos (24U)
2226#define CAN_TDL0R_DATA3_Msk (0xFFUL << CAN_TDL0R_DATA3_Pos)
2227#define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk
2228
2229/****************** Bit definition for CAN_TDH0R register *******************/
2230#define CAN_TDH0R_DATA4_Pos (0U)
2231#define CAN_TDH0R_DATA4_Msk (0xFFUL << CAN_TDH0R_DATA4_Pos)
2232#define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk
2233#define CAN_TDH0R_DATA5_Pos (8U)
2234#define CAN_TDH0R_DATA5_Msk (0xFFUL << CAN_TDH0R_DATA5_Pos)
2235#define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk
2236#define CAN_TDH0R_DATA6_Pos (16U)
2237#define CAN_TDH0R_DATA6_Msk (0xFFUL << CAN_TDH0R_DATA6_Pos)
2238#define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk
2239#define CAN_TDH0R_DATA7_Pos (24U)
2240#define CAN_TDH0R_DATA7_Msk (0xFFUL << CAN_TDH0R_DATA7_Pos)
2241#define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk
2242
2243/******************* Bit definition for CAN_TI1R register *******************/
2244#define CAN_TI1R_TXRQ_Pos (0U)
2245#define CAN_TI1R_TXRQ_Msk (0x1UL << CAN_TI1R_TXRQ_Pos)
2246#define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk
2247#define CAN_TI1R_RTR_Pos (1U)
2248#define CAN_TI1R_RTR_Msk (0x1UL << CAN_TI1R_RTR_Pos)
2249#define CAN_TI1R_RTR CAN_TI1R_RTR_Msk
2250#define CAN_TI1R_IDE_Pos (2U)
2251#define CAN_TI1R_IDE_Msk (0x1UL << CAN_TI1R_IDE_Pos)
2252#define CAN_TI1R_IDE CAN_TI1R_IDE_Msk
2253#define CAN_TI1R_EXID_Pos (3U)
2254#define CAN_TI1R_EXID_Msk (0x3FFFFUL << CAN_TI1R_EXID_Pos)
2255#define CAN_TI1R_EXID CAN_TI1R_EXID_Msk
2256#define CAN_TI1R_STID_Pos (21U)
2257#define CAN_TI1R_STID_Msk (0x7FFUL << CAN_TI1R_STID_Pos)
2258#define CAN_TI1R_STID CAN_TI1R_STID_Msk
2259
2260/******************* Bit definition for CAN_TDT1R register ******************/
2261#define CAN_TDT1R_DLC_Pos (0U)
2262#define CAN_TDT1R_DLC_Msk (0xFUL << CAN_TDT1R_DLC_Pos)
2263#define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk
2264#define CAN_TDT1R_TGT_Pos (8U)
2265#define CAN_TDT1R_TGT_Msk (0x1UL << CAN_TDT1R_TGT_Pos)
2266#define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk
2267#define CAN_TDT1R_TIME_Pos (16U)
2268#define CAN_TDT1R_TIME_Msk (0xFFFFUL << CAN_TDT1R_TIME_Pos)
2269#define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk
2270
2271/******************* Bit definition for CAN_TDL1R register ******************/
2272#define CAN_TDL1R_DATA0_Pos (0U)
2273#define CAN_TDL1R_DATA0_Msk (0xFFUL << CAN_TDL1R_DATA0_Pos)
2274#define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk
2275#define CAN_TDL1R_DATA1_Pos (8U)
2276#define CAN_TDL1R_DATA1_Msk (0xFFUL << CAN_TDL1R_DATA1_Pos)
2277#define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk
2278#define CAN_TDL1R_DATA2_Pos (16U)
2279#define CAN_TDL1R_DATA2_Msk (0xFFUL << CAN_TDL1R_DATA2_Pos)
2280#define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk
2281#define CAN_TDL1R_DATA3_Pos (24U)
2282#define CAN_TDL1R_DATA3_Msk (0xFFUL << CAN_TDL1R_DATA3_Pos)
2283#define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk
2284
2285/******************* Bit definition for CAN_TDH1R register ******************/
2286#define CAN_TDH1R_DATA4_Pos (0U)
2287#define CAN_TDH1R_DATA4_Msk (0xFFUL << CAN_TDH1R_DATA4_Pos)
2288#define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk
2289#define CAN_TDH1R_DATA5_Pos (8U)
2290#define CAN_TDH1R_DATA5_Msk (0xFFUL << CAN_TDH1R_DATA5_Pos)
2291#define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk
2292#define CAN_TDH1R_DATA6_Pos (16U)
2293#define CAN_TDH1R_DATA6_Msk (0xFFUL << CAN_TDH1R_DATA6_Pos)
2294#define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk
2295#define CAN_TDH1R_DATA7_Pos (24U)
2296#define CAN_TDH1R_DATA7_Msk (0xFFUL << CAN_TDH1R_DATA7_Pos)
2297#define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk
2298
2299/******************* Bit definition for CAN_TI2R register *******************/
2300#define CAN_TI2R_TXRQ_Pos (0U)
2301#define CAN_TI2R_TXRQ_Msk (0x1UL << CAN_TI2R_TXRQ_Pos)
2302#define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk
2303#define CAN_TI2R_RTR_Pos (1U)
2304#define CAN_TI2R_RTR_Msk (0x1UL << CAN_TI2R_RTR_Pos)
2305#define CAN_TI2R_RTR CAN_TI2R_RTR_Msk
2306#define CAN_TI2R_IDE_Pos (2U)
2307#define CAN_TI2R_IDE_Msk (0x1UL << CAN_TI2R_IDE_Pos)
2308#define CAN_TI2R_IDE CAN_TI2R_IDE_Msk
2309#define CAN_TI2R_EXID_Pos (3U)
2310#define CAN_TI2R_EXID_Msk (0x3FFFFUL << CAN_TI2R_EXID_Pos)
2311#define CAN_TI2R_EXID CAN_TI2R_EXID_Msk
2312#define CAN_TI2R_STID_Pos (21U)
2313#define CAN_TI2R_STID_Msk (0x7FFUL << CAN_TI2R_STID_Pos)
2314#define CAN_TI2R_STID CAN_TI2R_STID_Msk
2315
2316/******************* Bit definition for CAN_TDT2R register ******************/
2317#define CAN_TDT2R_DLC_Pos (0U)
2318#define CAN_TDT2R_DLC_Msk (0xFUL << CAN_TDT2R_DLC_Pos)
2319#define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk
2320#define CAN_TDT2R_TGT_Pos (8U)
2321#define CAN_TDT2R_TGT_Msk (0x1UL << CAN_TDT2R_TGT_Pos)
2322#define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk
2323#define CAN_TDT2R_TIME_Pos (16U)
2324#define CAN_TDT2R_TIME_Msk (0xFFFFUL << CAN_TDT2R_TIME_Pos)
2325#define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk
2326
2327/******************* Bit definition for CAN_TDL2R register ******************/
2328#define CAN_TDL2R_DATA0_Pos (0U)
2329#define CAN_TDL2R_DATA0_Msk (0xFFUL << CAN_TDL2R_DATA0_Pos)
2330#define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk
2331#define CAN_TDL2R_DATA1_Pos (8U)
2332#define CAN_TDL2R_DATA1_Msk (0xFFUL << CAN_TDL2R_DATA1_Pos)
2333#define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk
2334#define CAN_TDL2R_DATA2_Pos (16U)
2335#define CAN_TDL2R_DATA2_Msk (0xFFUL << CAN_TDL2R_DATA2_Pos)
2336#define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk
2337#define CAN_TDL2R_DATA3_Pos (24U)
2338#define CAN_TDL2R_DATA3_Msk (0xFFUL << CAN_TDL2R_DATA3_Pos)
2339#define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk
2340
2341/******************* Bit definition for CAN_TDH2R register ******************/
2342#define CAN_TDH2R_DATA4_Pos (0U)
2343#define CAN_TDH2R_DATA4_Msk (0xFFUL << CAN_TDH2R_DATA4_Pos)
2344#define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk
2345#define CAN_TDH2R_DATA5_Pos (8U)
2346#define CAN_TDH2R_DATA5_Msk (0xFFUL << CAN_TDH2R_DATA5_Pos)
2347#define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk
2348#define CAN_TDH2R_DATA6_Pos (16U)
2349#define CAN_TDH2R_DATA6_Msk (0xFFUL << CAN_TDH2R_DATA6_Pos)
2350#define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk
2351#define CAN_TDH2R_DATA7_Pos (24U)
2352#define CAN_TDH2R_DATA7_Msk (0xFFUL << CAN_TDH2R_DATA7_Pos)
2353#define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk
2354
2355/******************* Bit definition for CAN_RI0R register *******************/
2356#define CAN_RI0R_RTR_Pos (1U)
2357#define CAN_RI0R_RTR_Msk (0x1UL << CAN_RI0R_RTR_Pos)
2358#define CAN_RI0R_RTR CAN_RI0R_RTR_Msk
2359#define CAN_RI0R_IDE_Pos (2U)
2360#define CAN_RI0R_IDE_Msk (0x1UL << CAN_RI0R_IDE_Pos)
2361#define CAN_RI0R_IDE CAN_RI0R_IDE_Msk
2362#define CAN_RI0R_EXID_Pos (3U)
2363#define CAN_RI0R_EXID_Msk (0x3FFFFUL << CAN_RI0R_EXID_Pos)
2364#define CAN_RI0R_EXID CAN_RI0R_EXID_Msk
2365#define CAN_RI0R_STID_Pos (21U)
2366#define CAN_RI0R_STID_Msk (0x7FFUL << CAN_RI0R_STID_Pos)
2367#define CAN_RI0R_STID CAN_RI0R_STID_Msk
2368
2369/******************* Bit definition for CAN_RDT0R register ******************/
2370#define CAN_RDT0R_DLC_Pos (0U)
2371#define CAN_RDT0R_DLC_Msk (0xFUL << CAN_RDT0R_DLC_Pos)
2372#define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk
2373#define CAN_RDT0R_FMI_Pos (8U)
2374#define CAN_RDT0R_FMI_Msk (0xFFUL << CAN_RDT0R_FMI_Pos)
2375#define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk
2376#define CAN_RDT0R_TIME_Pos (16U)
2377#define CAN_RDT0R_TIME_Msk (0xFFFFUL << CAN_RDT0R_TIME_Pos)
2378#define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk
2379
2380/******************* Bit definition for CAN_RDL0R register ******************/
2381#define CAN_RDL0R_DATA0_Pos (0U)
2382#define CAN_RDL0R_DATA0_Msk (0xFFUL << CAN_RDL0R_DATA0_Pos)
2383#define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk
2384#define CAN_RDL0R_DATA1_Pos (8U)
2385#define CAN_RDL0R_DATA1_Msk (0xFFUL << CAN_RDL0R_DATA1_Pos)
2386#define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk
2387#define CAN_RDL0R_DATA2_Pos (16U)
2388#define CAN_RDL0R_DATA2_Msk (0xFFUL << CAN_RDL0R_DATA2_Pos)
2389#define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk
2390#define CAN_RDL0R_DATA3_Pos (24U)
2391#define CAN_RDL0R_DATA3_Msk (0xFFUL << CAN_RDL0R_DATA3_Pos)
2392#define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk
2393
2394/******************* Bit definition for CAN_RDH0R register ******************/
2395#define CAN_RDH0R_DATA4_Pos (0U)
2396#define CAN_RDH0R_DATA4_Msk (0xFFUL << CAN_RDH0R_DATA4_Pos)
2397#define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk
2398#define CAN_RDH0R_DATA5_Pos (8U)
2399#define CAN_RDH0R_DATA5_Msk (0xFFUL << CAN_RDH0R_DATA5_Pos)
2400#define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk
2401#define CAN_RDH0R_DATA6_Pos (16U)
2402#define CAN_RDH0R_DATA6_Msk (0xFFUL << CAN_RDH0R_DATA6_Pos)
2403#define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk
2404#define CAN_RDH0R_DATA7_Pos (24U)
2405#define CAN_RDH0R_DATA7_Msk (0xFFUL << CAN_RDH0R_DATA7_Pos)
2406#define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk
2407
2408/******************* Bit definition for CAN_RI1R register *******************/
2409#define CAN_RI1R_RTR_Pos (1U)
2410#define CAN_RI1R_RTR_Msk (0x1UL << CAN_RI1R_RTR_Pos)
2411#define CAN_RI1R_RTR CAN_RI1R_RTR_Msk
2412#define CAN_RI1R_IDE_Pos (2U)
2413#define CAN_RI1R_IDE_Msk (0x1UL << CAN_RI1R_IDE_Pos)
2414#define CAN_RI1R_IDE CAN_RI1R_IDE_Msk
2415#define CAN_RI1R_EXID_Pos (3U)
2416#define CAN_RI1R_EXID_Msk (0x3FFFFUL << CAN_RI1R_EXID_Pos)
2417#define CAN_RI1R_EXID CAN_RI1R_EXID_Msk
2418#define CAN_RI1R_STID_Pos (21U)
2419#define CAN_RI1R_STID_Msk (0x7FFUL << CAN_RI1R_STID_Pos)
2420#define CAN_RI1R_STID CAN_RI1R_STID_Msk
2421
2422/******************* Bit definition for CAN_RDT1R register ******************/
2423#define CAN_RDT1R_DLC_Pos (0U)
2424#define CAN_RDT1R_DLC_Msk (0xFUL << CAN_RDT1R_DLC_Pos)
2425#define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk
2426#define CAN_RDT1R_FMI_Pos (8U)
2427#define CAN_RDT1R_FMI_Msk (0xFFUL << CAN_RDT1R_FMI_Pos)
2428#define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk
2429#define CAN_RDT1R_TIME_Pos (16U)
2430#define CAN_RDT1R_TIME_Msk (0xFFFFUL << CAN_RDT1R_TIME_Pos)
2431#define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk
2432
2433/******************* Bit definition for CAN_RDL1R register ******************/
2434#define CAN_RDL1R_DATA0_Pos (0U)
2435#define CAN_RDL1R_DATA0_Msk (0xFFUL << CAN_RDL1R_DATA0_Pos)
2436#define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk
2437#define CAN_RDL1R_DATA1_Pos (8U)
2438#define CAN_RDL1R_DATA1_Msk (0xFFUL << CAN_RDL1R_DATA1_Pos)
2439#define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk
2440#define CAN_RDL1R_DATA2_Pos (16U)
2441#define CAN_RDL1R_DATA2_Msk (0xFFUL << CAN_RDL1R_DATA2_Pos)
2442#define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk
2443#define CAN_RDL1R_DATA3_Pos (24U)
2444#define CAN_RDL1R_DATA3_Msk (0xFFUL << CAN_RDL1R_DATA3_Pos)
2445#define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk
2446
2447/******************* Bit definition for CAN_RDH1R register ******************/
2448#define CAN_RDH1R_DATA4_Pos (0U)
2449#define CAN_RDH1R_DATA4_Msk (0xFFUL << CAN_RDH1R_DATA4_Pos)
2450#define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk
2451#define CAN_RDH1R_DATA5_Pos (8U)
2452#define CAN_RDH1R_DATA5_Msk (0xFFUL << CAN_RDH1R_DATA5_Pos)
2453#define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk
2454#define CAN_RDH1R_DATA6_Pos (16U)
2455#define CAN_RDH1R_DATA6_Msk (0xFFUL << CAN_RDH1R_DATA6_Pos)
2456#define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk
2457#define CAN_RDH1R_DATA7_Pos (24U)
2458#define CAN_RDH1R_DATA7_Msk (0xFFUL << CAN_RDH1R_DATA7_Pos)
2459#define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk
2460
2462/******************* Bit definition for CAN_FMR register ********************/
2463#define CAN_FMR_FINIT_Pos (0U)
2464#define CAN_FMR_FINIT_Msk (0x1UL << CAN_FMR_FINIT_Pos)
2465#define CAN_FMR_FINIT CAN_FMR_FINIT_Msk
2466#define CAN_FMR_CAN2SB_Pos (8U)
2467#define CAN_FMR_CAN2SB_Msk (0x3FUL << CAN_FMR_CAN2SB_Pos)
2468#define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk
2469
2470/******************* Bit definition for CAN_FM1R register *******************/
2471#define CAN_FM1R_FBM_Pos (0U)
2472#define CAN_FM1R_FBM_Msk (0xFFFFFFFUL << CAN_FM1R_FBM_Pos)
2473#define CAN_FM1R_FBM CAN_FM1R_FBM_Msk
2474#define CAN_FM1R_FBM0_Pos (0U)
2475#define CAN_FM1R_FBM0_Msk (0x1UL << CAN_FM1R_FBM0_Pos)
2476#define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk
2477#define CAN_FM1R_FBM1_Pos (1U)
2478#define CAN_FM1R_FBM1_Msk (0x1UL << CAN_FM1R_FBM1_Pos)
2479#define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk
2480#define CAN_FM1R_FBM2_Pos (2U)
2481#define CAN_FM1R_FBM2_Msk (0x1UL << CAN_FM1R_FBM2_Pos)
2482#define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk
2483#define CAN_FM1R_FBM3_Pos (3U)
2484#define CAN_FM1R_FBM3_Msk (0x1UL << CAN_FM1R_FBM3_Pos)
2485#define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk
2486#define CAN_FM1R_FBM4_Pos (4U)
2487#define CAN_FM1R_FBM4_Msk (0x1UL << CAN_FM1R_FBM4_Pos)
2488#define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk
2489#define CAN_FM1R_FBM5_Pos (5U)
2490#define CAN_FM1R_FBM5_Msk (0x1UL << CAN_FM1R_FBM5_Pos)
2491#define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk
2492#define CAN_FM1R_FBM6_Pos (6U)
2493#define CAN_FM1R_FBM6_Msk (0x1UL << CAN_FM1R_FBM6_Pos)
2494#define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk
2495#define CAN_FM1R_FBM7_Pos (7U)
2496#define CAN_FM1R_FBM7_Msk (0x1UL << CAN_FM1R_FBM7_Pos)
2497#define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk
2498#define CAN_FM1R_FBM8_Pos (8U)
2499#define CAN_FM1R_FBM8_Msk (0x1UL << CAN_FM1R_FBM8_Pos)
2500#define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk
2501#define CAN_FM1R_FBM9_Pos (9U)
2502#define CAN_FM1R_FBM9_Msk (0x1UL << CAN_FM1R_FBM9_Pos)
2503#define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk
2504#define CAN_FM1R_FBM10_Pos (10U)
2505#define CAN_FM1R_FBM10_Msk (0x1UL << CAN_FM1R_FBM10_Pos)
2506#define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk
2507#define CAN_FM1R_FBM11_Pos (11U)
2508#define CAN_FM1R_FBM11_Msk (0x1UL << CAN_FM1R_FBM11_Pos)
2509#define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk
2510#define CAN_FM1R_FBM12_Pos (12U)
2511#define CAN_FM1R_FBM12_Msk (0x1UL << CAN_FM1R_FBM12_Pos)
2512#define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk
2513#define CAN_FM1R_FBM13_Pos (13U)
2514#define CAN_FM1R_FBM13_Msk (0x1UL << CAN_FM1R_FBM13_Pos)
2515#define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk
2516#define CAN_FM1R_FBM14_Pos (14U)
2517#define CAN_FM1R_FBM14_Msk (0x1UL << CAN_FM1R_FBM14_Pos)
2518#define CAN_FM1R_FBM14 CAN_FM1R_FBM14_Msk
2519#define CAN_FM1R_FBM15_Pos (15U)
2520#define CAN_FM1R_FBM15_Msk (0x1UL << CAN_FM1R_FBM15_Pos)
2521#define CAN_FM1R_FBM15 CAN_FM1R_FBM15_Msk
2522#define CAN_FM1R_FBM16_Pos (16U)
2523#define CAN_FM1R_FBM16_Msk (0x1UL << CAN_FM1R_FBM16_Pos)
2524#define CAN_FM1R_FBM16 CAN_FM1R_FBM16_Msk
2525#define CAN_FM1R_FBM17_Pos (17U)
2526#define CAN_FM1R_FBM17_Msk (0x1UL << CAN_FM1R_FBM17_Pos)
2527#define CAN_FM1R_FBM17 CAN_FM1R_FBM17_Msk
2528#define CAN_FM1R_FBM18_Pos (18U)
2529#define CAN_FM1R_FBM18_Msk (0x1UL << CAN_FM1R_FBM18_Pos)
2530#define CAN_FM1R_FBM18 CAN_FM1R_FBM18_Msk
2531#define CAN_FM1R_FBM19_Pos (19U)
2532#define CAN_FM1R_FBM19_Msk (0x1UL << CAN_FM1R_FBM19_Pos)
2533#define CAN_FM1R_FBM19 CAN_FM1R_FBM19_Msk
2534#define CAN_FM1R_FBM20_Pos (20U)
2535#define CAN_FM1R_FBM20_Msk (0x1UL << CAN_FM1R_FBM20_Pos)
2536#define CAN_FM1R_FBM20 CAN_FM1R_FBM20_Msk
2537#define CAN_FM1R_FBM21_Pos (21U)
2538#define CAN_FM1R_FBM21_Msk (0x1UL << CAN_FM1R_FBM21_Pos)
2539#define CAN_FM1R_FBM21 CAN_FM1R_FBM21_Msk
2540#define CAN_FM1R_FBM22_Pos (22U)
2541#define CAN_FM1R_FBM22_Msk (0x1UL << CAN_FM1R_FBM22_Pos)
2542#define CAN_FM1R_FBM22 CAN_FM1R_FBM22_Msk
2543#define CAN_FM1R_FBM23_Pos (23U)
2544#define CAN_FM1R_FBM23_Msk (0x1UL << CAN_FM1R_FBM23_Pos)
2545#define CAN_FM1R_FBM23 CAN_FM1R_FBM23_Msk
2546#define CAN_FM1R_FBM24_Pos (24U)
2547#define CAN_FM1R_FBM24_Msk (0x1UL << CAN_FM1R_FBM24_Pos)
2548#define CAN_FM1R_FBM24 CAN_FM1R_FBM24_Msk
2549#define CAN_FM1R_FBM25_Pos (25U)
2550#define CAN_FM1R_FBM25_Msk (0x1UL << CAN_FM1R_FBM25_Pos)
2551#define CAN_FM1R_FBM25 CAN_FM1R_FBM25_Msk
2552#define CAN_FM1R_FBM26_Pos (26U)
2553#define CAN_FM1R_FBM26_Msk (0x1UL << CAN_FM1R_FBM26_Pos)
2554#define CAN_FM1R_FBM26 CAN_FM1R_FBM26_Msk
2555#define CAN_FM1R_FBM27_Pos (27U)
2556#define CAN_FM1R_FBM27_Msk (0x1UL << CAN_FM1R_FBM27_Pos)
2557#define CAN_FM1R_FBM27 CAN_FM1R_FBM27_Msk
2558
2559/******************* Bit definition for CAN_FS1R register *******************/
2560#define CAN_FS1R_FSC_Pos (0U)
2561#define CAN_FS1R_FSC_Msk (0xFFFFFFFUL << CAN_FS1R_FSC_Pos)
2562#define CAN_FS1R_FSC CAN_FS1R_FSC_Msk
2563#define CAN_FS1R_FSC0_Pos (0U)
2564#define CAN_FS1R_FSC0_Msk (0x1UL << CAN_FS1R_FSC0_Pos)
2565#define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk
2566#define CAN_FS1R_FSC1_Pos (1U)
2567#define CAN_FS1R_FSC1_Msk (0x1UL << CAN_FS1R_FSC1_Pos)
2568#define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk
2569#define CAN_FS1R_FSC2_Pos (2U)
2570#define CAN_FS1R_FSC2_Msk (0x1UL << CAN_FS1R_FSC2_Pos)
2571#define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk
2572#define CAN_FS1R_FSC3_Pos (3U)
2573#define CAN_FS1R_FSC3_Msk (0x1UL << CAN_FS1R_FSC3_Pos)
2574#define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk
2575#define CAN_FS1R_FSC4_Pos (4U)
2576#define CAN_FS1R_FSC4_Msk (0x1UL << CAN_FS1R_FSC4_Pos)
2577#define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk
2578#define CAN_FS1R_FSC5_Pos (5U)
2579#define CAN_FS1R_FSC5_Msk (0x1UL << CAN_FS1R_FSC5_Pos)
2580#define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk
2581#define CAN_FS1R_FSC6_Pos (6U)
2582#define CAN_FS1R_FSC6_Msk (0x1UL << CAN_FS1R_FSC6_Pos)
2583#define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk
2584#define CAN_FS1R_FSC7_Pos (7U)
2585#define CAN_FS1R_FSC7_Msk (0x1UL << CAN_FS1R_FSC7_Pos)
2586#define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk
2587#define CAN_FS1R_FSC8_Pos (8U)
2588#define CAN_FS1R_FSC8_Msk (0x1UL << CAN_FS1R_FSC8_Pos)
2589#define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk
2590#define CAN_FS1R_FSC9_Pos (9U)
2591#define CAN_FS1R_FSC9_Msk (0x1UL << CAN_FS1R_FSC9_Pos)
2592#define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk
2593#define CAN_FS1R_FSC10_Pos (10U)
2594#define CAN_FS1R_FSC10_Msk (0x1UL << CAN_FS1R_FSC10_Pos)
2595#define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk
2596#define CAN_FS1R_FSC11_Pos (11U)
2597#define CAN_FS1R_FSC11_Msk (0x1UL << CAN_FS1R_FSC11_Pos)
2598#define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk
2599#define CAN_FS1R_FSC12_Pos (12U)
2600#define CAN_FS1R_FSC12_Msk (0x1UL << CAN_FS1R_FSC12_Pos)
2601#define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk
2602#define CAN_FS1R_FSC13_Pos (13U)
2603#define CAN_FS1R_FSC13_Msk (0x1UL << CAN_FS1R_FSC13_Pos)
2604#define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk
2605#define CAN_FS1R_FSC14_Pos (14U)
2606#define CAN_FS1R_FSC14_Msk (0x1UL << CAN_FS1R_FSC14_Pos)
2607#define CAN_FS1R_FSC14 CAN_FS1R_FSC14_Msk
2608#define CAN_FS1R_FSC15_Pos (15U)
2609#define CAN_FS1R_FSC15_Msk (0x1UL << CAN_FS1R_FSC15_Pos)
2610#define CAN_FS1R_FSC15 CAN_FS1R_FSC15_Msk
2611#define CAN_FS1R_FSC16_Pos (16U)
2612#define CAN_FS1R_FSC16_Msk (0x1UL << CAN_FS1R_FSC16_Pos)
2613#define CAN_FS1R_FSC16 CAN_FS1R_FSC16_Msk
2614#define CAN_FS1R_FSC17_Pos (17U)
2615#define CAN_FS1R_FSC17_Msk (0x1UL << CAN_FS1R_FSC17_Pos)
2616#define CAN_FS1R_FSC17 CAN_FS1R_FSC17_Msk
2617#define CAN_FS1R_FSC18_Pos (18U)
2618#define CAN_FS1R_FSC18_Msk (0x1UL << CAN_FS1R_FSC18_Pos)
2619#define CAN_FS1R_FSC18 CAN_FS1R_FSC18_Msk
2620#define CAN_FS1R_FSC19_Pos (19U)
2621#define CAN_FS1R_FSC19_Msk (0x1UL << CAN_FS1R_FSC19_Pos)
2622#define CAN_FS1R_FSC19 CAN_FS1R_FSC19_Msk
2623#define CAN_FS1R_FSC20_Pos (20U)
2624#define CAN_FS1R_FSC20_Msk (0x1UL << CAN_FS1R_FSC20_Pos)
2625#define CAN_FS1R_FSC20 CAN_FS1R_FSC20_Msk
2626#define CAN_FS1R_FSC21_Pos (21U)
2627#define CAN_FS1R_FSC21_Msk (0x1UL << CAN_FS1R_FSC21_Pos)
2628#define CAN_FS1R_FSC21 CAN_FS1R_FSC21_Msk
2629#define CAN_FS1R_FSC22_Pos (22U)
2630#define CAN_FS1R_FSC22_Msk (0x1UL << CAN_FS1R_FSC22_Pos)
2631#define CAN_FS1R_FSC22 CAN_FS1R_FSC22_Msk
2632#define CAN_FS1R_FSC23_Pos (23U)
2633#define CAN_FS1R_FSC23_Msk (0x1UL << CAN_FS1R_FSC23_Pos)
2634#define CAN_FS1R_FSC23 CAN_FS1R_FSC23_Msk
2635#define CAN_FS1R_FSC24_Pos (24U)
2636#define CAN_FS1R_FSC24_Msk (0x1UL << CAN_FS1R_FSC24_Pos)
2637#define CAN_FS1R_FSC24 CAN_FS1R_FSC24_Msk
2638#define CAN_FS1R_FSC25_Pos (25U)
2639#define CAN_FS1R_FSC25_Msk (0x1UL << CAN_FS1R_FSC25_Pos)
2640#define CAN_FS1R_FSC25 CAN_FS1R_FSC25_Msk
2641#define CAN_FS1R_FSC26_Pos (26U)
2642#define CAN_FS1R_FSC26_Msk (0x1UL << CAN_FS1R_FSC26_Pos)
2643#define CAN_FS1R_FSC26 CAN_FS1R_FSC26_Msk
2644#define CAN_FS1R_FSC27_Pos (27U)
2645#define CAN_FS1R_FSC27_Msk (0x1UL << CAN_FS1R_FSC27_Pos)
2646#define CAN_FS1R_FSC27 CAN_FS1R_FSC27_Msk
2647
2648/****************** Bit definition for CAN_FFA1R register *******************/
2649#define CAN_FFA1R_FFA_Pos (0U)
2650#define CAN_FFA1R_FFA_Msk (0xFFFFFFFUL << CAN_FFA1R_FFA_Pos)
2651#define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk
2652#define CAN_FFA1R_FFA0_Pos (0U)
2653#define CAN_FFA1R_FFA0_Msk (0x1UL << CAN_FFA1R_FFA0_Pos)
2654#define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk
2655#define CAN_FFA1R_FFA1_Pos (1U)
2656#define CAN_FFA1R_FFA1_Msk (0x1UL << CAN_FFA1R_FFA1_Pos)
2657#define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk
2658#define CAN_FFA1R_FFA2_Pos (2U)
2659#define CAN_FFA1R_FFA2_Msk (0x1UL << CAN_FFA1R_FFA2_Pos)
2660#define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk
2661#define CAN_FFA1R_FFA3_Pos (3U)
2662#define CAN_FFA1R_FFA3_Msk (0x1UL << CAN_FFA1R_FFA3_Pos)
2663#define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk
2664#define CAN_FFA1R_FFA4_Pos (4U)
2665#define CAN_FFA1R_FFA4_Msk (0x1UL << CAN_FFA1R_FFA4_Pos)
2666#define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk
2667#define CAN_FFA1R_FFA5_Pos (5U)
2668#define CAN_FFA1R_FFA5_Msk (0x1UL << CAN_FFA1R_FFA5_Pos)
2669#define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk
2670#define CAN_FFA1R_FFA6_Pos (6U)
2671#define CAN_FFA1R_FFA6_Msk (0x1UL << CAN_FFA1R_FFA6_Pos)
2672#define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk
2673#define CAN_FFA1R_FFA7_Pos (7U)
2674#define CAN_FFA1R_FFA7_Msk (0x1UL << CAN_FFA1R_FFA7_Pos)
2675#define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk
2676#define CAN_FFA1R_FFA8_Pos (8U)
2677#define CAN_FFA1R_FFA8_Msk (0x1UL << CAN_FFA1R_FFA8_Pos)
2678#define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk
2679#define CAN_FFA1R_FFA9_Pos (9U)
2680#define CAN_FFA1R_FFA9_Msk (0x1UL << CAN_FFA1R_FFA9_Pos)
2681#define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk
2682#define CAN_FFA1R_FFA10_Pos (10U)
2683#define CAN_FFA1R_FFA10_Msk (0x1UL << CAN_FFA1R_FFA10_Pos)
2684#define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk
2685#define CAN_FFA1R_FFA11_Pos (11U)
2686#define CAN_FFA1R_FFA11_Msk (0x1UL << CAN_FFA1R_FFA11_Pos)
2687#define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk
2688#define CAN_FFA1R_FFA12_Pos (12U)
2689#define CAN_FFA1R_FFA12_Msk (0x1UL << CAN_FFA1R_FFA12_Pos)
2690#define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk
2691#define CAN_FFA1R_FFA13_Pos (13U)
2692#define CAN_FFA1R_FFA13_Msk (0x1UL << CAN_FFA1R_FFA13_Pos)
2693#define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk
2694#define CAN_FFA1R_FFA14_Pos (14U)
2695#define CAN_FFA1R_FFA14_Msk (0x1UL << CAN_FFA1R_FFA14_Pos)
2696#define CAN_FFA1R_FFA14 CAN_FFA1R_FFA14_Msk
2697#define CAN_FFA1R_FFA15_Pos (15U)
2698#define CAN_FFA1R_FFA15_Msk (0x1UL << CAN_FFA1R_FFA15_Pos)
2699#define CAN_FFA1R_FFA15 CAN_FFA1R_FFA15_Msk
2700#define CAN_FFA1R_FFA16_Pos (16U)
2701#define CAN_FFA1R_FFA16_Msk (0x1UL << CAN_FFA1R_FFA16_Pos)
2702#define CAN_FFA1R_FFA16 CAN_FFA1R_FFA16_Msk
2703#define CAN_FFA1R_FFA17_Pos (17U)
2704#define CAN_FFA1R_FFA17_Msk (0x1UL << CAN_FFA1R_FFA17_Pos)
2705#define CAN_FFA1R_FFA17 CAN_FFA1R_FFA17_Msk
2706#define CAN_FFA1R_FFA18_Pos (18U)
2707#define CAN_FFA1R_FFA18_Msk (0x1UL << CAN_FFA1R_FFA18_Pos)
2708#define CAN_FFA1R_FFA18 CAN_FFA1R_FFA18_Msk
2709#define CAN_FFA1R_FFA19_Pos (19U)
2710#define CAN_FFA1R_FFA19_Msk (0x1UL << CAN_FFA1R_FFA19_Pos)
2711#define CAN_FFA1R_FFA19 CAN_FFA1R_FFA19_Msk
2712#define CAN_FFA1R_FFA20_Pos (20U)
2713#define CAN_FFA1R_FFA20_Msk (0x1UL << CAN_FFA1R_FFA20_Pos)
2714#define CAN_FFA1R_FFA20 CAN_FFA1R_FFA20_Msk
2715#define CAN_FFA1R_FFA21_Pos (21U)
2716#define CAN_FFA1R_FFA21_Msk (0x1UL << CAN_FFA1R_FFA21_Pos)
2717#define CAN_FFA1R_FFA21 CAN_FFA1R_FFA21_Msk
2718#define CAN_FFA1R_FFA22_Pos (22U)
2719#define CAN_FFA1R_FFA22_Msk (0x1UL << CAN_FFA1R_FFA22_Pos)
2720#define CAN_FFA1R_FFA22 CAN_FFA1R_FFA22_Msk
2721#define CAN_FFA1R_FFA23_Pos (23U)
2722#define CAN_FFA1R_FFA23_Msk (0x1UL << CAN_FFA1R_FFA23_Pos)
2723#define CAN_FFA1R_FFA23 CAN_FFA1R_FFA23_Msk
2724#define CAN_FFA1R_FFA24_Pos (24U)
2725#define CAN_FFA1R_FFA24_Msk (0x1UL << CAN_FFA1R_FFA24_Pos)
2726#define CAN_FFA1R_FFA24 CAN_FFA1R_FFA24_Msk
2727#define CAN_FFA1R_FFA25_Pos (25U)
2728#define CAN_FFA1R_FFA25_Msk (0x1UL << CAN_FFA1R_FFA25_Pos)
2729#define CAN_FFA1R_FFA25 CAN_FFA1R_FFA25_Msk
2730#define CAN_FFA1R_FFA26_Pos (26U)
2731#define CAN_FFA1R_FFA26_Msk (0x1UL << CAN_FFA1R_FFA26_Pos)
2732#define CAN_FFA1R_FFA26 CAN_FFA1R_FFA26_Msk
2733#define CAN_FFA1R_FFA27_Pos (27U)
2734#define CAN_FFA1R_FFA27_Msk (0x1UL << CAN_FFA1R_FFA27_Pos)
2735#define CAN_FFA1R_FFA27 CAN_FFA1R_FFA27_Msk
2736
2737/******************* Bit definition for CAN_FA1R register *******************/
2738#define CAN_FA1R_FACT_Pos (0U)
2739#define CAN_FA1R_FACT_Msk (0xFFFFFFFUL << CAN_FA1R_FACT_Pos)
2740#define CAN_FA1R_FACT CAN_FA1R_FACT_Msk
2741#define CAN_FA1R_FACT0_Pos (0U)
2742#define CAN_FA1R_FACT0_Msk (0x1UL << CAN_FA1R_FACT0_Pos)
2743#define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk
2744#define CAN_FA1R_FACT1_Pos (1U)
2745#define CAN_FA1R_FACT1_Msk (0x1UL << CAN_FA1R_FACT1_Pos)
2746#define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk
2747#define CAN_FA1R_FACT2_Pos (2U)
2748#define CAN_FA1R_FACT2_Msk (0x1UL << CAN_FA1R_FACT2_Pos)
2749#define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk
2750#define CAN_FA1R_FACT3_Pos (3U)
2751#define CAN_FA1R_FACT3_Msk (0x1UL << CAN_FA1R_FACT3_Pos)
2752#define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk
2753#define CAN_FA1R_FACT4_Pos (4U)
2754#define CAN_FA1R_FACT4_Msk (0x1UL << CAN_FA1R_FACT4_Pos)
2755#define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk
2756#define CAN_FA1R_FACT5_Pos (5U)
2757#define CAN_FA1R_FACT5_Msk (0x1UL << CAN_FA1R_FACT5_Pos)
2758#define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk
2759#define CAN_FA1R_FACT6_Pos (6U)
2760#define CAN_FA1R_FACT6_Msk (0x1UL << CAN_FA1R_FACT6_Pos)
2761#define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk
2762#define CAN_FA1R_FACT7_Pos (7U)
2763#define CAN_FA1R_FACT7_Msk (0x1UL << CAN_FA1R_FACT7_Pos)
2764#define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk
2765#define CAN_FA1R_FACT8_Pos (8U)
2766#define CAN_FA1R_FACT8_Msk (0x1UL << CAN_FA1R_FACT8_Pos)
2767#define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk
2768#define CAN_FA1R_FACT9_Pos (9U)
2769#define CAN_FA1R_FACT9_Msk (0x1UL << CAN_FA1R_FACT9_Pos)
2770#define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk
2771#define CAN_FA1R_FACT10_Pos (10U)
2772#define CAN_FA1R_FACT10_Msk (0x1UL << CAN_FA1R_FACT10_Pos)
2773#define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk
2774#define CAN_FA1R_FACT11_Pos (11U)
2775#define CAN_FA1R_FACT11_Msk (0x1UL << CAN_FA1R_FACT11_Pos)
2776#define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk
2777#define CAN_FA1R_FACT12_Pos (12U)
2778#define CAN_FA1R_FACT12_Msk (0x1UL << CAN_FA1R_FACT12_Pos)
2779#define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk
2780#define CAN_FA1R_FACT13_Pos (13U)
2781#define CAN_FA1R_FACT13_Msk (0x1UL << CAN_FA1R_FACT13_Pos)
2782#define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk
2783#define CAN_FA1R_FACT14_Pos (14U)
2784#define CAN_FA1R_FACT14_Msk (0x1UL << CAN_FA1R_FACT14_Pos)
2785#define CAN_FA1R_FACT14 CAN_FA1R_FACT14_Msk
2786#define CAN_FA1R_FACT15_Pos (15U)
2787#define CAN_FA1R_FACT15_Msk (0x1UL << CAN_FA1R_FACT15_Pos)
2788#define CAN_FA1R_FACT15 CAN_FA1R_FACT15_Msk
2789#define CAN_FA1R_FACT16_Pos (16U)
2790#define CAN_FA1R_FACT16_Msk (0x1UL << CAN_FA1R_FACT16_Pos)
2791#define CAN_FA1R_FACT16 CAN_FA1R_FACT16_Msk
2792#define CAN_FA1R_FACT17_Pos (17U)
2793#define CAN_FA1R_FACT17_Msk (0x1UL << CAN_FA1R_FACT17_Pos)
2794#define CAN_FA1R_FACT17 CAN_FA1R_FACT17_Msk
2795#define CAN_FA1R_FACT18_Pos (18U)
2796#define CAN_FA1R_FACT18_Msk (0x1UL << CAN_FA1R_FACT18_Pos)
2797#define CAN_FA1R_FACT18 CAN_FA1R_FACT18_Msk
2798#define CAN_FA1R_FACT19_Pos (19U)
2799#define CAN_FA1R_FACT19_Msk (0x1UL << CAN_FA1R_FACT19_Pos)
2800#define CAN_FA1R_FACT19 CAN_FA1R_FACT19_Msk
2801#define CAN_FA1R_FACT20_Pos (20U)
2802#define CAN_FA1R_FACT20_Msk (0x1UL << CAN_FA1R_FACT20_Pos)
2803#define CAN_FA1R_FACT20 CAN_FA1R_FACT20_Msk
2804#define CAN_FA1R_FACT21_Pos (21U)
2805#define CAN_FA1R_FACT21_Msk (0x1UL << CAN_FA1R_FACT21_Pos)
2806#define CAN_FA1R_FACT21 CAN_FA1R_FACT21_Msk
2807#define CAN_FA1R_FACT22_Pos (22U)
2808#define CAN_FA1R_FACT22_Msk (0x1UL << CAN_FA1R_FACT22_Pos)
2809#define CAN_FA1R_FACT22 CAN_FA1R_FACT22_Msk
2810#define CAN_FA1R_FACT23_Pos (23U)
2811#define CAN_FA1R_FACT23_Msk (0x1UL << CAN_FA1R_FACT23_Pos)
2812#define CAN_FA1R_FACT23 CAN_FA1R_FACT23_Msk
2813#define CAN_FA1R_FACT24_Pos (24U)
2814#define CAN_FA1R_FACT24_Msk (0x1UL << CAN_FA1R_FACT24_Pos)
2815#define CAN_FA1R_FACT24 CAN_FA1R_FACT24_Msk
2816#define CAN_FA1R_FACT25_Pos (25U)
2817#define CAN_FA1R_FACT25_Msk (0x1UL << CAN_FA1R_FACT25_Pos)
2818#define CAN_FA1R_FACT25 CAN_FA1R_FACT25_Msk
2819#define CAN_FA1R_FACT26_Pos (26U)
2820#define CAN_FA1R_FACT26_Msk (0x1UL << CAN_FA1R_FACT26_Pos)
2821#define CAN_FA1R_FACT26 CAN_FA1R_FACT26_Msk
2822#define CAN_FA1R_FACT27_Pos (27U)
2823#define CAN_FA1R_FACT27_Msk (0x1UL << CAN_FA1R_FACT27_Pos)
2824#define CAN_FA1R_FACT27 CAN_FA1R_FACT27_Msk
2825
2826
2827/******************* Bit definition for CAN_F0R1 register *******************/
2828#define CAN_F0R1_FB0_Pos (0U)
2829#define CAN_F0R1_FB0_Msk (0x1UL << CAN_F0R1_FB0_Pos)
2830#define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk
2831#define CAN_F0R1_FB1_Pos (1U)
2832#define CAN_F0R1_FB1_Msk (0x1UL << CAN_F0R1_FB1_Pos)
2833#define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk
2834#define CAN_F0R1_FB2_Pos (2U)
2835#define CAN_F0R1_FB2_Msk (0x1UL << CAN_F0R1_FB2_Pos)
2836#define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk
2837#define CAN_F0R1_FB3_Pos (3U)
2838#define CAN_F0R1_FB3_Msk (0x1UL << CAN_F0R1_FB3_Pos)
2839#define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk
2840#define CAN_F0R1_FB4_Pos (4U)
2841#define CAN_F0R1_FB4_Msk (0x1UL << CAN_F0R1_FB4_Pos)
2842#define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk
2843#define CAN_F0R1_FB5_Pos (5U)
2844#define CAN_F0R1_FB5_Msk (0x1UL << CAN_F0R1_FB5_Pos)
2845#define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk
2846#define CAN_F0R1_FB6_Pos (6U)
2847#define CAN_F0R1_FB6_Msk (0x1UL << CAN_F0R1_FB6_Pos)
2848#define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk
2849#define CAN_F0R1_FB7_Pos (7U)
2850#define CAN_F0R1_FB7_Msk (0x1UL << CAN_F0R1_FB7_Pos)
2851#define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk
2852#define CAN_F0R1_FB8_Pos (8U)
2853#define CAN_F0R1_FB8_Msk (0x1UL << CAN_F0R1_FB8_Pos)
2854#define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk
2855#define CAN_F0R1_FB9_Pos (9U)
2856#define CAN_F0R1_FB9_Msk (0x1UL << CAN_F0R1_FB9_Pos)
2857#define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk
2858#define CAN_F0R1_FB10_Pos (10U)
2859#define CAN_F0R1_FB10_Msk (0x1UL << CAN_F0R1_FB10_Pos)
2860#define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk
2861#define CAN_F0R1_FB11_Pos (11U)
2862#define CAN_F0R1_FB11_Msk (0x1UL << CAN_F0R1_FB11_Pos)
2863#define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk
2864#define CAN_F0R1_FB12_Pos (12U)
2865#define CAN_F0R1_FB12_Msk (0x1UL << CAN_F0R1_FB12_Pos)
2866#define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk
2867#define CAN_F0R1_FB13_Pos (13U)
2868#define CAN_F0R1_FB13_Msk (0x1UL << CAN_F0R1_FB13_Pos)
2869#define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk
2870#define CAN_F0R1_FB14_Pos (14U)
2871#define CAN_F0R1_FB14_Msk (0x1UL << CAN_F0R1_FB14_Pos)
2872#define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk
2873#define CAN_F0R1_FB15_Pos (15U)
2874#define CAN_F0R1_FB15_Msk (0x1UL << CAN_F0R1_FB15_Pos)
2875#define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk
2876#define CAN_F0R1_FB16_Pos (16U)
2877#define CAN_F0R1_FB16_Msk (0x1UL << CAN_F0R1_FB16_Pos)
2878#define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk
2879#define CAN_F0R1_FB17_Pos (17U)
2880#define CAN_F0R1_FB17_Msk (0x1UL << CAN_F0R1_FB17_Pos)
2881#define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk
2882#define CAN_F0R1_FB18_Pos (18U)
2883#define CAN_F0R1_FB18_Msk (0x1UL << CAN_F0R1_FB18_Pos)
2884#define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk
2885#define CAN_F0R1_FB19_Pos (19U)
2886#define CAN_F0R1_FB19_Msk (0x1UL << CAN_F0R1_FB19_Pos)
2887#define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk
2888#define CAN_F0R1_FB20_Pos (20U)
2889#define CAN_F0R1_FB20_Msk (0x1UL << CAN_F0R1_FB20_Pos)
2890#define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk
2891#define CAN_F0R1_FB21_Pos (21U)
2892#define CAN_F0R1_FB21_Msk (0x1UL << CAN_F0R1_FB21_Pos)
2893#define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk
2894#define CAN_F0R1_FB22_Pos (22U)
2895#define CAN_F0R1_FB22_Msk (0x1UL << CAN_F0R1_FB22_Pos)
2896#define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk
2897#define CAN_F0R1_FB23_Pos (23U)
2898#define CAN_F0R1_FB23_Msk (0x1UL << CAN_F0R1_FB23_Pos)
2899#define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk
2900#define CAN_F0R1_FB24_Pos (24U)
2901#define CAN_F0R1_FB24_Msk (0x1UL << CAN_F0R1_FB24_Pos)
2902#define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk
2903#define CAN_F0R1_FB25_Pos (25U)
2904#define CAN_F0R1_FB25_Msk (0x1UL << CAN_F0R1_FB25_Pos)
2905#define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk
2906#define CAN_F0R1_FB26_Pos (26U)
2907#define CAN_F0R1_FB26_Msk (0x1UL << CAN_F0R1_FB26_Pos)
2908#define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk
2909#define CAN_F0R1_FB27_Pos (27U)
2910#define CAN_F0R1_FB27_Msk (0x1UL << CAN_F0R1_FB27_Pos)
2911#define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk
2912#define CAN_F0R1_FB28_Pos (28U)
2913#define CAN_F0R1_FB28_Msk (0x1UL << CAN_F0R1_FB28_Pos)
2914#define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk
2915#define CAN_F0R1_FB29_Pos (29U)
2916#define CAN_F0R1_FB29_Msk (0x1UL << CAN_F0R1_FB29_Pos)
2917#define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk
2918#define CAN_F0R1_FB30_Pos (30U)
2919#define CAN_F0R1_FB30_Msk (0x1UL << CAN_F0R1_FB30_Pos)
2920#define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk
2921#define CAN_F0R1_FB31_Pos (31U)
2922#define CAN_F0R1_FB31_Msk (0x1UL << CAN_F0R1_FB31_Pos)
2923#define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk
2924
2925/******************* Bit definition for CAN_F1R1 register *******************/
2926#define CAN_F1R1_FB0_Pos (0U)
2927#define CAN_F1R1_FB0_Msk (0x1UL << CAN_F1R1_FB0_Pos)
2928#define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk
2929#define CAN_F1R1_FB1_Pos (1U)
2930#define CAN_F1R1_FB1_Msk (0x1UL << CAN_F1R1_FB1_Pos)
2931#define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk
2932#define CAN_F1R1_FB2_Pos (2U)
2933#define CAN_F1R1_FB2_Msk (0x1UL << CAN_F1R1_FB2_Pos)
2934#define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk
2935#define CAN_F1R1_FB3_Pos (3U)
2936#define CAN_F1R1_FB3_Msk (0x1UL << CAN_F1R1_FB3_Pos)
2937#define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk
2938#define CAN_F1R1_FB4_Pos (4U)
2939#define CAN_F1R1_FB4_Msk (0x1UL << CAN_F1R1_FB4_Pos)
2940#define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk
2941#define CAN_F1R1_FB5_Pos (5U)
2942#define CAN_F1R1_FB5_Msk (0x1UL << CAN_F1R1_FB5_Pos)
2943#define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk
2944#define CAN_F1R1_FB6_Pos (6U)
2945#define CAN_F1R1_FB6_Msk (0x1UL << CAN_F1R1_FB6_Pos)
2946#define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk
2947#define CAN_F1R1_FB7_Pos (7U)
2948#define CAN_F1R1_FB7_Msk (0x1UL << CAN_F1R1_FB7_Pos)
2949#define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk
2950#define CAN_F1R1_FB8_Pos (8U)
2951#define CAN_F1R1_FB8_Msk (0x1UL << CAN_F1R1_FB8_Pos)
2952#define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk
2953#define CAN_F1R1_FB9_Pos (9U)
2954#define CAN_F1R1_FB9_Msk (0x1UL << CAN_F1R1_FB9_Pos)
2955#define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk
2956#define CAN_F1R1_FB10_Pos (10U)
2957#define CAN_F1R1_FB10_Msk (0x1UL << CAN_F1R1_FB10_Pos)
2958#define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk
2959#define CAN_F1R1_FB11_Pos (11U)
2960#define CAN_F1R1_FB11_Msk (0x1UL << CAN_F1R1_FB11_Pos)
2961#define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk
2962#define CAN_F1R1_FB12_Pos (12U)
2963#define CAN_F1R1_FB12_Msk (0x1UL << CAN_F1R1_FB12_Pos)
2964#define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk
2965#define CAN_F1R1_FB13_Pos (13U)
2966#define CAN_F1R1_FB13_Msk (0x1UL << CAN_F1R1_FB13_Pos)
2967#define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk
2968#define CAN_F1R1_FB14_Pos (14U)
2969#define CAN_F1R1_FB14_Msk (0x1UL << CAN_F1R1_FB14_Pos)
2970#define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk
2971#define CAN_F1R1_FB15_Pos (15U)
2972#define CAN_F1R1_FB15_Msk (0x1UL << CAN_F1R1_FB15_Pos)
2973#define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk
2974#define CAN_F1R1_FB16_Pos (16U)
2975#define CAN_F1R1_FB16_Msk (0x1UL << CAN_F1R1_FB16_Pos)
2976#define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk
2977#define CAN_F1R1_FB17_Pos (17U)
2978#define CAN_F1R1_FB17_Msk (0x1UL << CAN_F1R1_FB17_Pos)
2979#define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk
2980#define CAN_F1R1_FB18_Pos (18U)
2981#define CAN_F1R1_FB18_Msk (0x1UL << CAN_F1R1_FB18_Pos)
2982#define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk
2983#define CAN_F1R1_FB19_Pos (19U)
2984#define CAN_F1R1_FB19_Msk (0x1UL << CAN_F1R1_FB19_Pos)
2985#define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk
2986#define CAN_F1R1_FB20_Pos (20U)
2987#define CAN_F1R1_FB20_Msk (0x1UL << CAN_F1R1_FB20_Pos)
2988#define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk
2989#define CAN_F1R1_FB21_Pos (21U)
2990#define CAN_F1R1_FB21_Msk (0x1UL << CAN_F1R1_FB21_Pos)
2991#define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk
2992#define CAN_F1R1_FB22_Pos (22U)
2993#define CAN_F1R1_FB22_Msk (0x1UL << CAN_F1R1_FB22_Pos)
2994#define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk
2995#define CAN_F1R1_FB23_Pos (23U)
2996#define CAN_F1R1_FB23_Msk (0x1UL << CAN_F1R1_FB23_Pos)
2997#define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk
2998#define CAN_F1R1_FB24_Pos (24U)
2999#define CAN_F1R1_FB24_Msk (0x1UL << CAN_F1R1_FB24_Pos)
3000#define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk
3001#define CAN_F1R1_FB25_Pos (25U)
3002#define CAN_F1R1_FB25_Msk (0x1UL << CAN_F1R1_FB25_Pos)
3003#define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk
3004#define CAN_F1R1_FB26_Pos (26U)
3005#define CAN_F1R1_FB26_Msk (0x1UL << CAN_F1R1_FB26_Pos)
3006#define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk
3007#define CAN_F1R1_FB27_Pos (27U)
3008#define CAN_F1R1_FB27_Msk (0x1UL << CAN_F1R1_FB27_Pos)
3009#define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk
3010#define CAN_F1R1_FB28_Pos (28U)
3011#define CAN_F1R1_FB28_Msk (0x1UL << CAN_F1R1_FB28_Pos)
3012#define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk
3013#define CAN_F1R1_FB29_Pos (29U)
3014#define CAN_F1R1_FB29_Msk (0x1UL << CAN_F1R1_FB29_Pos)
3015#define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk
3016#define CAN_F1R1_FB30_Pos (30U)
3017#define CAN_F1R1_FB30_Msk (0x1UL << CAN_F1R1_FB30_Pos)
3018#define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk
3019#define CAN_F1R1_FB31_Pos (31U)
3020#define CAN_F1R1_FB31_Msk (0x1UL << CAN_F1R1_FB31_Pos)
3021#define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk
3022
3023/******************* Bit definition for CAN_F2R1 register *******************/
3024#define CAN_F2R1_FB0_Pos (0U)
3025#define CAN_F2R1_FB0_Msk (0x1UL << CAN_F2R1_FB0_Pos)
3026#define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk
3027#define CAN_F2R1_FB1_Pos (1U)
3028#define CAN_F2R1_FB1_Msk (0x1UL << CAN_F2R1_FB1_Pos)
3029#define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk
3030#define CAN_F2R1_FB2_Pos (2U)
3031#define CAN_F2R1_FB2_Msk (0x1UL << CAN_F2R1_FB2_Pos)
3032#define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk
3033#define CAN_F2R1_FB3_Pos (3U)
3034#define CAN_F2R1_FB3_Msk (0x1UL << CAN_F2R1_FB3_Pos)
3035#define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk
3036#define CAN_F2R1_FB4_Pos (4U)
3037#define CAN_F2R1_FB4_Msk (0x1UL << CAN_F2R1_FB4_Pos)
3038#define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk
3039#define CAN_F2R1_FB5_Pos (5U)
3040#define CAN_F2R1_FB5_Msk (0x1UL << CAN_F2R1_FB5_Pos)
3041#define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk
3042#define CAN_F2R1_FB6_Pos (6U)
3043#define CAN_F2R1_FB6_Msk (0x1UL << CAN_F2R1_FB6_Pos)
3044#define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk
3045#define CAN_F2R1_FB7_Pos (7U)
3046#define CAN_F2R1_FB7_Msk (0x1UL << CAN_F2R1_FB7_Pos)
3047#define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk
3048#define CAN_F2R1_FB8_Pos (8U)
3049#define CAN_F2R1_FB8_Msk (0x1UL << CAN_F2R1_FB8_Pos)
3050#define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk
3051#define CAN_F2R1_FB9_Pos (9U)
3052#define CAN_F2R1_FB9_Msk (0x1UL << CAN_F2R1_FB9_Pos)
3053#define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk
3054#define CAN_F2R1_FB10_Pos (10U)
3055#define CAN_F2R1_FB10_Msk (0x1UL << CAN_F2R1_FB10_Pos)
3056#define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk
3057#define CAN_F2R1_FB11_Pos (11U)
3058#define CAN_F2R1_FB11_Msk (0x1UL << CAN_F2R1_FB11_Pos)
3059#define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk
3060#define CAN_F2R1_FB12_Pos (12U)
3061#define CAN_F2R1_FB12_Msk (0x1UL << CAN_F2R1_FB12_Pos)
3062#define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk
3063#define CAN_F2R1_FB13_Pos (13U)
3064#define CAN_F2R1_FB13_Msk (0x1UL << CAN_F2R1_FB13_Pos)
3065#define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk
3066#define CAN_F2R1_FB14_Pos (14U)
3067#define CAN_F2R1_FB14_Msk (0x1UL << CAN_F2R1_FB14_Pos)
3068#define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk
3069#define CAN_F2R1_FB15_Pos (15U)
3070#define CAN_F2R1_FB15_Msk (0x1UL << CAN_F2R1_FB15_Pos)
3071#define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk
3072#define CAN_F2R1_FB16_Pos (16U)
3073#define CAN_F2R1_FB16_Msk (0x1UL << CAN_F2R1_FB16_Pos)
3074#define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk
3075#define CAN_F2R1_FB17_Pos (17U)
3076#define CAN_F2R1_FB17_Msk (0x1UL << CAN_F2R1_FB17_Pos)
3077#define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk
3078#define CAN_F2R1_FB18_Pos (18U)
3079#define CAN_F2R1_FB18_Msk (0x1UL << CAN_F2R1_FB18_Pos)
3080#define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk
3081#define CAN_F2R1_FB19_Pos (19U)
3082#define CAN_F2R1_FB19_Msk (0x1UL << CAN_F2R1_FB19_Pos)
3083#define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk
3084#define CAN_F2R1_FB20_Pos (20U)
3085#define CAN_F2R1_FB20_Msk (0x1UL << CAN_F2R1_FB20_Pos)
3086#define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk
3087#define CAN_F2R1_FB21_Pos (21U)
3088#define CAN_F2R1_FB21_Msk (0x1UL << CAN_F2R1_FB21_Pos)
3089#define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk
3090#define CAN_F2R1_FB22_Pos (22U)
3091#define CAN_F2R1_FB22_Msk (0x1UL << CAN_F2R1_FB22_Pos)
3092#define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk
3093#define CAN_F2R1_FB23_Pos (23U)
3094#define CAN_F2R1_FB23_Msk (0x1UL << CAN_F2R1_FB23_Pos)
3095#define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk
3096#define CAN_F2R1_FB24_Pos (24U)
3097#define CAN_F2R1_FB24_Msk (0x1UL << CAN_F2R1_FB24_Pos)
3098#define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk
3099#define CAN_F2R1_FB25_Pos (25U)
3100#define CAN_F2R1_FB25_Msk (0x1UL << CAN_F2R1_FB25_Pos)
3101#define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk
3102#define CAN_F2R1_FB26_Pos (26U)
3103#define CAN_F2R1_FB26_Msk (0x1UL << CAN_F2R1_FB26_Pos)
3104#define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk
3105#define CAN_F2R1_FB27_Pos (27U)
3106#define CAN_F2R1_FB27_Msk (0x1UL << CAN_F2R1_FB27_Pos)
3107#define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk
3108#define CAN_F2R1_FB28_Pos (28U)
3109#define CAN_F2R1_FB28_Msk (0x1UL << CAN_F2R1_FB28_Pos)
3110#define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk
3111#define CAN_F2R1_FB29_Pos (29U)
3112#define CAN_F2R1_FB29_Msk (0x1UL << CAN_F2R1_FB29_Pos)
3113#define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk
3114#define CAN_F2R1_FB30_Pos (30U)
3115#define CAN_F2R1_FB30_Msk (0x1UL << CAN_F2R1_FB30_Pos)
3116#define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk
3117#define CAN_F2R1_FB31_Pos (31U)
3118#define CAN_F2R1_FB31_Msk (0x1UL << CAN_F2R1_FB31_Pos)
3119#define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk
3120
3121/******************* Bit definition for CAN_F3R1 register *******************/
3122#define CAN_F3R1_FB0_Pos (0U)
3123#define CAN_F3R1_FB0_Msk (0x1UL << CAN_F3R1_FB0_Pos)
3124#define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk
3125#define CAN_F3R1_FB1_Pos (1U)
3126#define CAN_F3R1_FB1_Msk (0x1UL << CAN_F3R1_FB1_Pos)
3127#define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk
3128#define CAN_F3R1_FB2_Pos (2U)
3129#define CAN_F3R1_FB2_Msk (0x1UL << CAN_F3R1_FB2_Pos)
3130#define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk
3131#define CAN_F3R1_FB3_Pos (3U)
3132#define CAN_F3R1_FB3_Msk (0x1UL << CAN_F3R1_FB3_Pos)
3133#define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk
3134#define CAN_F3R1_FB4_Pos (4U)
3135#define CAN_F3R1_FB4_Msk (0x1UL << CAN_F3R1_FB4_Pos)
3136#define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk
3137#define CAN_F3R1_FB5_Pos (5U)
3138#define CAN_F3R1_FB5_Msk (0x1UL << CAN_F3R1_FB5_Pos)
3139#define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk
3140#define CAN_F3R1_FB6_Pos (6U)
3141#define CAN_F3R1_FB6_Msk (0x1UL << CAN_F3R1_FB6_Pos)
3142#define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk
3143#define CAN_F3R1_FB7_Pos (7U)
3144#define CAN_F3R1_FB7_Msk (0x1UL << CAN_F3R1_FB7_Pos)
3145#define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk
3146#define CAN_F3R1_FB8_Pos (8U)
3147#define CAN_F3R1_FB8_Msk (0x1UL << CAN_F3R1_FB8_Pos)
3148#define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk
3149#define CAN_F3R1_FB9_Pos (9U)
3150#define CAN_F3R1_FB9_Msk (0x1UL << CAN_F3R1_FB9_Pos)
3151#define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk
3152#define CAN_F3R1_FB10_Pos (10U)
3153#define CAN_F3R1_FB10_Msk (0x1UL << CAN_F3R1_FB10_Pos)
3154#define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk
3155#define CAN_F3R1_FB11_Pos (11U)
3156#define CAN_F3R1_FB11_Msk (0x1UL << CAN_F3R1_FB11_Pos)
3157#define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk
3158#define CAN_F3R1_FB12_Pos (12U)
3159#define CAN_F3R1_FB12_Msk (0x1UL << CAN_F3R1_FB12_Pos)
3160#define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk
3161#define CAN_F3R1_FB13_Pos (13U)
3162#define CAN_F3R1_FB13_Msk (0x1UL << CAN_F3R1_FB13_Pos)
3163#define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk
3164#define CAN_F3R1_FB14_Pos (14U)
3165#define CAN_F3R1_FB14_Msk (0x1UL << CAN_F3R1_FB14_Pos)
3166#define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk
3167#define CAN_F3R1_FB15_Pos (15U)
3168#define CAN_F3R1_FB15_Msk (0x1UL << CAN_F3R1_FB15_Pos)
3169#define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk
3170#define CAN_F3R1_FB16_Pos (16U)
3171#define CAN_F3R1_FB16_Msk (0x1UL << CAN_F3R1_FB16_Pos)
3172#define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk
3173#define CAN_F3R1_FB17_Pos (17U)
3174#define CAN_F3R1_FB17_Msk (0x1UL << CAN_F3R1_FB17_Pos)
3175#define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk
3176#define CAN_F3R1_FB18_Pos (18U)
3177#define CAN_F3R1_FB18_Msk (0x1UL << CAN_F3R1_FB18_Pos)
3178#define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk
3179#define CAN_F3R1_FB19_Pos (19U)
3180#define CAN_F3R1_FB19_Msk (0x1UL << CAN_F3R1_FB19_Pos)
3181#define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk
3182#define CAN_F3R1_FB20_Pos (20U)
3183#define CAN_F3R1_FB20_Msk (0x1UL << CAN_F3R1_FB20_Pos)
3184#define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk
3185#define CAN_F3R1_FB21_Pos (21U)
3186#define CAN_F3R1_FB21_Msk (0x1UL << CAN_F3R1_FB21_Pos)
3187#define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk
3188#define CAN_F3R1_FB22_Pos (22U)
3189#define CAN_F3R1_FB22_Msk (0x1UL << CAN_F3R1_FB22_Pos)
3190#define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk
3191#define CAN_F3R1_FB23_Pos (23U)
3192#define CAN_F3R1_FB23_Msk (0x1UL << CAN_F3R1_FB23_Pos)
3193#define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk
3194#define CAN_F3R1_FB24_Pos (24U)
3195#define CAN_F3R1_FB24_Msk (0x1UL << CAN_F3R1_FB24_Pos)
3196#define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk
3197#define CAN_F3R1_FB25_Pos (25U)
3198#define CAN_F3R1_FB25_Msk (0x1UL << CAN_F3R1_FB25_Pos)
3199#define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk
3200#define CAN_F3R1_FB26_Pos (26U)
3201#define CAN_F3R1_FB26_Msk (0x1UL << CAN_F3R1_FB26_Pos)
3202#define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk
3203#define CAN_F3R1_FB27_Pos (27U)
3204#define CAN_F3R1_FB27_Msk (0x1UL << CAN_F3R1_FB27_Pos)
3205#define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk
3206#define CAN_F3R1_FB28_Pos (28U)
3207#define CAN_F3R1_FB28_Msk (0x1UL << CAN_F3R1_FB28_Pos)
3208#define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk
3209#define CAN_F3R1_FB29_Pos (29U)
3210#define CAN_F3R1_FB29_Msk (0x1UL << CAN_F3R1_FB29_Pos)
3211#define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk
3212#define CAN_F3R1_FB30_Pos (30U)
3213#define CAN_F3R1_FB30_Msk (0x1UL << CAN_F3R1_FB30_Pos)
3214#define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk
3215#define CAN_F3R1_FB31_Pos (31U)
3216#define CAN_F3R1_FB31_Msk (0x1UL << CAN_F3R1_FB31_Pos)
3217#define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk
3218
3219/******************* Bit definition for CAN_F4R1 register *******************/
3220#define CAN_F4R1_FB0_Pos (0U)
3221#define CAN_F4R1_FB0_Msk (0x1UL << CAN_F4R1_FB0_Pos)
3222#define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk
3223#define CAN_F4R1_FB1_Pos (1U)
3224#define CAN_F4R1_FB1_Msk (0x1UL << CAN_F4R1_FB1_Pos)
3225#define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk
3226#define CAN_F4R1_FB2_Pos (2U)
3227#define CAN_F4R1_FB2_Msk (0x1UL << CAN_F4R1_FB2_Pos)
3228#define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk
3229#define CAN_F4R1_FB3_Pos (3U)
3230#define CAN_F4R1_FB3_Msk (0x1UL << CAN_F4R1_FB3_Pos)
3231#define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk
3232#define CAN_F4R1_FB4_Pos (4U)
3233#define CAN_F4R1_FB4_Msk (0x1UL << CAN_F4R1_FB4_Pos)
3234#define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk
3235#define CAN_F4R1_FB5_Pos (5U)
3236#define CAN_F4R1_FB5_Msk (0x1UL << CAN_F4R1_FB5_Pos)
3237#define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk
3238#define CAN_F4R1_FB6_Pos (6U)
3239#define CAN_F4R1_FB6_Msk (0x1UL << CAN_F4R1_FB6_Pos)
3240#define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk
3241#define CAN_F4R1_FB7_Pos (7U)
3242#define CAN_F4R1_FB7_Msk (0x1UL << CAN_F4R1_FB7_Pos)
3243#define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk
3244#define CAN_F4R1_FB8_Pos (8U)
3245#define CAN_F4R1_FB8_Msk (0x1UL << CAN_F4R1_FB8_Pos)
3246#define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk
3247#define CAN_F4R1_FB9_Pos (9U)
3248#define CAN_F4R1_FB9_Msk (0x1UL << CAN_F4R1_FB9_Pos)
3249#define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk
3250#define CAN_F4R1_FB10_Pos (10U)
3251#define CAN_F4R1_FB10_Msk (0x1UL << CAN_F4R1_FB10_Pos)
3252#define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk
3253#define CAN_F4R1_FB11_Pos (11U)
3254#define CAN_F4R1_FB11_Msk (0x1UL << CAN_F4R1_FB11_Pos)
3255#define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk
3256#define CAN_F4R1_FB12_Pos (12U)
3257#define CAN_F4R1_FB12_Msk (0x1UL << CAN_F4R1_FB12_Pos)
3258#define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk
3259#define CAN_F4R1_FB13_Pos (13U)
3260#define CAN_F4R1_FB13_Msk (0x1UL << CAN_F4R1_FB13_Pos)
3261#define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk
3262#define CAN_F4R1_FB14_Pos (14U)
3263#define CAN_F4R1_FB14_Msk (0x1UL << CAN_F4R1_FB14_Pos)
3264#define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk
3265#define CAN_F4R1_FB15_Pos (15U)
3266#define CAN_F4R1_FB15_Msk (0x1UL << CAN_F4R1_FB15_Pos)
3267#define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk
3268#define CAN_F4R1_FB16_Pos (16U)
3269#define CAN_F4R1_FB16_Msk (0x1UL << CAN_F4R1_FB16_Pos)
3270#define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk
3271#define CAN_F4R1_FB17_Pos (17U)
3272#define CAN_F4R1_FB17_Msk (0x1UL << CAN_F4R1_FB17_Pos)
3273#define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk
3274#define CAN_F4R1_FB18_Pos (18U)
3275#define CAN_F4R1_FB18_Msk (0x1UL << CAN_F4R1_FB18_Pos)
3276#define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk
3277#define CAN_F4R1_FB19_Pos (19U)
3278#define CAN_F4R1_FB19_Msk (0x1UL << CAN_F4R1_FB19_Pos)
3279#define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk
3280#define CAN_F4R1_FB20_Pos (20U)
3281#define CAN_F4R1_FB20_Msk (0x1UL << CAN_F4R1_FB20_Pos)
3282#define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk
3283#define CAN_F4R1_FB21_Pos (21U)
3284#define CAN_F4R1_FB21_Msk (0x1UL << CAN_F4R1_FB21_Pos)
3285#define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk
3286#define CAN_F4R1_FB22_Pos (22U)
3287#define CAN_F4R1_FB22_Msk (0x1UL << CAN_F4R1_FB22_Pos)
3288#define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk
3289#define CAN_F4R1_FB23_Pos (23U)
3290#define CAN_F4R1_FB23_Msk (0x1UL << CAN_F4R1_FB23_Pos)
3291#define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk
3292#define CAN_F4R1_FB24_Pos (24U)
3293#define CAN_F4R1_FB24_Msk (0x1UL << CAN_F4R1_FB24_Pos)
3294#define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk
3295#define CAN_F4R1_FB25_Pos (25U)
3296#define CAN_F4R1_FB25_Msk (0x1UL << CAN_F4R1_FB25_Pos)
3297#define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk
3298#define CAN_F4R1_FB26_Pos (26U)
3299#define CAN_F4R1_FB26_Msk (0x1UL << CAN_F4R1_FB26_Pos)
3300#define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk
3301#define CAN_F4R1_FB27_Pos (27U)
3302#define CAN_F4R1_FB27_Msk (0x1UL << CAN_F4R1_FB27_Pos)
3303#define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk
3304#define CAN_F4R1_FB28_Pos (28U)
3305#define CAN_F4R1_FB28_Msk (0x1UL << CAN_F4R1_FB28_Pos)
3306#define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk
3307#define CAN_F4R1_FB29_Pos (29U)
3308#define CAN_F4R1_FB29_Msk (0x1UL << CAN_F4R1_FB29_Pos)
3309#define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk
3310#define CAN_F4R1_FB30_Pos (30U)
3311#define CAN_F4R1_FB30_Msk (0x1UL << CAN_F4R1_FB30_Pos)
3312#define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk
3313#define CAN_F4R1_FB31_Pos (31U)
3314#define CAN_F4R1_FB31_Msk (0x1UL << CAN_F4R1_FB31_Pos)
3315#define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk
3316
3317/******************* Bit definition for CAN_F5R1 register *******************/
3318#define CAN_F5R1_FB0_Pos (0U)
3319#define CAN_F5R1_FB0_Msk (0x1UL << CAN_F5R1_FB0_Pos)
3320#define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk
3321#define CAN_F5R1_FB1_Pos (1U)
3322#define CAN_F5R1_FB1_Msk (0x1UL << CAN_F5R1_FB1_Pos)
3323#define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk
3324#define CAN_F5R1_FB2_Pos (2U)
3325#define CAN_F5R1_FB2_Msk (0x1UL << CAN_F5R1_FB2_Pos)
3326#define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk
3327#define CAN_F5R1_FB3_Pos (3U)
3328#define CAN_F5R1_FB3_Msk (0x1UL << CAN_F5R1_FB3_Pos)
3329#define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk
3330#define CAN_F5R1_FB4_Pos (4U)
3331#define CAN_F5R1_FB4_Msk (0x1UL << CAN_F5R1_FB4_Pos)
3332#define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk
3333#define CAN_F5R1_FB5_Pos (5U)
3334#define CAN_F5R1_FB5_Msk (0x1UL << CAN_F5R1_FB5_Pos)
3335#define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk
3336#define CAN_F5R1_FB6_Pos (6U)
3337#define CAN_F5R1_FB6_Msk (0x1UL << CAN_F5R1_FB6_Pos)
3338#define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk
3339#define CAN_F5R1_FB7_Pos (7U)
3340#define CAN_F5R1_FB7_Msk (0x1UL << CAN_F5R1_FB7_Pos)
3341#define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk
3342#define CAN_F5R1_FB8_Pos (8U)
3343#define CAN_F5R1_FB8_Msk (0x1UL << CAN_F5R1_FB8_Pos)
3344#define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk
3345#define CAN_F5R1_FB9_Pos (9U)
3346#define CAN_F5R1_FB9_Msk (0x1UL << CAN_F5R1_FB9_Pos)
3347#define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk
3348#define CAN_F5R1_FB10_Pos (10U)
3349#define CAN_F5R1_FB10_Msk (0x1UL << CAN_F5R1_FB10_Pos)
3350#define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk
3351#define CAN_F5R1_FB11_Pos (11U)
3352#define CAN_F5R1_FB11_Msk (0x1UL << CAN_F5R1_FB11_Pos)
3353#define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk
3354#define CAN_F5R1_FB12_Pos (12U)
3355#define CAN_F5R1_FB12_Msk (0x1UL << CAN_F5R1_FB12_Pos)
3356#define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk
3357#define CAN_F5R1_FB13_Pos (13U)
3358#define CAN_F5R1_FB13_Msk (0x1UL << CAN_F5R1_FB13_Pos)
3359#define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk
3360#define CAN_F5R1_FB14_Pos (14U)
3361#define CAN_F5R1_FB14_Msk (0x1UL << CAN_F5R1_FB14_Pos)
3362#define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk
3363#define CAN_F5R1_FB15_Pos (15U)
3364#define CAN_F5R1_FB15_Msk (0x1UL << CAN_F5R1_FB15_Pos)
3365#define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk
3366#define CAN_F5R1_FB16_Pos (16U)
3367#define CAN_F5R1_FB16_Msk (0x1UL << CAN_F5R1_FB16_Pos)
3368#define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk
3369#define CAN_F5R1_FB17_Pos (17U)
3370#define CAN_F5R1_FB17_Msk (0x1UL << CAN_F5R1_FB17_Pos)
3371#define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk
3372#define CAN_F5R1_FB18_Pos (18U)
3373#define CAN_F5R1_FB18_Msk (0x1UL << CAN_F5R1_FB18_Pos)
3374#define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk
3375#define CAN_F5R1_FB19_Pos (19U)
3376#define CAN_F5R1_FB19_Msk (0x1UL << CAN_F5R1_FB19_Pos)
3377#define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk
3378#define CAN_F5R1_FB20_Pos (20U)
3379#define CAN_F5R1_FB20_Msk (0x1UL << CAN_F5R1_FB20_Pos)
3380#define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk
3381#define CAN_F5R1_FB21_Pos (21U)
3382#define CAN_F5R1_FB21_Msk (0x1UL << CAN_F5R1_FB21_Pos)
3383#define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk
3384#define CAN_F5R1_FB22_Pos (22U)
3385#define CAN_F5R1_FB22_Msk (0x1UL << CAN_F5R1_FB22_Pos)
3386#define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk
3387#define CAN_F5R1_FB23_Pos (23U)
3388#define CAN_F5R1_FB23_Msk (0x1UL << CAN_F5R1_FB23_Pos)
3389#define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk
3390#define CAN_F5R1_FB24_Pos (24U)
3391#define CAN_F5R1_FB24_Msk (0x1UL << CAN_F5R1_FB24_Pos)
3392#define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk
3393#define CAN_F5R1_FB25_Pos (25U)
3394#define CAN_F5R1_FB25_Msk (0x1UL << CAN_F5R1_FB25_Pos)
3395#define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk
3396#define CAN_F5R1_FB26_Pos (26U)
3397#define CAN_F5R1_FB26_Msk (0x1UL << CAN_F5R1_FB26_Pos)
3398#define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk
3399#define CAN_F5R1_FB27_Pos (27U)
3400#define CAN_F5R1_FB27_Msk (0x1UL << CAN_F5R1_FB27_Pos)
3401#define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk
3402#define CAN_F5R1_FB28_Pos (28U)
3403#define CAN_F5R1_FB28_Msk (0x1UL << CAN_F5R1_FB28_Pos)
3404#define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk
3405#define CAN_F5R1_FB29_Pos (29U)
3406#define CAN_F5R1_FB29_Msk (0x1UL << CAN_F5R1_FB29_Pos)
3407#define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk
3408#define CAN_F5R1_FB30_Pos (30U)
3409#define CAN_F5R1_FB30_Msk (0x1UL << CAN_F5R1_FB30_Pos)
3410#define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk
3411#define CAN_F5R1_FB31_Pos (31U)
3412#define CAN_F5R1_FB31_Msk (0x1UL << CAN_F5R1_FB31_Pos)
3413#define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk
3414
3415/******************* Bit definition for CAN_F6R1 register *******************/
3416#define CAN_F6R1_FB0_Pos (0U)
3417#define CAN_F6R1_FB0_Msk (0x1UL << CAN_F6R1_FB0_Pos)
3418#define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk
3419#define CAN_F6R1_FB1_Pos (1U)
3420#define CAN_F6R1_FB1_Msk (0x1UL << CAN_F6R1_FB1_Pos)
3421#define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk
3422#define CAN_F6R1_FB2_Pos (2U)
3423#define CAN_F6R1_FB2_Msk (0x1UL << CAN_F6R1_FB2_Pos)
3424#define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk
3425#define CAN_F6R1_FB3_Pos (3U)
3426#define CAN_F6R1_FB3_Msk (0x1UL << CAN_F6R1_FB3_Pos)
3427#define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk
3428#define CAN_F6R1_FB4_Pos (4U)
3429#define CAN_F6R1_FB4_Msk (0x1UL << CAN_F6R1_FB4_Pos)
3430#define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk
3431#define CAN_F6R1_FB5_Pos (5U)
3432#define CAN_F6R1_FB5_Msk (0x1UL << CAN_F6R1_FB5_Pos)
3433#define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk
3434#define CAN_F6R1_FB6_Pos (6U)
3435#define CAN_F6R1_FB6_Msk (0x1UL << CAN_F6R1_FB6_Pos)
3436#define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk
3437#define CAN_F6R1_FB7_Pos (7U)
3438#define CAN_F6R1_FB7_Msk (0x1UL << CAN_F6R1_FB7_Pos)
3439#define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk
3440#define CAN_F6R1_FB8_Pos (8U)
3441#define CAN_F6R1_FB8_Msk (0x1UL << CAN_F6R1_FB8_Pos)
3442#define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk
3443#define CAN_F6R1_FB9_Pos (9U)
3444#define CAN_F6R1_FB9_Msk (0x1UL << CAN_F6R1_FB9_Pos)
3445#define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk
3446#define CAN_F6R1_FB10_Pos (10U)
3447#define CAN_F6R1_FB10_Msk (0x1UL << CAN_F6R1_FB10_Pos)
3448#define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk
3449#define CAN_F6R1_FB11_Pos (11U)
3450#define CAN_F6R1_FB11_Msk (0x1UL << CAN_F6R1_FB11_Pos)
3451#define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk
3452#define CAN_F6R1_FB12_Pos (12U)
3453#define CAN_F6R1_FB12_Msk (0x1UL << CAN_F6R1_FB12_Pos)
3454#define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk
3455#define CAN_F6R1_FB13_Pos (13U)
3456#define CAN_F6R1_FB13_Msk (0x1UL << CAN_F6R1_FB13_Pos)
3457#define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk
3458#define CAN_F6R1_FB14_Pos (14U)
3459#define CAN_F6R1_FB14_Msk (0x1UL << CAN_F6R1_FB14_Pos)
3460#define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk
3461#define CAN_F6R1_FB15_Pos (15U)
3462#define CAN_F6R1_FB15_Msk (0x1UL << CAN_F6R1_FB15_Pos)
3463#define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk
3464#define CAN_F6R1_FB16_Pos (16U)
3465#define CAN_F6R1_FB16_Msk (0x1UL << CAN_F6R1_FB16_Pos)
3466#define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk
3467#define CAN_F6R1_FB17_Pos (17U)
3468#define CAN_F6R1_FB17_Msk (0x1UL << CAN_F6R1_FB17_Pos)
3469#define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk
3470#define CAN_F6R1_FB18_Pos (18U)
3471#define CAN_F6R1_FB18_Msk (0x1UL << CAN_F6R1_FB18_Pos)
3472#define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk
3473#define CAN_F6R1_FB19_Pos (19U)
3474#define CAN_F6R1_FB19_Msk (0x1UL << CAN_F6R1_FB19_Pos)
3475#define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk
3476#define CAN_F6R1_FB20_Pos (20U)
3477#define CAN_F6R1_FB20_Msk (0x1UL << CAN_F6R1_FB20_Pos)
3478#define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk
3479#define CAN_F6R1_FB21_Pos (21U)
3480#define CAN_F6R1_FB21_Msk (0x1UL << CAN_F6R1_FB21_Pos)
3481#define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk
3482#define CAN_F6R1_FB22_Pos (22U)
3483#define CAN_F6R1_FB22_Msk (0x1UL << CAN_F6R1_FB22_Pos)
3484#define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk
3485#define CAN_F6R1_FB23_Pos (23U)
3486#define CAN_F6R1_FB23_Msk (0x1UL << CAN_F6R1_FB23_Pos)
3487#define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk
3488#define CAN_F6R1_FB24_Pos (24U)
3489#define CAN_F6R1_FB24_Msk (0x1UL << CAN_F6R1_FB24_Pos)
3490#define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk
3491#define CAN_F6R1_FB25_Pos (25U)
3492#define CAN_F6R1_FB25_Msk (0x1UL << CAN_F6R1_FB25_Pos)
3493#define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk
3494#define CAN_F6R1_FB26_Pos (26U)
3495#define CAN_F6R1_FB26_Msk (0x1UL << CAN_F6R1_FB26_Pos)
3496#define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk
3497#define CAN_F6R1_FB27_Pos (27U)
3498#define CAN_F6R1_FB27_Msk (0x1UL << CAN_F6R1_FB27_Pos)
3499#define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk
3500#define CAN_F6R1_FB28_Pos (28U)
3501#define CAN_F6R1_FB28_Msk (0x1UL << CAN_F6R1_FB28_Pos)
3502#define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk
3503#define CAN_F6R1_FB29_Pos (29U)
3504#define CAN_F6R1_FB29_Msk (0x1UL << CAN_F6R1_FB29_Pos)
3505#define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk
3506#define CAN_F6R1_FB30_Pos (30U)
3507#define CAN_F6R1_FB30_Msk (0x1UL << CAN_F6R1_FB30_Pos)
3508#define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk
3509#define CAN_F6R1_FB31_Pos (31U)
3510#define CAN_F6R1_FB31_Msk (0x1UL << CAN_F6R1_FB31_Pos)
3511#define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk
3512
3513/******************* Bit definition for CAN_F7R1 register *******************/
3514#define CAN_F7R1_FB0_Pos (0U)
3515#define CAN_F7R1_FB0_Msk (0x1UL << CAN_F7R1_FB0_Pos)
3516#define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk
3517#define CAN_F7R1_FB1_Pos (1U)
3518#define CAN_F7R1_FB1_Msk (0x1UL << CAN_F7R1_FB1_Pos)
3519#define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk
3520#define CAN_F7R1_FB2_Pos (2U)
3521#define CAN_F7R1_FB2_Msk (0x1UL << CAN_F7R1_FB2_Pos)
3522#define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk
3523#define CAN_F7R1_FB3_Pos (3U)
3524#define CAN_F7R1_FB3_Msk (0x1UL << CAN_F7R1_FB3_Pos)
3525#define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk
3526#define CAN_F7R1_FB4_Pos (4U)
3527#define CAN_F7R1_FB4_Msk (0x1UL << CAN_F7R1_FB4_Pos)
3528#define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk
3529#define CAN_F7R1_FB5_Pos (5U)
3530#define CAN_F7R1_FB5_Msk (0x1UL << CAN_F7R1_FB5_Pos)
3531#define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk
3532#define CAN_F7R1_FB6_Pos (6U)
3533#define CAN_F7R1_FB6_Msk (0x1UL << CAN_F7R1_FB6_Pos)
3534#define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk
3535#define CAN_F7R1_FB7_Pos (7U)
3536#define CAN_F7R1_FB7_Msk (0x1UL << CAN_F7R1_FB7_Pos)
3537#define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk
3538#define CAN_F7R1_FB8_Pos (8U)
3539#define CAN_F7R1_FB8_Msk (0x1UL << CAN_F7R1_FB8_Pos)
3540#define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk
3541#define CAN_F7R1_FB9_Pos (9U)
3542#define CAN_F7R1_FB9_Msk (0x1UL << CAN_F7R1_FB9_Pos)
3543#define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk
3544#define CAN_F7R1_FB10_Pos (10U)
3545#define CAN_F7R1_FB10_Msk (0x1UL << CAN_F7R1_FB10_Pos)
3546#define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk
3547#define CAN_F7R1_FB11_Pos (11U)
3548#define CAN_F7R1_FB11_Msk (0x1UL << CAN_F7R1_FB11_Pos)
3549#define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk
3550#define CAN_F7R1_FB12_Pos (12U)
3551#define CAN_F7R1_FB12_Msk (0x1UL << CAN_F7R1_FB12_Pos)
3552#define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk
3553#define CAN_F7R1_FB13_Pos (13U)
3554#define CAN_F7R1_FB13_Msk (0x1UL << CAN_F7R1_FB13_Pos)
3555#define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk
3556#define CAN_F7R1_FB14_Pos (14U)
3557#define CAN_F7R1_FB14_Msk (0x1UL << CAN_F7R1_FB14_Pos)
3558#define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk
3559#define CAN_F7R1_FB15_Pos (15U)
3560#define CAN_F7R1_FB15_Msk (0x1UL << CAN_F7R1_FB15_Pos)
3561#define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk
3562#define CAN_F7R1_FB16_Pos (16U)
3563#define CAN_F7R1_FB16_Msk (0x1UL << CAN_F7R1_FB16_Pos)
3564#define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk
3565#define CAN_F7R1_FB17_Pos (17U)
3566#define CAN_F7R1_FB17_Msk (0x1UL << CAN_F7R1_FB17_Pos)
3567#define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk
3568#define CAN_F7R1_FB18_Pos (18U)
3569#define CAN_F7R1_FB18_Msk (0x1UL << CAN_F7R1_FB18_Pos)
3570#define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk
3571#define CAN_F7R1_FB19_Pos (19U)
3572#define CAN_F7R1_FB19_Msk (0x1UL << CAN_F7R1_FB19_Pos)
3573#define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk
3574#define CAN_F7R1_FB20_Pos (20U)
3575#define CAN_F7R1_FB20_Msk (0x1UL << CAN_F7R1_FB20_Pos)
3576#define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk
3577#define CAN_F7R1_FB21_Pos (21U)
3578#define CAN_F7R1_FB21_Msk (0x1UL << CAN_F7R1_FB21_Pos)
3579#define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk
3580#define CAN_F7R1_FB22_Pos (22U)
3581#define CAN_F7R1_FB22_Msk (0x1UL << CAN_F7R1_FB22_Pos)
3582#define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk
3583#define CAN_F7R1_FB23_Pos (23U)
3584#define CAN_F7R1_FB23_Msk (0x1UL << CAN_F7R1_FB23_Pos)
3585#define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk
3586#define CAN_F7R1_FB24_Pos (24U)
3587#define CAN_F7R1_FB24_Msk (0x1UL << CAN_F7R1_FB24_Pos)
3588#define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk
3589#define CAN_F7R1_FB25_Pos (25U)
3590#define CAN_F7R1_FB25_Msk (0x1UL << CAN_F7R1_FB25_Pos)
3591#define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk
3592#define CAN_F7R1_FB26_Pos (26U)
3593#define CAN_F7R1_FB26_Msk (0x1UL << CAN_F7R1_FB26_Pos)
3594#define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk
3595#define CAN_F7R1_FB27_Pos (27U)
3596#define CAN_F7R1_FB27_Msk (0x1UL << CAN_F7R1_FB27_Pos)
3597#define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk
3598#define CAN_F7R1_FB28_Pos (28U)
3599#define CAN_F7R1_FB28_Msk (0x1UL << CAN_F7R1_FB28_Pos)
3600#define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk
3601#define CAN_F7R1_FB29_Pos (29U)
3602#define CAN_F7R1_FB29_Msk (0x1UL << CAN_F7R1_FB29_Pos)
3603#define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk
3604#define CAN_F7R1_FB30_Pos (30U)
3605#define CAN_F7R1_FB30_Msk (0x1UL << CAN_F7R1_FB30_Pos)
3606#define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk
3607#define CAN_F7R1_FB31_Pos (31U)
3608#define CAN_F7R1_FB31_Msk (0x1UL << CAN_F7R1_FB31_Pos)
3609#define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk
3610
3611/******************* Bit definition for CAN_F8R1 register *******************/
3612#define CAN_F8R1_FB0_Pos (0U)
3613#define CAN_F8R1_FB0_Msk (0x1UL << CAN_F8R1_FB0_Pos)
3614#define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk
3615#define CAN_F8R1_FB1_Pos (1U)
3616#define CAN_F8R1_FB1_Msk (0x1UL << CAN_F8R1_FB1_Pos)
3617#define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk
3618#define CAN_F8R1_FB2_Pos (2U)
3619#define CAN_F8R1_FB2_Msk (0x1UL << CAN_F8R1_FB2_Pos)
3620#define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk
3621#define CAN_F8R1_FB3_Pos (3U)
3622#define CAN_F8R1_FB3_Msk (0x1UL << CAN_F8R1_FB3_Pos)
3623#define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk
3624#define CAN_F8R1_FB4_Pos (4U)
3625#define CAN_F8R1_FB4_Msk (0x1UL << CAN_F8R1_FB4_Pos)
3626#define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk
3627#define CAN_F8R1_FB5_Pos (5U)
3628#define CAN_F8R1_FB5_Msk (0x1UL << CAN_F8R1_FB5_Pos)
3629#define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk
3630#define CAN_F8R1_FB6_Pos (6U)
3631#define CAN_F8R1_FB6_Msk (0x1UL << CAN_F8R1_FB6_Pos)
3632#define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk
3633#define CAN_F8R1_FB7_Pos (7U)
3634#define CAN_F8R1_FB7_Msk (0x1UL << CAN_F8R1_FB7_Pos)
3635#define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk
3636#define CAN_F8R1_FB8_Pos (8U)
3637#define CAN_F8R1_FB8_Msk (0x1UL << CAN_F8R1_FB8_Pos)
3638#define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk
3639#define CAN_F8R1_FB9_Pos (9U)
3640#define CAN_F8R1_FB9_Msk (0x1UL << CAN_F8R1_FB9_Pos)
3641#define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk
3642#define CAN_F8R1_FB10_Pos (10U)
3643#define CAN_F8R1_FB10_Msk (0x1UL << CAN_F8R1_FB10_Pos)
3644#define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk
3645#define CAN_F8R1_FB11_Pos (11U)
3646#define CAN_F8R1_FB11_Msk (0x1UL << CAN_F8R1_FB11_Pos)
3647#define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk
3648#define CAN_F8R1_FB12_Pos (12U)
3649#define CAN_F8R1_FB12_Msk (0x1UL << CAN_F8R1_FB12_Pos)
3650#define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk
3651#define CAN_F8R1_FB13_Pos (13U)
3652#define CAN_F8R1_FB13_Msk (0x1UL << CAN_F8R1_FB13_Pos)
3653#define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk
3654#define CAN_F8R1_FB14_Pos (14U)
3655#define CAN_F8R1_FB14_Msk (0x1UL << CAN_F8R1_FB14_Pos)
3656#define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk
3657#define CAN_F8R1_FB15_Pos (15U)
3658#define CAN_F8R1_FB15_Msk (0x1UL << CAN_F8R1_FB15_Pos)
3659#define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk
3660#define CAN_F8R1_FB16_Pos (16U)
3661#define CAN_F8R1_FB16_Msk (0x1UL << CAN_F8R1_FB16_Pos)
3662#define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk
3663#define CAN_F8R1_FB17_Pos (17U)
3664#define CAN_F8R1_FB17_Msk (0x1UL << CAN_F8R1_FB17_Pos)
3665#define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk
3666#define CAN_F8R1_FB18_Pos (18U)
3667#define CAN_F8R1_FB18_Msk (0x1UL << CAN_F8R1_FB18_Pos)
3668#define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk
3669#define CAN_F8R1_FB19_Pos (19U)
3670#define CAN_F8R1_FB19_Msk (0x1UL << CAN_F8R1_FB19_Pos)
3671#define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk
3672#define CAN_F8R1_FB20_Pos (20U)
3673#define CAN_F8R1_FB20_Msk (0x1UL << CAN_F8R1_FB20_Pos)
3674#define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk
3675#define CAN_F8R1_FB21_Pos (21U)
3676#define CAN_F8R1_FB21_Msk (0x1UL << CAN_F8R1_FB21_Pos)
3677#define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk
3678#define CAN_F8R1_FB22_Pos (22U)
3679#define CAN_F8R1_FB22_Msk (0x1UL << CAN_F8R1_FB22_Pos)
3680#define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk
3681#define CAN_F8R1_FB23_Pos (23U)
3682#define CAN_F8R1_FB23_Msk (0x1UL << CAN_F8R1_FB23_Pos)
3683#define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk
3684#define CAN_F8R1_FB24_Pos (24U)
3685#define CAN_F8R1_FB24_Msk (0x1UL << CAN_F8R1_FB24_Pos)
3686#define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk
3687#define CAN_F8R1_FB25_Pos (25U)
3688#define CAN_F8R1_FB25_Msk (0x1UL << CAN_F8R1_FB25_Pos)
3689#define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk
3690#define CAN_F8R1_FB26_Pos (26U)
3691#define CAN_F8R1_FB26_Msk (0x1UL << CAN_F8R1_FB26_Pos)
3692#define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk
3693#define CAN_F8R1_FB27_Pos (27U)
3694#define CAN_F8R1_FB27_Msk (0x1UL << CAN_F8R1_FB27_Pos)
3695#define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk
3696#define CAN_F8R1_FB28_Pos (28U)
3697#define CAN_F8R1_FB28_Msk (0x1UL << CAN_F8R1_FB28_Pos)
3698#define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk
3699#define CAN_F8R1_FB29_Pos (29U)
3700#define CAN_F8R1_FB29_Msk (0x1UL << CAN_F8R1_FB29_Pos)
3701#define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk
3702#define CAN_F8R1_FB30_Pos (30U)
3703#define CAN_F8R1_FB30_Msk (0x1UL << CAN_F8R1_FB30_Pos)
3704#define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk
3705#define CAN_F8R1_FB31_Pos (31U)
3706#define CAN_F8R1_FB31_Msk (0x1UL << CAN_F8R1_FB31_Pos)
3707#define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk
3708
3709/******************* Bit definition for CAN_F9R1 register *******************/
3710#define CAN_F9R1_FB0_Pos (0U)
3711#define CAN_F9R1_FB0_Msk (0x1UL << CAN_F9R1_FB0_Pos)
3712#define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk
3713#define CAN_F9R1_FB1_Pos (1U)
3714#define CAN_F9R1_FB1_Msk (0x1UL << CAN_F9R1_FB1_Pos)
3715#define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk
3716#define CAN_F9R1_FB2_Pos (2U)
3717#define CAN_F9R1_FB2_Msk (0x1UL << CAN_F9R1_FB2_Pos)
3718#define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk
3719#define CAN_F9R1_FB3_Pos (3U)
3720#define CAN_F9R1_FB3_Msk (0x1UL << CAN_F9R1_FB3_Pos)
3721#define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk
3722#define CAN_F9R1_FB4_Pos (4U)
3723#define CAN_F9R1_FB4_Msk (0x1UL << CAN_F9R1_FB4_Pos)
3724#define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk
3725#define CAN_F9R1_FB5_Pos (5U)
3726#define CAN_F9R1_FB5_Msk (0x1UL << CAN_F9R1_FB5_Pos)
3727#define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk
3728#define CAN_F9R1_FB6_Pos (6U)
3729#define CAN_F9R1_FB6_Msk (0x1UL << CAN_F9R1_FB6_Pos)
3730#define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk
3731#define CAN_F9R1_FB7_Pos (7U)
3732#define CAN_F9R1_FB7_Msk (0x1UL << CAN_F9R1_FB7_Pos)
3733#define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk
3734#define CAN_F9R1_FB8_Pos (8U)
3735#define CAN_F9R1_FB8_Msk (0x1UL << CAN_F9R1_FB8_Pos)
3736#define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk
3737#define CAN_F9R1_FB9_Pos (9U)
3738#define CAN_F9R1_FB9_Msk (0x1UL << CAN_F9R1_FB9_Pos)
3739#define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk
3740#define CAN_F9R1_FB10_Pos (10U)
3741#define CAN_F9R1_FB10_Msk (0x1UL << CAN_F9R1_FB10_Pos)
3742#define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk
3743#define CAN_F9R1_FB11_Pos (11U)
3744#define CAN_F9R1_FB11_Msk (0x1UL << CAN_F9R1_FB11_Pos)
3745#define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk
3746#define CAN_F9R1_FB12_Pos (12U)
3747#define CAN_F9R1_FB12_Msk (0x1UL << CAN_F9R1_FB12_Pos)
3748#define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk
3749#define CAN_F9R1_FB13_Pos (13U)
3750#define CAN_F9R1_FB13_Msk (0x1UL << CAN_F9R1_FB13_Pos)
3751#define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk
3752#define CAN_F9R1_FB14_Pos (14U)
3753#define CAN_F9R1_FB14_Msk (0x1UL << CAN_F9R1_FB14_Pos)
3754#define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk
3755#define CAN_F9R1_FB15_Pos (15U)
3756#define CAN_F9R1_FB15_Msk (0x1UL << CAN_F9R1_FB15_Pos)
3757#define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk
3758#define CAN_F9R1_FB16_Pos (16U)
3759#define CAN_F9R1_FB16_Msk (0x1UL << CAN_F9R1_FB16_Pos)
3760#define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk
3761#define CAN_F9R1_FB17_Pos (17U)
3762#define CAN_F9R1_FB17_Msk (0x1UL << CAN_F9R1_FB17_Pos)
3763#define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk
3764#define CAN_F9R1_FB18_Pos (18U)
3765#define CAN_F9R1_FB18_Msk (0x1UL << CAN_F9R1_FB18_Pos)
3766#define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk
3767#define CAN_F9R1_FB19_Pos (19U)
3768#define CAN_F9R1_FB19_Msk (0x1UL << CAN_F9R1_FB19_Pos)
3769#define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk
3770#define CAN_F9R1_FB20_Pos (20U)
3771#define CAN_F9R1_FB20_Msk (0x1UL << CAN_F9R1_FB20_Pos)
3772#define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk
3773#define CAN_F9R1_FB21_Pos (21U)
3774#define CAN_F9R1_FB21_Msk (0x1UL << CAN_F9R1_FB21_Pos)
3775#define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk
3776#define CAN_F9R1_FB22_Pos (22U)
3777#define CAN_F9R1_FB22_Msk (0x1UL << CAN_F9R1_FB22_Pos)
3778#define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk
3779#define CAN_F9R1_FB23_Pos (23U)
3780#define CAN_F9R1_FB23_Msk (0x1UL << CAN_F9R1_FB23_Pos)
3781#define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk
3782#define CAN_F9R1_FB24_Pos (24U)
3783#define CAN_F9R1_FB24_Msk (0x1UL << CAN_F9R1_FB24_Pos)
3784#define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk
3785#define CAN_F9R1_FB25_Pos (25U)
3786#define CAN_F9R1_FB25_Msk (0x1UL << CAN_F9R1_FB25_Pos)
3787#define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk
3788#define CAN_F9R1_FB26_Pos (26U)
3789#define CAN_F9R1_FB26_Msk (0x1UL << CAN_F9R1_FB26_Pos)
3790#define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk
3791#define CAN_F9R1_FB27_Pos (27U)
3792#define CAN_F9R1_FB27_Msk (0x1UL << CAN_F9R1_FB27_Pos)
3793#define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk
3794#define CAN_F9R1_FB28_Pos (28U)
3795#define CAN_F9R1_FB28_Msk (0x1UL << CAN_F9R1_FB28_Pos)
3796#define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk
3797#define CAN_F9R1_FB29_Pos (29U)
3798#define CAN_F9R1_FB29_Msk (0x1UL << CAN_F9R1_FB29_Pos)
3799#define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk
3800#define CAN_F9R1_FB30_Pos (30U)
3801#define CAN_F9R1_FB30_Msk (0x1UL << CAN_F9R1_FB30_Pos)
3802#define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk
3803#define CAN_F9R1_FB31_Pos (31U)
3804#define CAN_F9R1_FB31_Msk (0x1UL << CAN_F9R1_FB31_Pos)
3805#define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk
3806
3807/******************* Bit definition for CAN_F10R1 register ******************/
3808#define CAN_F10R1_FB0_Pos (0U)
3809#define CAN_F10R1_FB0_Msk (0x1UL << CAN_F10R1_FB0_Pos)
3810#define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk
3811#define CAN_F10R1_FB1_Pos (1U)
3812#define CAN_F10R1_FB1_Msk (0x1UL << CAN_F10R1_FB1_Pos)
3813#define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk
3814#define CAN_F10R1_FB2_Pos (2U)
3815#define CAN_F10R1_FB2_Msk (0x1UL << CAN_F10R1_FB2_Pos)
3816#define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk
3817#define CAN_F10R1_FB3_Pos (3U)
3818#define CAN_F10R1_FB3_Msk (0x1UL << CAN_F10R1_FB3_Pos)
3819#define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk
3820#define CAN_F10R1_FB4_Pos (4U)
3821#define CAN_F10R1_FB4_Msk (0x1UL << CAN_F10R1_FB4_Pos)
3822#define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk
3823#define CAN_F10R1_FB5_Pos (5U)
3824#define CAN_F10R1_FB5_Msk (0x1UL << CAN_F10R1_FB5_Pos)
3825#define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk
3826#define CAN_F10R1_FB6_Pos (6U)
3827#define CAN_F10R1_FB6_Msk (0x1UL << CAN_F10R1_FB6_Pos)
3828#define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk
3829#define CAN_F10R1_FB7_Pos (7U)
3830#define CAN_F10R1_FB7_Msk (0x1UL << CAN_F10R1_FB7_Pos)
3831#define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk
3832#define CAN_F10R1_FB8_Pos (8U)
3833#define CAN_F10R1_FB8_Msk (0x1UL << CAN_F10R1_FB8_Pos)
3834#define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk
3835#define CAN_F10R1_FB9_Pos (9U)
3836#define CAN_F10R1_FB9_Msk (0x1UL << CAN_F10R1_FB9_Pos)
3837#define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk
3838#define CAN_F10R1_FB10_Pos (10U)
3839#define CAN_F10R1_FB10_Msk (0x1UL << CAN_F10R1_FB10_Pos)
3840#define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk
3841#define CAN_F10R1_FB11_Pos (11U)
3842#define CAN_F10R1_FB11_Msk (0x1UL << CAN_F10R1_FB11_Pos)
3843#define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk
3844#define CAN_F10R1_FB12_Pos (12U)
3845#define CAN_F10R1_FB12_Msk (0x1UL << CAN_F10R1_FB12_Pos)
3846#define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk
3847#define CAN_F10R1_FB13_Pos (13U)
3848#define CAN_F10R1_FB13_Msk (0x1UL << CAN_F10R1_FB13_Pos)
3849#define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk
3850#define CAN_F10R1_FB14_Pos (14U)
3851#define CAN_F10R1_FB14_Msk (0x1UL << CAN_F10R1_FB14_Pos)
3852#define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk
3853#define CAN_F10R1_FB15_Pos (15U)
3854#define CAN_F10R1_FB15_Msk (0x1UL << CAN_F10R1_FB15_Pos)
3855#define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk
3856#define CAN_F10R1_FB16_Pos (16U)
3857#define CAN_F10R1_FB16_Msk (0x1UL << CAN_F10R1_FB16_Pos)
3858#define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk
3859#define CAN_F10R1_FB17_Pos (17U)
3860#define CAN_F10R1_FB17_Msk (0x1UL << CAN_F10R1_FB17_Pos)
3861#define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk
3862#define CAN_F10R1_FB18_Pos (18U)
3863#define CAN_F10R1_FB18_Msk (0x1UL << CAN_F10R1_FB18_Pos)
3864#define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk
3865#define CAN_F10R1_FB19_Pos (19U)
3866#define CAN_F10R1_FB19_Msk (0x1UL << CAN_F10R1_FB19_Pos)
3867#define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk
3868#define CAN_F10R1_FB20_Pos (20U)
3869#define CAN_F10R1_FB20_Msk (0x1UL << CAN_F10R1_FB20_Pos)
3870#define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk
3871#define CAN_F10R1_FB21_Pos (21U)
3872#define CAN_F10R1_FB21_Msk (0x1UL << CAN_F10R1_FB21_Pos)
3873#define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk
3874#define CAN_F10R1_FB22_Pos (22U)
3875#define CAN_F10R1_FB22_Msk (0x1UL << CAN_F10R1_FB22_Pos)
3876#define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk
3877#define CAN_F10R1_FB23_Pos (23U)
3878#define CAN_F10R1_FB23_Msk (0x1UL << CAN_F10R1_FB23_Pos)
3879#define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk
3880#define CAN_F10R1_FB24_Pos (24U)
3881#define CAN_F10R1_FB24_Msk (0x1UL << CAN_F10R1_FB24_Pos)
3882#define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk
3883#define CAN_F10R1_FB25_Pos (25U)
3884#define CAN_F10R1_FB25_Msk (0x1UL << CAN_F10R1_FB25_Pos)
3885#define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk
3886#define CAN_F10R1_FB26_Pos (26U)
3887#define CAN_F10R1_FB26_Msk (0x1UL << CAN_F10R1_FB26_Pos)
3888#define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk
3889#define CAN_F10R1_FB27_Pos (27U)
3890#define CAN_F10R1_FB27_Msk (0x1UL << CAN_F10R1_FB27_Pos)
3891#define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk
3892#define CAN_F10R1_FB28_Pos (28U)
3893#define CAN_F10R1_FB28_Msk (0x1UL << CAN_F10R1_FB28_Pos)
3894#define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk
3895#define CAN_F10R1_FB29_Pos (29U)
3896#define CAN_F10R1_FB29_Msk (0x1UL << CAN_F10R1_FB29_Pos)
3897#define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk
3898#define CAN_F10R1_FB30_Pos (30U)
3899#define CAN_F10R1_FB30_Msk (0x1UL << CAN_F10R1_FB30_Pos)
3900#define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk
3901#define CAN_F10R1_FB31_Pos (31U)
3902#define CAN_F10R1_FB31_Msk (0x1UL << CAN_F10R1_FB31_Pos)
3903#define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk
3904
3905/******************* Bit definition for CAN_F11R1 register ******************/
3906#define CAN_F11R1_FB0_Pos (0U)
3907#define CAN_F11R1_FB0_Msk (0x1UL << CAN_F11R1_FB0_Pos)
3908#define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk
3909#define CAN_F11R1_FB1_Pos (1U)
3910#define CAN_F11R1_FB1_Msk (0x1UL << CAN_F11R1_FB1_Pos)
3911#define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk
3912#define CAN_F11R1_FB2_Pos (2U)
3913#define CAN_F11R1_FB2_Msk (0x1UL << CAN_F11R1_FB2_Pos)
3914#define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk
3915#define CAN_F11R1_FB3_Pos (3U)
3916#define CAN_F11R1_FB3_Msk (0x1UL << CAN_F11R1_FB3_Pos)
3917#define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk
3918#define CAN_F11R1_FB4_Pos (4U)
3919#define CAN_F11R1_FB4_Msk (0x1UL << CAN_F11R1_FB4_Pos)
3920#define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk
3921#define CAN_F11R1_FB5_Pos (5U)
3922#define CAN_F11R1_FB5_Msk (0x1UL << CAN_F11R1_FB5_Pos)
3923#define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk
3924#define CAN_F11R1_FB6_Pos (6U)
3925#define CAN_F11R1_FB6_Msk (0x1UL << CAN_F11R1_FB6_Pos)
3926#define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk
3927#define CAN_F11R1_FB7_Pos (7U)
3928#define CAN_F11R1_FB7_Msk (0x1UL << CAN_F11R1_FB7_Pos)
3929#define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk
3930#define CAN_F11R1_FB8_Pos (8U)
3931#define CAN_F11R1_FB8_Msk (0x1UL << CAN_F11R1_FB8_Pos)
3932#define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk
3933#define CAN_F11R1_FB9_Pos (9U)
3934#define CAN_F11R1_FB9_Msk (0x1UL << CAN_F11R1_FB9_Pos)
3935#define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk
3936#define CAN_F11R1_FB10_Pos (10U)
3937#define CAN_F11R1_FB10_Msk (0x1UL << CAN_F11R1_FB10_Pos)
3938#define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk
3939#define CAN_F11R1_FB11_Pos (11U)
3940#define CAN_F11R1_FB11_Msk (0x1UL << CAN_F11R1_FB11_Pos)
3941#define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk
3942#define CAN_F11R1_FB12_Pos (12U)
3943#define CAN_F11R1_FB12_Msk (0x1UL << CAN_F11R1_FB12_Pos)
3944#define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk
3945#define CAN_F11R1_FB13_Pos (13U)
3946#define CAN_F11R1_FB13_Msk (0x1UL << CAN_F11R1_FB13_Pos)
3947#define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk
3948#define CAN_F11R1_FB14_Pos (14U)
3949#define CAN_F11R1_FB14_Msk (0x1UL << CAN_F11R1_FB14_Pos)
3950#define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk
3951#define CAN_F11R1_FB15_Pos (15U)
3952#define CAN_F11R1_FB15_Msk (0x1UL << CAN_F11R1_FB15_Pos)
3953#define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk
3954#define CAN_F11R1_FB16_Pos (16U)
3955#define CAN_F11R1_FB16_Msk (0x1UL << CAN_F11R1_FB16_Pos)
3956#define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk
3957#define CAN_F11R1_FB17_Pos (17U)
3958#define CAN_F11R1_FB17_Msk (0x1UL << CAN_F11R1_FB17_Pos)
3959#define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk
3960#define CAN_F11R1_FB18_Pos (18U)
3961#define CAN_F11R1_FB18_Msk (0x1UL << CAN_F11R1_FB18_Pos)
3962#define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk
3963#define CAN_F11R1_FB19_Pos (19U)
3964#define CAN_F11R1_FB19_Msk (0x1UL << CAN_F11R1_FB19_Pos)
3965#define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk
3966#define CAN_F11R1_FB20_Pos (20U)
3967#define CAN_F11R1_FB20_Msk (0x1UL << CAN_F11R1_FB20_Pos)
3968#define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk
3969#define CAN_F11R1_FB21_Pos (21U)
3970#define CAN_F11R1_FB21_Msk (0x1UL << CAN_F11R1_FB21_Pos)
3971#define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk
3972#define CAN_F11R1_FB22_Pos (22U)
3973#define CAN_F11R1_FB22_Msk (0x1UL << CAN_F11R1_FB22_Pos)
3974#define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk
3975#define CAN_F11R1_FB23_Pos (23U)
3976#define CAN_F11R1_FB23_Msk (0x1UL << CAN_F11R1_FB23_Pos)
3977#define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk
3978#define CAN_F11R1_FB24_Pos (24U)
3979#define CAN_F11R1_FB24_Msk (0x1UL << CAN_F11R1_FB24_Pos)
3980#define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk
3981#define CAN_F11R1_FB25_Pos (25U)
3982#define CAN_F11R1_FB25_Msk (0x1UL << CAN_F11R1_FB25_Pos)
3983#define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk
3984#define CAN_F11R1_FB26_Pos (26U)
3985#define CAN_F11R1_FB26_Msk (0x1UL << CAN_F11R1_FB26_Pos)
3986#define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk
3987#define CAN_F11R1_FB27_Pos (27U)
3988#define CAN_F11R1_FB27_Msk (0x1UL << CAN_F11R1_FB27_Pos)
3989#define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk
3990#define CAN_F11R1_FB28_Pos (28U)
3991#define CAN_F11R1_FB28_Msk (0x1UL << CAN_F11R1_FB28_Pos)
3992#define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk
3993#define CAN_F11R1_FB29_Pos (29U)
3994#define CAN_F11R1_FB29_Msk (0x1UL << CAN_F11R1_FB29_Pos)
3995#define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk
3996#define CAN_F11R1_FB30_Pos (30U)
3997#define CAN_F11R1_FB30_Msk (0x1UL << CAN_F11R1_FB30_Pos)
3998#define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk
3999#define CAN_F11R1_FB31_Pos (31U)
4000#define CAN_F11R1_FB31_Msk (0x1UL << CAN_F11R1_FB31_Pos)
4001#define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk
4002
4003/******************* Bit definition for CAN_F12R1 register ******************/
4004#define CAN_F12R1_FB0_Pos (0U)
4005#define CAN_F12R1_FB0_Msk (0x1UL << CAN_F12R1_FB0_Pos)
4006#define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk
4007#define CAN_F12R1_FB1_Pos (1U)
4008#define CAN_F12R1_FB1_Msk (0x1UL << CAN_F12R1_FB1_Pos)
4009#define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk
4010#define CAN_F12R1_FB2_Pos (2U)
4011#define CAN_F12R1_FB2_Msk (0x1UL << CAN_F12R1_FB2_Pos)
4012#define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk
4013#define CAN_F12R1_FB3_Pos (3U)
4014#define CAN_F12R1_FB3_Msk (0x1UL << CAN_F12R1_FB3_Pos)
4015#define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk
4016#define CAN_F12R1_FB4_Pos (4U)
4017#define CAN_F12R1_FB4_Msk (0x1UL << CAN_F12R1_FB4_Pos)
4018#define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk
4019#define CAN_F12R1_FB5_Pos (5U)
4020#define CAN_F12R1_FB5_Msk (0x1UL << CAN_F12R1_FB5_Pos)
4021#define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk
4022#define CAN_F12R1_FB6_Pos (6U)
4023#define CAN_F12R1_FB6_Msk (0x1UL << CAN_F12R1_FB6_Pos)
4024#define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk
4025#define CAN_F12R1_FB7_Pos (7U)
4026#define CAN_F12R1_FB7_Msk (0x1UL << CAN_F12R1_FB7_Pos)
4027#define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk
4028#define CAN_F12R1_FB8_Pos (8U)
4029#define CAN_F12R1_FB8_Msk (0x1UL << CAN_F12R1_FB8_Pos)
4030#define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk
4031#define CAN_F12R1_FB9_Pos (9U)
4032#define CAN_F12R1_FB9_Msk (0x1UL << CAN_F12R1_FB9_Pos)
4033#define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk
4034#define CAN_F12R1_FB10_Pos (10U)
4035#define CAN_F12R1_FB10_Msk (0x1UL << CAN_F12R1_FB10_Pos)
4036#define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk
4037#define CAN_F12R1_FB11_Pos (11U)
4038#define CAN_F12R1_FB11_Msk (0x1UL << CAN_F12R1_FB11_Pos)
4039#define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk
4040#define CAN_F12R1_FB12_Pos (12U)
4041#define CAN_F12R1_FB12_Msk (0x1UL << CAN_F12R1_FB12_Pos)
4042#define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk
4043#define CAN_F12R1_FB13_Pos (13U)
4044#define CAN_F12R1_FB13_Msk (0x1UL << CAN_F12R1_FB13_Pos)
4045#define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk
4046#define CAN_F12R1_FB14_Pos (14U)
4047#define CAN_F12R1_FB14_Msk (0x1UL << CAN_F12R1_FB14_Pos)
4048#define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk
4049#define CAN_F12R1_FB15_Pos (15U)
4050#define CAN_F12R1_FB15_Msk (0x1UL << CAN_F12R1_FB15_Pos)
4051#define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk
4052#define CAN_F12R1_FB16_Pos (16U)
4053#define CAN_F12R1_FB16_Msk (0x1UL << CAN_F12R1_FB16_Pos)
4054#define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk
4055#define CAN_F12R1_FB17_Pos (17U)
4056#define CAN_F12R1_FB17_Msk (0x1UL << CAN_F12R1_FB17_Pos)
4057#define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk
4058#define CAN_F12R1_FB18_Pos (18U)
4059#define CAN_F12R1_FB18_Msk (0x1UL << CAN_F12R1_FB18_Pos)
4060#define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk
4061#define CAN_F12R1_FB19_Pos (19U)
4062#define CAN_F12R1_FB19_Msk (0x1UL << CAN_F12R1_FB19_Pos)
4063#define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk
4064#define CAN_F12R1_FB20_Pos (20U)
4065#define CAN_F12R1_FB20_Msk (0x1UL << CAN_F12R1_FB20_Pos)
4066#define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk
4067#define CAN_F12R1_FB21_Pos (21U)
4068#define CAN_F12R1_FB21_Msk (0x1UL << CAN_F12R1_FB21_Pos)
4069#define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk
4070#define CAN_F12R1_FB22_Pos (22U)
4071#define CAN_F12R1_FB22_Msk (0x1UL << CAN_F12R1_FB22_Pos)
4072#define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk
4073#define CAN_F12R1_FB23_Pos (23U)
4074#define CAN_F12R1_FB23_Msk (0x1UL << CAN_F12R1_FB23_Pos)
4075#define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk
4076#define CAN_F12R1_FB24_Pos (24U)
4077#define CAN_F12R1_FB24_Msk (0x1UL << CAN_F12R1_FB24_Pos)
4078#define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk
4079#define CAN_F12R1_FB25_Pos (25U)
4080#define CAN_F12R1_FB25_Msk (0x1UL << CAN_F12R1_FB25_Pos)
4081#define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk
4082#define CAN_F12R1_FB26_Pos (26U)
4083#define CAN_F12R1_FB26_Msk (0x1UL << CAN_F12R1_FB26_Pos)
4084#define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk
4085#define CAN_F12R1_FB27_Pos (27U)
4086#define CAN_F12R1_FB27_Msk (0x1UL << CAN_F12R1_FB27_Pos)
4087#define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk
4088#define CAN_F12R1_FB28_Pos (28U)
4089#define CAN_F12R1_FB28_Msk (0x1UL << CAN_F12R1_FB28_Pos)
4090#define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk
4091#define CAN_F12R1_FB29_Pos (29U)
4092#define CAN_F12R1_FB29_Msk (0x1UL << CAN_F12R1_FB29_Pos)
4093#define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk
4094#define CAN_F12R1_FB30_Pos (30U)
4095#define CAN_F12R1_FB30_Msk (0x1UL << CAN_F12R1_FB30_Pos)
4096#define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk
4097#define CAN_F12R1_FB31_Pos (31U)
4098#define CAN_F12R1_FB31_Msk (0x1UL << CAN_F12R1_FB31_Pos)
4099#define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk
4100
4101/******************* Bit definition for CAN_F13R1 register ******************/
4102#define CAN_F13R1_FB0_Pos (0U)
4103#define CAN_F13R1_FB0_Msk (0x1UL << CAN_F13R1_FB0_Pos)
4104#define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk
4105#define CAN_F13R1_FB1_Pos (1U)
4106#define CAN_F13R1_FB1_Msk (0x1UL << CAN_F13R1_FB1_Pos)
4107#define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk
4108#define CAN_F13R1_FB2_Pos (2U)
4109#define CAN_F13R1_FB2_Msk (0x1UL << CAN_F13R1_FB2_Pos)
4110#define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk
4111#define CAN_F13R1_FB3_Pos (3U)
4112#define CAN_F13R1_FB3_Msk (0x1UL << CAN_F13R1_FB3_Pos)
4113#define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk
4114#define CAN_F13R1_FB4_Pos (4U)
4115#define CAN_F13R1_FB4_Msk (0x1UL << CAN_F13R1_FB4_Pos)
4116#define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk
4117#define CAN_F13R1_FB5_Pos (5U)
4118#define CAN_F13R1_FB5_Msk (0x1UL << CAN_F13R1_FB5_Pos)
4119#define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk
4120#define CAN_F13R1_FB6_Pos (6U)
4121#define CAN_F13R1_FB6_Msk (0x1UL << CAN_F13R1_FB6_Pos)
4122#define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk
4123#define CAN_F13R1_FB7_Pos (7U)
4124#define CAN_F13R1_FB7_Msk (0x1UL << CAN_F13R1_FB7_Pos)
4125#define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk
4126#define CAN_F13R1_FB8_Pos (8U)
4127#define CAN_F13R1_FB8_Msk (0x1UL << CAN_F13R1_FB8_Pos)
4128#define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk
4129#define CAN_F13R1_FB9_Pos (9U)
4130#define CAN_F13R1_FB9_Msk (0x1UL << CAN_F13R1_FB9_Pos)
4131#define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk
4132#define CAN_F13R1_FB10_Pos (10U)
4133#define CAN_F13R1_FB10_Msk (0x1UL << CAN_F13R1_FB10_Pos)
4134#define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk
4135#define CAN_F13R1_FB11_Pos (11U)
4136#define CAN_F13R1_FB11_Msk (0x1UL << CAN_F13R1_FB11_Pos)
4137#define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk
4138#define CAN_F13R1_FB12_Pos (12U)
4139#define CAN_F13R1_FB12_Msk (0x1UL << CAN_F13R1_FB12_Pos)
4140#define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk
4141#define CAN_F13R1_FB13_Pos (13U)
4142#define CAN_F13R1_FB13_Msk (0x1UL << CAN_F13R1_FB13_Pos)
4143#define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk
4144#define CAN_F13R1_FB14_Pos (14U)
4145#define CAN_F13R1_FB14_Msk (0x1UL << CAN_F13R1_FB14_Pos)
4146#define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk
4147#define CAN_F13R1_FB15_Pos (15U)
4148#define CAN_F13R1_FB15_Msk (0x1UL << CAN_F13R1_FB15_Pos)
4149#define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk
4150#define CAN_F13R1_FB16_Pos (16U)
4151#define CAN_F13R1_FB16_Msk (0x1UL << CAN_F13R1_FB16_Pos)
4152#define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk
4153#define CAN_F13R1_FB17_Pos (17U)
4154#define CAN_F13R1_FB17_Msk (0x1UL << CAN_F13R1_FB17_Pos)
4155#define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk
4156#define CAN_F13R1_FB18_Pos (18U)
4157#define CAN_F13R1_FB18_Msk (0x1UL << CAN_F13R1_FB18_Pos)
4158#define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk
4159#define CAN_F13R1_FB19_Pos (19U)
4160#define CAN_F13R1_FB19_Msk (0x1UL << CAN_F13R1_FB19_Pos)
4161#define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk
4162#define CAN_F13R1_FB20_Pos (20U)
4163#define CAN_F13R1_FB20_Msk (0x1UL << CAN_F13R1_FB20_Pos)
4164#define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk
4165#define CAN_F13R1_FB21_Pos (21U)
4166#define CAN_F13R1_FB21_Msk (0x1UL << CAN_F13R1_FB21_Pos)
4167#define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk
4168#define CAN_F13R1_FB22_Pos (22U)
4169#define CAN_F13R1_FB22_Msk (0x1UL << CAN_F13R1_FB22_Pos)
4170#define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk
4171#define CAN_F13R1_FB23_Pos (23U)
4172#define CAN_F13R1_FB23_Msk (0x1UL << CAN_F13R1_FB23_Pos)
4173#define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk
4174#define CAN_F13R1_FB24_Pos (24U)
4175#define CAN_F13R1_FB24_Msk (0x1UL << CAN_F13R1_FB24_Pos)
4176#define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk
4177#define CAN_F13R1_FB25_Pos (25U)
4178#define CAN_F13R1_FB25_Msk (0x1UL << CAN_F13R1_FB25_Pos)
4179#define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk
4180#define CAN_F13R1_FB26_Pos (26U)
4181#define CAN_F13R1_FB26_Msk (0x1UL << CAN_F13R1_FB26_Pos)
4182#define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk
4183#define CAN_F13R1_FB27_Pos (27U)
4184#define CAN_F13R1_FB27_Msk (0x1UL << CAN_F13R1_FB27_Pos)
4185#define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk
4186#define CAN_F13R1_FB28_Pos (28U)
4187#define CAN_F13R1_FB28_Msk (0x1UL << CAN_F13R1_FB28_Pos)
4188#define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk
4189#define CAN_F13R1_FB29_Pos (29U)
4190#define CAN_F13R1_FB29_Msk (0x1UL << CAN_F13R1_FB29_Pos)
4191#define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk
4192#define CAN_F13R1_FB30_Pos (30U)
4193#define CAN_F13R1_FB30_Msk (0x1UL << CAN_F13R1_FB30_Pos)
4194#define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk
4195#define CAN_F13R1_FB31_Pos (31U)
4196#define CAN_F13R1_FB31_Msk (0x1UL << CAN_F13R1_FB31_Pos)
4197#define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk
4198
4199/******************* Bit definition for CAN_F0R2 register *******************/
4200#define CAN_F0R2_FB0_Pos (0U)
4201#define CAN_F0R2_FB0_Msk (0x1UL << CAN_F0R2_FB0_Pos)
4202#define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk
4203#define CAN_F0R2_FB1_Pos (1U)
4204#define CAN_F0R2_FB1_Msk (0x1UL << CAN_F0R2_FB1_Pos)
4205#define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk
4206#define CAN_F0R2_FB2_Pos (2U)
4207#define CAN_F0R2_FB2_Msk (0x1UL << CAN_F0R2_FB2_Pos)
4208#define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk
4209#define CAN_F0R2_FB3_Pos (3U)
4210#define CAN_F0R2_FB3_Msk (0x1UL << CAN_F0R2_FB3_Pos)
4211#define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk
4212#define CAN_F0R2_FB4_Pos (4U)
4213#define CAN_F0R2_FB4_Msk (0x1UL << CAN_F0R2_FB4_Pos)
4214#define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk
4215#define CAN_F0R2_FB5_Pos (5U)
4216#define CAN_F0R2_FB5_Msk (0x1UL << CAN_F0R2_FB5_Pos)
4217#define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk
4218#define CAN_F0R2_FB6_Pos (6U)
4219#define CAN_F0R2_FB6_Msk (0x1UL << CAN_F0R2_FB6_Pos)
4220#define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk
4221#define CAN_F0R2_FB7_Pos (7U)
4222#define CAN_F0R2_FB7_Msk (0x1UL << CAN_F0R2_FB7_Pos)
4223#define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk
4224#define CAN_F0R2_FB8_Pos (8U)
4225#define CAN_F0R2_FB8_Msk (0x1UL << CAN_F0R2_FB8_Pos)
4226#define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk
4227#define CAN_F0R2_FB9_Pos (9U)
4228#define CAN_F0R2_FB9_Msk (0x1UL << CAN_F0R2_FB9_Pos)
4229#define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk
4230#define CAN_F0R2_FB10_Pos (10U)
4231#define CAN_F0R2_FB10_Msk (0x1UL << CAN_F0R2_FB10_Pos)
4232#define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk
4233#define CAN_F0R2_FB11_Pos (11U)
4234#define CAN_F0R2_FB11_Msk (0x1UL << CAN_F0R2_FB11_Pos)
4235#define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk
4236#define CAN_F0R2_FB12_Pos (12U)
4237#define CAN_F0R2_FB12_Msk (0x1UL << CAN_F0R2_FB12_Pos)
4238#define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk
4239#define CAN_F0R2_FB13_Pos (13U)
4240#define CAN_F0R2_FB13_Msk (0x1UL << CAN_F0R2_FB13_Pos)
4241#define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk
4242#define CAN_F0R2_FB14_Pos (14U)
4243#define CAN_F0R2_FB14_Msk (0x1UL << CAN_F0R2_FB14_Pos)
4244#define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk
4245#define CAN_F0R2_FB15_Pos (15U)
4246#define CAN_F0R2_FB15_Msk (0x1UL << CAN_F0R2_FB15_Pos)
4247#define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk
4248#define CAN_F0R2_FB16_Pos (16U)
4249#define CAN_F0R2_FB16_Msk (0x1UL << CAN_F0R2_FB16_Pos)
4250#define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk
4251#define CAN_F0R2_FB17_Pos (17U)
4252#define CAN_F0R2_FB17_Msk (0x1UL << CAN_F0R2_FB17_Pos)
4253#define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk
4254#define CAN_F0R2_FB18_Pos (18U)
4255#define CAN_F0R2_FB18_Msk (0x1UL << CAN_F0R2_FB18_Pos)
4256#define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk
4257#define CAN_F0R2_FB19_Pos (19U)
4258#define CAN_F0R2_FB19_Msk (0x1UL << CAN_F0R2_FB19_Pos)
4259#define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk
4260#define CAN_F0R2_FB20_Pos (20U)
4261#define CAN_F0R2_FB20_Msk (0x1UL << CAN_F0R2_FB20_Pos)
4262#define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk
4263#define CAN_F0R2_FB21_Pos (21U)
4264#define CAN_F0R2_FB21_Msk (0x1UL << CAN_F0R2_FB21_Pos)
4265#define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk
4266#define CAN_F0R2_FB22_Pos (22U)
4267#define CAN_F0R2_FB22_Msk (0x1UL << CAN_F0R2_FB22_Pos)
4268#define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk
4269#define CAN_F0R2_FB23_Pos (23U)
4270#define CAN_F0R2_FB23_Msk (0x1UL << CAN_F0R2_FB23_Pos)
4271#define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk
4272#define CAN_F0R2_FB24_Pos (24U)
4273#define CAN_F0R2_FB24_Msk (0x1UL << CAN_F0R2_FB24_Pos)
4274#define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk
4275#define CAN_F0R2_FB25_Pos (25U)
4276#define CAN_F0R2_FB25_Msk (0x1UL << CAN_F0R2_FB25_Pos)
4277#define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk
4278#define CAN_F0R2_FB26_Pos (26U)
4279#define CAN_F0R2_FB26_Msk (0x1UL << CAN_F0R2_FB26_Pos)
4280#define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk
4281#define CAN_F0R2_FB27_Pos (27U)
4282#define CAN_F0R2_FB27_Msk (0x1UL << CAN_F0R2_FB27_Pos)
4283#define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk
4284#define CAN_F0R2_FB28_Pos (28U)
4285#define CAN_F0R2_FB28_Msk (0x1UL << CAN_F0R2_FB28_Pos)
4286#define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk
4287#define CAN_F0R2_FB29_Pos (29U)
4288#define CAN_F0R2_FB29_Msk (0x1UL << CAN_F0R2_FB29_Pos)
4289#define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk
4290#define CAN_F0R2_FB30_Pos (30U)
4291#define CAN_F0R2_FB30_Msk (0x1UL << CAN_F0R2_FB30_Pos)
4292#define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk
4293#define CAN_F0R2_FB31_Pos (31U)
4294#define CAN_F0R2_FB31_Msk (0x1UL << CAN_F0R2_FB31_Pos)
4295#define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk
4296
4297/******************* Bit definition for CAN_F1R2 register *******************/
4298#define CAN_F1R2_FB0_Pos (0U)
4299#define CAN_F1R2_FB0_Msk (0x1UL << CAN_F1R2_FB0_Pos)
4300#define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk
4301#define CAN_F1R2_FB1_Pos (1U)
4302#define CAN_F1R2_FB1_Msk (0x1UL << CAN_F1R2_FB1_Pos)
4303#define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk
4304#define CAN_F1R2_FB2_Pos (2U)
4305#define CAN_F1R2_FB2_Msk (0x1UL << CAN_F1R2_FB2_Pos)
4306#define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk
4307#define CAN_F1R2_FB3_Pos (3U)
4308#define CAN_F1R2_FB3_Msk (0x1UL << CAN_F1R2_FB3_Pos)
4309#define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk
4310#define CAN_F1R2_FB4_Pos (4U)
4311#define CAN_F1R2_FB4_Msk (0x1UL << CAN_F1R2_FB4_Pos)
4312#define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk
4313#define CAN_F1R2_FB5_Pos (5U)
4314#define CAN_F1R2_FB5_Msk (0x1UL << CAN_F1R2_FB5_Pos)
4315#define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk
4316#define CAN_F1R2_FB6_Pos (6U)
4317#define CAN_F1R2_FB6_Msk (0x1UL << CAN_F1R2_FB6_Pos)
4318#define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk
4319#define CAN_F1R2_FB7_Pos (7U)
4320#define CAN_F1R2_FB7_Msk (0x1UL << CAN_F1R2_FB7_Pos)
4321#define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk
4322#define CAN_F1R2_FB8_Pos (8U)
4323#define CAN_F1R2_FB8_Msk (0x1UL << CAN_F1R2_FB8_Pos)
4324#define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk
4325#define CAN_F1R2_FB9_Pos (9U)
4326#define CAN_F1R2_FB9_Msk (0x1UL << CAN_F1R2_FB9_Pos)
4327#define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk
4328#define CAN_F1R2_FB10_Pos (10U)
4329#define CAN_F1R2_FB10_Msk (0x1UL << CAN_F1R2_FB10_Pos)
4330#define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk
4331#define CAN_F1R2_FB11_Pos (11U)
4332#define CAN_F1R2_FB11_Msk (0x1UL << CAN_F1R2_FB11_Pos)
4333#define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk
4334#define CAN_F1R2_FB12_Pos (12U)
4335#define CAN_F1R2_FB12_Msk (0x1UL << CAN_F1R2_FB12_Pos)
4336#define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk
4337#define CAN_F1R2_FB13_Pos (13U)
4338#define CAN_F1R2_FB13_Msk (0x1UL << CAN_F1R2_FB13_Pos)
4339#define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk
4340#define CAN_F1R2_FB14_Pos (14U)
4341#define CAN_F1R2_FB14_Msk (0x1UL << CAN_F1R2_FB14_Pos)
4342#define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk
4343#define CAN_F1R2_FB15_Pos (15U)
4344#define CAN_F1R2_FB15_Msk (0x1UL << CAN_F1R2_FB15_Pos)
4345#define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk
4346#define CAN_F1R2_FB16_Pos (16U)
4347#define CAN_F1R2_FB16_Msk (0x1UL << CAN_F1R2_FB16_Pos)
4348#define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk
4349#define CAN_F1R2_FB17_Pos (17U)
4350#define CAN_F1R2_FB17_Msk (0x1UL << CAN_F1R2_FB17_Pos)
4351#define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk
4352#define CAN_F1R2_FB18_Pos (18U)
4353#define CAN_F1R2_FB18_Msk (0x1UL << CAN_F1R2_FB18_Pos)
4354#define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk
4355#define CAN_F1R2_FB19_Pos (19U)
4356#define CAN_F1R2_FB19_Msk (0x1UL << CAN_F1R2_FB19_Pos)
4357#define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk
4358#define CAN_F1R2_FB20_Pos (20U)
4359#define CAN_F1R2_FB20_Msk (0x1UL << CAN_F1R2_FB20_Pos)
4360#define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk
4361#define CAN_F1R2_FB21_Pos (21U)
4362#define CAN_F1R2_FB21_Msk (0x1UL << CAN_F1R2_FB21_Pos)
4363#define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk
4364#define CAN_F1R2_FB22_Pos (22U)
4365#define CAN_F1R2_FB22_Msk (0x1UL << CAN_F1R2_FB22_Pos)
4366#define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk
4367#define CAN_F1R2_FB23_Pos (23U)
4368#define CAN_F1R2_FB23_Msk (0x1UL << CAN_F1R2_FB23_Pos)
4369#define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk
4370#define CAN_F1R2_FB24_Pos (24U)
4371#define CAN_F1R2_FB24_Msk (0x1UL << CAN_F1R2_FB24_Pos)
4372#define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk
4373#define CAN_F1R2_FB25_Pos (25U)
4374#define CAN_F1R2_FB25_Msk (0x1UL << CAN_F1R2_FB25_Pos)
4375#define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk
4376#define CAN_F1R2_FB26_Pos (26U)
4377#define CAN_F1R2_FB26_Msk (0x1UL << CAN_F1R2_FB26_Pos)
4378#define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk
4379#define CAN_F1R2_FB27_Pos (27U)
4380#define CAN_F1R2_FB27_Msk (0x1UL << CAN_F1R2_FB27_Pos)
4381#define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk
4382#define CAN_F1R2_FB28_Pos (28U)
4383#define CAN_F1R2_FB28_Msk (0x1UL << CAN_F1R2_FB28_Pos)
4384#define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk
4385#define CAN_F1R2_FB29_Pos (29U)
4386#define CAN_F1R2_FB29_Msk (0x1UL << CAN_F1R2_FB29_Pos)
4387#define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk
4388#define CAN_F1R2_FB30_Pos (30U)
4389#define CAN_F1R2_FB30_Msk (0x1UL << CAN_F1R2_FB30_Pos)
4390#define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk
4391#define CAN_F1R2_FB31_Pos (31U)
4392#define CAN_F1R2_FB31_Msk (0x1UL << CAN_F1R2_FB31_Pos)
4393#define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk
4394
4395/******************* Bit definition for CAN_F2R2 register *******************/
4396#define CAN_F2R2_FB0_Pos (0U)
4397#define CAN_F2R2_FB0_Msk (0x1UL << CAN_F2R2_FB0_Pos)
4398#define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk
4399#define CAN_F2R2_FB1_Pos (1U)
4400#define CAN_F2R2_FB1_Msk (0x1UL << CAN_F2R2_FB1_Pos)
4401#define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk
4402#define CAN_F2R2_FB2_Pos (2U)
4403#define CAN_F2R2_FB2_Msk (0x1UL << CAN_F2R2_FB2_Pos)
4404#define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk
4405#define CAN_F2R2_FB3_Pos (3U)
4406#define CAN_F2R2_FB3_Msk (0x1UL << CAN_F2R2_FB3_Pos)
4407#define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk
4408#define CAN_F2R2_FB4_Pos (4U)
4409#define CAN_F2R2_FB4_Msk (0x1UL << CAN_F2R2_FB4_Pos)
4410#define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk
4411#define CAN_F2R2_FB5_Pos (5U)
4412#define CAN_F2R2_FB5_Msk (0x1UL << CAN_F2R2_FB5_Pos)
4413#define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk
4414#define CAN_F2R2_FB6_Pos (6U)
4415#define CAN_F2R2_FB6_Msk (0x1UL << CAN_F2R2_FB6_Pos)
4416#define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk
4417#define CAN_F2R2_FB7_Pos (7U)
4418#define CAN_F2R2_FB7_Msk (0x1UL << CAN_F2R2_FB7_Pos)
4419#define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk
4420#define CAN_F2R2_FB8_Pos (8U)
4421#define CAN_F2R2_FB8_Msk (0x1UL << CAN_F2R2_FB8_Pos)
4422#define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk
4423#define CAN_F2R2_FB9_Pos (9U)
4424#define CAN_F2R2_FB9_Msk (0x1UL << CAN_F2R2_FB9_Pos)
4425#define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk
4426#define CAN_F2R2_FB10_Pos (10U)
4427#define CAN_F2R2_FB10_Msk (0x1UL << CAN_F2R2_FB10_Pos)
4428#define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk
4429#define CAN_F2R2_FB11_Pos (11U)
4430#define CAN_F2R2_FB11_Msk (0x1UL << CAN_F2R2_FB11_Pos)
4431#define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk
4432#define CAN_F2R2_FB12_Pos (12U)
4433#define CAN_F2R2_FB12_Msk (0x1UL << CAN_F2R2_FB12_Pos)
4434#define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk
4435#define CAN_F2R2_FB13_Pos (13U)
4436#define CAN_F2R2_FB13_Msk (0x1UL << CAN_F2R2_FB13_Pos)
4437#define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk
4438#define CAN_F2R2_FB14_Pos (14U)
4439#define CAN_F2R2_FB14_Msk (0x1UL << CAN_F2R2_FB14_Pos)
4440#define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk
4441#define CAN_F2R2_FB15_Pos (15U)
4442#define CAN_F2R2_FB15_Msk (0x1UL << CAN_F2R2_FB15_Pos)
4443#define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk
4444#define CAN_F2R2_FB16_Pos (16U)
4445#define CAN_F2R2_FB16_Msk (0x1UL << CAN_F2R2_FB16_Pos)
4446#define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk
4447#define CAN_F2R2_FB17_Pos (17U)
4448#define CAN_F2R2_FB17_Msk (0x1UL << CAN_F2R2_FB17_Pos)
4449#define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk
4450#define CAN_F2R2_FB18_Pos (18U)
4451#define CAN_F2R2_FB18_Msk (0x1UL << CAN_F2R2_FB18_Pos)
4452#define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk
4453#define CAN_F2R2_FB19_Pos (19U)
4454#define CAN_F2R2_FB19_Msk (0x1UL << CAN_F2R2_FB19_Pos)
4455#define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk
4456#define CAN_F2R2_FB20_Pos (20U)
4457#define CAN_F2R2_FB20_Msk (0x1UL << CAN_F2R2_FB20_Pos)
4458#define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk
4459#define CAN_F2R2_FB21_Pos (21U)
4460#define CAN_F2R2_FB21_Msk (0x1UL << CAN_F2R2_FB21_Pos)
4461#define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk
4462#define CAN_F2R2_FB22_Pos (22U)
4463#define CAN_F2R2_FB22_Msk (0x1UL << CAN_F2R2_FB22_Pos)
4464#define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk
4465#define CAN_F2R2_FB23_Pos (23U)
4466#define CAN_F2R2_FB23_Msk (0x1UL << CAN_F2R2_FB23_Pos)
4467#define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk
4468#define CAN_F2R2_FB24_Pos (24U)
4469#define CAN_F2R2_FB24_Msk (0x1UL << CAN_F2R2_FB24_Pos)
4470#define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk
4471#define CAN_F2R2_FB25_Pos (25U)
4472#define CAN_F2R2_FB25_Msk (0x1UL << CAN_F2R2_FB25_Pos)
4473#define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk
4474#define CAN_F2R2_FB26_Pos (26U)
4475#define CAN_F2R2_FB26_Msk (0x1UL << CAN_F2R2_FB26_Pos)
4476#define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk
4477#define CAN_F2R2_FB27_Pos (27U)
4478#define CAN_F2R2_FB27_Msk (0x1UL << CAN_F2R2_FB27_Pos)
4479#define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk
4480#define CAN_F2R2_FB28_Pos (28U)
4481#define CAN_F2R2_FB28_Msk (0x1UL << CAN_F2R2_FB28_Pos)
4482#define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk
4483#define CAN_F2R2_FB29_Pos (29U)
4484#define CAN_F2R2_FB29_Msk (0x1UL << CAN_F2R2_FB29_Pos)
4485#define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk
4486#define CAN_F2R2_FB30_Pos (30U)
4487#define CAN_F2R2_FB30_Msk (0x1UL << CAN_F2R2_FB30_Pos)
4488#define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk
4489#define CAN_F2R2_FB31_Pos (31U)
4490#define CAN_F2R2_FB31_Msk (0x1UL << CAN_F2R2_FB31_Pos)
4491#define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk
4492
4493/******************* Bit definition for CAN_F3R2 register *******************/
4494#define CAN_F3R2_FB0_Pos (0U)
4495#define CAN_F3R2_FB0_Msk (0x1UL << CAN_F3R2_FB0_Pos)
4496#define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk
4497#define CAN_F3R2_FB1_Pos (1U)
4498#define CAN_F3R2_FB1_Msk (0x1UL << CAN_F3R2_FB1_Pos)
4499#define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk
4500#define CAN_F3R2_FB2_Pos (2U)
4501#define CAN_F3R2_FB2_Msk (0x1UL << CAN_F3R2_FB2_Pos)
4502#define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk
4503#define CAN_F3R2_FB3_Pos (3U)
4504#define CAN_F3R2_FB3_Msk (0x1UL << CAN_F3R2_FB3_Pos)
4505#define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk
4506#define CAN_F3R2_FB4_Pos (4U)
4507#define CAN_F3R2_FB4_Msk (0x1UL << CAN_F3R2_FB4_Pos)
4508#define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk
4509#define CAN_F3R2_FB5_Pos (5U)
4510#define CAN_F3R2_FB5_Msk (0x1UL << CAN_F3R2_FB5_Pos)
4511#define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk
4512#define CAN_F3R2_FB6_Pos (6U)
4513#define CAN_F3R2_FB6_Msk (0x1UL << CAN_F3R2_FB6_Pos)
4514#define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk
4515#define CAN_F3R2_FB7_Pos (7U)
4516#define CAN_F3R2_FB7_Msk (0x1UL << CAN_F3R2_FB7_Pos)
4517#define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk
4518#define CAN_F3R2_FB8_Pos (8U)
4519#define CAN_F3R2_FB8_Msk (0x1UL << CAN_F3R2_FB8_Pos)
4520#define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk
4521#define CAN_F3R2_FB9_Pos (9U)
4522#define CAN_F3R2_FB9_Msk (0x1UL << CAN_F3R2_FB9_Pos)
4523#define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk
4524#define CAN_F3R2_FB10_Pos (10U)
4525#define CAN_F3R2_FB10_Msk (0x1UL << CAN_F3R2_FB10_Pos)
4526#define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk
4527#define CAN_F3R2_FB11_Pos (11U)
4528#define CAN_F3R2_FB11_Msk (0x1UL << CAN_F3R2_FB11_Pos)
4529#define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk
4530#define CAN_F3R2_FB12_Pos (12U)
4531#define CAN_F3R2_FB12_Msk (0x1UL << CAN_F3R2_FB12_Pos)
4532#define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk
4533#define CAN_F3R2_FB13_Pos (13U)
4534#define CAN_F3R2_FB13_Msk (0x1UL << CAN_F3R2_FB13_Pos)
4535#define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk
4536#define CAN_F3R2_FB14_Pos (14U)
4537#define CAN_F3R2_FB14_Msk (0x1UL << CAN_F3R2_FB14_Pos)
4538#define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk
4539#define CAN_F3R2_FB15_Pos (15U)
4540#define CAN_F3R2_FB15_Msk (0x1UL << CAN_F3R2_FB15_Pos)
4541#define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk
4542#define CAN_F3R2_FB16_Pos (16U)
4543#define CAN_F3R2_FB16_Msk (0x1UL << CAN_F3R2_FB16_Pos)
4544#define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk
4545#define CAN_F3R2_FB17_Pos (17U)
4546#define CAN_F3R2_FB17_Msk (0x1UL << CAN_F3R2_FB17_Pos)
4547#define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk
4548#define CAN_F3R2_FB18_Pos (18U)
4549#define CAN_F3R2_FB18_Msk (0x1UL << CAN_F3R2_FB18_Pos)
4550#define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk
4551#define CAN_F3R2_FB19_Pos (19U)
4552#define CAN_F3R2_FB19_Msk (0x1UL << CAN_F3R2_FB19_Pos)
4553#define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk
4554#define CAN_F3R2_FB20_Pos (20U)
4555#define CAN_F3R2_FB20_Msk (0x1UL << CAN_F3R2_FB20_Pos)
4556#define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk
4557#define CAN_F3R2_FB21_Pos (21U)
4558#define CAN_F3R2_FB21_Msk (0x1UL << CAN_F3R2_FB21_Pos)
4559#define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk
4560#define CAN_F3R2_FB22_Pos (22U)
4561#define CAN_F3R2_FB22_Msk (0x1UL << CAN_F3R2_FB22_Pos)
4562#define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk
4563#define CAN_F3R2_FB23_Pos (23U)
4564#define CAN_F3R2_FB23_Msk (0x1UL << CAN_F3R2_FB23_Pos)
4565#define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk
4566#define CAN_F3R2_FB24_Pos (24U)
4567#define CAN_F3R2_FB24_Msk (0x1UL << CAN_F3R2_FB24_Pos)
4568#define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk
4569#define CAN_F3R2_FB25_Pos (25U)
4570#define CAN_F3R2_FB25_Msk (0x1UL << CAN_F3R2_FB25_Pos)
4571#define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk
4572#define CAN_F3R2_FB26_Pos (26U)
4573#define CAN_F3R2_FB26_Msk (0x1UL << CAN_F3R2_FB26_Pos)
4574#define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk
4575#define CAN_F3R2_FB27_Pos (27U)
4576#define CAN_F3R2_FB27_Msk (0x1UL << CAN_F3R2_FB27_Pos)
4577#define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk
4578#define CAN_F3R2_FB28_Pos (28U)
4579#define CAN_F3R2_FB28_Msk (0x1UL << CAN_F3R2_FB28_Pos)
4580#define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk
4581#define CAN_F3R2_FB29_Pos (29U)
4582#define CAN_F3R2_FB29_Msk (0x1UL << CAN_F3R2_FB29_Pos)
4583#define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk
4584#define CAN_F3R2_FB30_Pos (30U)
4585#define CAN_F3R2_FB30_Msk (0x1UL << CAN_F3R2_FB30_Pos)
4586#define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk
4587#define CAN_F3R2_FB31_Pos (31U)
4588#define CAN_F3R2_FB31_Msk (0x1UL << CAN_F3R2_FB31_Pos)
4589#define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk
4590
4591/******************* Bit definition for CAN_F4R2 register *******************/
4592#define CAN_F4R2_FB0_Pos (0U)
4593#define CAN_F4R2_FB0_Msk (0x1UL << CAN_F4R2_FB0_Pos)
4594#define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk
4595#define CAN_F4R2_FB1_Pos (1U)
4596#define CAN_F4R2_FB1_Msk (0x1UL << CAN_F4R2_FB1_Pos)
4597#define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk
4598#define CAN_F4R2_FB2_Pos (2U)
4599#define CAN_F4R2_FB2_Msk (0x1UL << CAN_F4R2_FB2_Pos)
4600#define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk
4601#define CAN_F4R2_FB3_Pos (3U)
4602#define CAN_F4R2_FB3_Msk (0x1UL << CAN_F4R2_FB3_Pos)
4603#define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk
4604#define CAN_F4R2_FB4_Pos (4U)
4605#define CAN_F4R2_FB4_Msk (0x1UL << CAN_F4R2_FB4_Pos)
4606#define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk
4607#define CAN_F4R2_FB5_Pos (5U)
4608#define CAN_F4R2_FB5_Msk (0x1UL << CAN_F4R2_FB5_Pos)
4609#define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk
4610#define CAN_F4R2_FB6_Pos (6U)
4611#define CAN_F4R2_FB6_Msk (0x1UL << CAN_F4R2_FB6_Pos)
4612#define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk
4613#define CAN_F4R2_FB7_Pos (7U)
4614#define CAN_F4R2_FB7_Msk (0x1UL << CAN_F4R2_FB7_Pos)
4615#define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk
4616#define CAN_F4R2_FB8_Pos (8U)
4617#define CAN_F4R2_FB8_Msk (0x1UL << CAN_F4R2_FB8_Pos)
4618#define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk
4619#define CAN_F4R2_FB9_Pos (9U)
4620#define CAN_F4R2_FB9_Msk (0x1UL << CAN_F4R2_FB9_Pos)
4621#define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk
4622#define CAN_F4R2_FB10_Pos (10U)
4623#define CAN_F4R2_FB10_Msk (0x1UL << CAN_F4R2_FB10_Pos)
4624#define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk
4625#define CAN_F4R2_FB11_Pos (11U)
4626#define CAN_F4R2_FB11_Msk (0x1UL << CAN_F4R2_FB11_Pos)
4627#define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk
4628#define CAN_F4R2_FB12_Pos (12U)
4629#define CAN_F4R2_FB12_Msk (0x1UL << CAN_F4R2_FB12_Pos)
4630#define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk
4631#define CAN_F4R2_FB13_Pos (13U)
4632#define CAN_F4R2_FB13_Msk (0x1UL << CAN_F4R2_FB13_Pos)
4633#define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk
4634#define CAN_F4R2_FB14_Pos (14U)
4635#define CAN_F4R2_FB14_Msk (0x1UL << CAN_F4R2_FB14_Pos)
4636#define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk
4637#define CAN_F4R2_FB15_Pos (15U)
4638#define CAN_F4R2_FB15_Msk (0x1UL << CAN_F4R2_FB15_Pos)
4639#define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk
4640#define CAN_F4R2_FB16_Pos (16U)
4641#define CAN_F4R2_FB16_Msk (0x1UL << CAN_F4R2_FB16_Pos)
4642#define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk
4643#define CAN_F4R2_FB17_Pos (17U)
4644#define CAN_F4R2_FB17_Msk (0x1UL << CAN_F4R2_FB17_Pos)
4645#define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk
4646#define CAN_F4R2_FB18_Pos (18U)
4647#define CAN_F4R2_FB18_Msk (0x1UL << CAN_F4R2_FB18_Pos)
4648#define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk
4649#define CAN_F4R2_FB19_Pos (19U)
4650#define CAN_F4R2_FB19_Msk (0x1UL << CAN_F4R2_FB19_Pos)
4651#define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk
4652#define CAN_F4R2_FB20_Pos (20U)
4653#define CAN_F4R2_FB20_Msk (0x1UL << CAN_F4R2_FB20_Pos)
4654#define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk
4655#define CAN_F4R2_FB21_Pos (21U)
4656#define CAN_F4R2_FB21_Msk (0x1UL << CAN_F4R2_FB21_Pos)
4657#define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk
4658#define CAN_F4R2_FB22_Pos (22U)
4659#define CAN_F4R2_FB22_Msk (0x1UL << CAN_F4R2_FB22_Pos)
4660#define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk
4661#define CAN_F4R2_FB23_Pos (23U)
4662#define CAN_F4R2_FB23_Msk (0x1UL << CAN_F4R2_FB23_Pos)
4663#define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk
4664#define CAN_F4R2_FB24_Pos (24U)
4665#define CAN_F4R2_FB24_Msk (0x1UL << CAN_F4R2_FB24_Pos)
4666#define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk
4667#define CAN_F4R2_FB25_Pos (25U)
4668#define CAN_F4R2_FB25_Msk (0x1UL << CAN_F4R2_FB25_Pos)
4669#define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk
4670#define CAN_F4R2_FB26_Pos (26U)
4671#define CAN_F4R2_FB26_Msk (0x1UL << CAN_F4R2_FB26_Pos)
4672#define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk
4673#define CAN_F4R2_FB27_Pos (27U)
4674#define CAN_F4R2_FB27_Msk (0x1UL << CAN_F4R2_FB27_Pos)
4675#define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk
4676#define CAN_F4R2_FB28_Pos (28U)
4677#define CAN_F4R2_FB28_Msk (0x1UL << CAN_F4R2_FB28_Pos)
4678#define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk
4679#define CAN_F4R2_FB29_Pos (29U)
4680#define CAN_F4R2_FB29_Msk (0x1UL << CAN_F4R2_FB29_Pos)
4681#define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk
4682#define CAN_F4R2_FB30_Pos (30U)
4683#define CAN_F4R2_FB30_Msk (0x1UL << CAN_F4R2_FB30_Pos)
4684#define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk
4685#define CAN_F4R2_FB31_Pos (31U)
4686#define CAN_F4R2_FB31_Msk (0x1UL << CAN_F4R2_FB31_Pos)
4687#define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk
4688
4689/******************* Bit definition for CAN_F5R2 register *******************/
4690#define CAN_F5R2_FB0_Pos (0U)
4691#define CAN_F5R2_FB0_Msk (0x1UL << CAN_F5R2_FB0_Pos)
4692#define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk
4693#define CAN_F5R2_FB1_Pos (1U)
4694#define CAN_F5R2_FB1_Msk (0x1UL << CAN_F5R2_FB1_Pos)
4695#define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk
4696#define CAN_F5R2_FB2_Pos (2U)
4697#define CAN_F5R2_FB2_Msk (0x1UL << CAN_F5R2_FB2_Pos)
4698#define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk
4699#define CAN_F5R2_FB3_Pos (3U)
4700#define CAN_F5R2_FB3_Msk (0x1UL << CAN_F5R2_FB3_Pos)
4701#define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk
4702#define CAN_F5R2_FB4_Pos (4U)
4703#define CAN_F5R2_FB4_Msk (0x1UL << CAN_F5R2_FB4_Pos)
4704#define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk
4705#define CAN_F5R2_FB5_Pos (5U)
4706#define CAN_F5R2_FB5_Msk (0x1UL << CAN_F5R2_FB5_Pos)
4707#define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk
4708#define CAN_F5R2_FB6_Pos (6U)
4709#define CAN_F5R2_FB6_Msk (0x1UL << CAN_F5R2_FB6_Pos)
4710#define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk
4711#define CAN_F5R2_FB7_Pos (7U)
4712#define CAN_F5R2_FB7_Msk (0x1UL << CAN_F5R2_FB7_Pos)
4713#define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk
4714#define CAN_F5R2_FB8_Pos (8U)
4715#define CAN_F5R2_FB8_Msk (0x1UL << CAN_F5R2_FB8_Pos)
4716#define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk
4717#define CAN_F5R2_FB9_Pos (9U)
4718#define CAN_F5R2_FB9_Msk (0x1UL << CAN_F5R2_FB9_Pos)
4719#define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk
4720#define CAN_F5R2_FB10_Pos (10U)
4721#define CAN_F5R2_FB10_Msk (0x1UL << CAN_F5R2_FB10_Pos)
4722#define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk
4723#define CAN_F5R2_FB11_Pos (11U)
4724#define CAN_F5R2_FB11_Msk (0x1UL << CAN_F5R2_FB11_Pos)
4725#define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk
4726#define CAN_F5R2_FB12_Pos (12U)
4727#define CAN_F5R2_FB12_Msk (0x1UL << CAN_F5R2_FB12_Pos)
4728#define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk
4729#define CAN_F5R2_FB13_Pos (13U)
4730#define CAN_F5R2_FB13_Msk (0x1UL << CAN_F5R2_FB13_Pos)
4731#define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk
4732#define CAN_F5R2_FB14_Pos (14U)
4733#define CAN_F5R2_FB14_Msk (0x1UL << CAN_F5R2_FB14_Pos)
4734#define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk
4735#define CAN_F5R2_FB15_Pos (15U)
4736#define CAN_F5R2_FB15_Msk (0x1UL << CAN_F5R2_FB15_Pos)
4737#define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk
4738#define CAN_F5R2_FB16_Pos (16U)
4739#define CAN_F5R2_FB16_Msk (0x1UL << CAN_F5R2_FB16_Pos)
4740#define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk
4741#define CAN_F5R2_FB17_Pos (17U)
4742#define CAN_F5R2_FB17_Msk (0x1UL << CAN_F5R2_FB17_Pos)
4743#define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk
4744#define CAN_F5R2_FB18_Pos (18U)
4745#define CAN_F5R2_FB18_Msk (0x1UL << CAN_F5R2_FB18_Pos)
4746#define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk
4747#define CAN_F5R2_FB19_Pos (19U)
4748#define CAN_F5R2_FB19_Msk (0x1UL << CAN_F5R2_FB19_Pos)
4749#define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk
4750#define CAN_F5R2_FB20_Pos (20U)
4751#define CAN_F5R2_FB20_Msk (0x1UL << CAN_F5R2_FB20_Pos)
4752#define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk
4753#define CAN_F5R2_FB21_Pos (21U)
4754#define CAN_F5R2_FB21_Msk (0x1UL << CAN_F5R2_FB21_Pos)
4755#define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk
4756#define CAN_F5R2_FB22_Pos (22U)
4757#define CAN_F5R2_FB22_Msk (0x1UL << CAN_F5R2_FB22_Pos)
4758#define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk
4759#define CAN_F5R2_FB23_Pos (23U)
4760#define CAN_F5R2_FB23_Msk (0x1UL << CAN_F5R2_FB23_Pos)
4761#define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk
4762#define CAN_F5R2_FB24_Pos (24U)
4763#define CAN_F5R2_FB24_Msk (0x1UL << CAN_F5R2_FB24_Pos)
4764#define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk
4765#define CAN_F5R2_FB25_Pos (25U)
4766#define CAN_F5R2_FB25_Msk (0x1UL << CAN_F5R2_FB25_Pos)
4767#define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk
4768#define CAN_F5R2_FB26_Pos (26U)
4769#define CAN_F5R2_FB26_Msk (0x1UL << CAN_F5R2_FB26_Pos)
4770#define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk
4771#define CAN_F5R2_FB27_Pos (27U)
4772#define CAN_F5R2_FB27_Msk (0x1UL << CAN_F5R2_FB27_Pos)
4773#define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk
4774#define CAN_F5R2_FB28_Pos (28U)
4775#define CAN_F5R2_FB28_Msk (0x1UL << CAN_F5R2_FB28_Pos)
4776#define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk
4777#define CAN_F5R2_FB29_Pos (29U)
4778#define CAN_F5R2_FB29_Msk (0x1UL << CAN_F5R2_FB29_Pos)
4779#define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk
4780#define CAN_F5R2_FB30_Pos (30U)
4781#define CAN_F5R2_FB30_Msk (0x1UL << CAN_F5R2_FB30_Pos)
4782#define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk
4783#define CAN_F5R2_FB31_Pos (31U)
4784#define CAN_F5R2_FB31_Msk (0x1UL << CAN_F5R2_FB31_Pos)
4785#define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk
4786
4787/******************* Bit definition for CAN_F6R2 register *******************/
4788#define CAN_F6R2_FB0_Pos (0U)
4789#define CAN_F6R2_FB0_Msk (0x1UL << CAN_F6R2_FB0_Pos)
4790#define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk
4791#define CAN_F6R2_FB1_Pos (1U)
4792#define CAN_F6R2_FB1_Msk (0x1UL << CAN_F6R2_FB1_Pos)
4793#define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk
4794#define CAN_F6R2_FB2_Pos (2U)
4795#define CAN_F6R2_FB2_Msk (0x1UL << CAN_F6R2_FB2_Pos)
4796#define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk
4797#define CAN_F6R2_FB3_Pos (3U)
4798#define CAN_F6R2_FB3_Msk (0x1UL << CAN_F6R2_FB3_Pos)
4799#define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk
4800#define CAN_F6R2_FB4_Pos (4U)
4801#define CAN_F6R2_FB4_Msk (0x1UL << CAN_F6R2_FB4_Pos)
4802#define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk
4803#define CAN_F6R2_FB5_Pos (5U)
4804#define CAN_F6R2_FB5_Msk (0x1UL << CAN_F6R2_FB5_Pos)
4805#define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk
4806#define CAN_F6R2_FB6_Pos (6U)
4807#define CAN_F6R2_FB6_Msk (0x1UL << CAN_F6R2_FB6_Pos)
4808#define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk
4809#define CAN_F6R2_FB7_Pos (7U)
4810#define CAN_F6R2_FB7_Msk (0x1UL << CAN_F6R2_FB7_Pos)
4811#define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk
4812#define CAN_F6R2_FB8_Pos (8U)
4813#define CAN_F6R2_FB8_Msk (0x1UL << CAN_F6R2_FB8_Pos)
4814#define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk
4815#define CAN_F6R2_FB9_Pos (9U)
4816#define CAN_F6R2_FB9_Msk (0x1UL << CAN_F6R2_FB9_Pos)
4817#define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk
4818#define CAN_F6R2_FB10_Pos (10U)
4819#define CAN_F6R2_FB10_Msk (0x1UL << CAN_F6R2_FB10_Pos)
4820#define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk
4821#define CAN_F6R2_FB11_Pos (11U)
4822#define CAN_F6R2_FB11_Msk (0x1UL << CAN_F6R2_FB11_Pos)
4823#define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk
4824#define CAN_F6R2_FB12_Pos (12U)
4825#define CAN_F6R2_FB12_Msk (0x1UL << CAN_F6R2_FB12_Pos)
4826#define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk
4827#define CAN_F6R2_FB13_Pos (13U)
4828#define CAN_F6R2_FB13_Msk (0x1UL << CAN_F6R2_FB13_Pos)
4829#define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk
4830#define CAN_F6R2_FB14_Pos (14U)
4831#define CAN_F6R2_FB14_Msk (0x1UL << CAN_F6R2_FB14_Pos)
4832#define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk
4833#define CAN_F6R2_FB15_Pos (15U)
4834#define CAN_F6R2_FB15_Msk (0x1UL << CAN_F6R2_FB15_Pos)
4835#define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk
4836#define CAN_F6R2_FB16_Pos (16U)
4837#define CAN_F6R2_FB16_Msk (0x1UL << CAN_F6R2_FB16_Pos)
4838#define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk
4839#define CAN_F6R2_FB17_Pos (17U)
4840#define CAN_F6R2_FB17_Msk (0x1UL << CAN_F6R2_FB17_Pos)
4841#define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk
4842#define CAN_F6R2_FB18_Pos (18U)
4843#define CAN_F6R2_FB18_Msk (0x1UL << CAN_F6R2_FB18_Pos)
4844#define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk
4845#define CAN_F6R2_FB19_Pos (19U)
4846#define CAN_F6R2_FB19_Msk (0x1UL << CAN_F6R2_FB19_Pos)
4847#define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk
4848#define CAN_F6R2_FB20_Pos (20U)
4849#define CAN_F6R2_FB20_Msk (0x1UL << CAN_F6R2_FB20_Pos)
4850#define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk
4851#define CAN_F6R2_FB21_Pos (21U)
4852#define CAN_F6R2_FB21_Msk (0x1UL << CAN_F6R2_FB21_Pos)
4853#define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk
4854#define CAN_F6R2_FB22_Pos (22U)
4855#define CAN_F6R2_FB22_Msk (0x1UL << CAN_F6R2_FB22_Pos)
4856#define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk
4857#define CAN_F6R2_FB23_Pos (23U)
4858#define CAN_F6R2_FB23_Msk (0x1UL << CAN_F6R2_FB23_Pos)
4859#define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk
4860#define CAN_F6R2_FB24_Pos (24U)
4861#define CAN_F6R2_FB24_Msk (0x1UL << CAN_F6R2_FB24_Pos)
4862#define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk
4863#define CAN_F6R2_FB25_Pos (25U)
4864#define CAN_F6R2_FB25_Msk (0x1UL << CAN_F6R2_FB25_Pos)
4865#define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk
4866#define CAN_F6R2_FB26_Pos (26U)
4867#define CAN_F6R2_FB26_Msk (0x1UL << CAN_F6R2_FB26_Pos)
4868#define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk
4869#define CAN_F6R2_FB27_Pos (27U)
4870#define CAN_F6R2_FB27_Msk (0x1UL << CAN_F6R2_FB27_Pos)
4871#define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk
4872#define CAN_F6R2_FB28_Pos (28U)
4873#define CAN_F6R2_FB28_Msk (0x1UL << CAN_F6R2_FB28_Pos)
4874#define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk
4875#define CAN_F6R2_FB29_Pos (29U)
4876#define CAN_F6R2_FB29_Msk (0x1UL << CAN_F6R2_FB29_Pos)
4877#define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk
4878#define CAN_F6R2_FB30_Pos (30U)
4879#define CAN_F6R2_FB30_Msk (0x1UL << CAN_F6R2_FB30_Pos)
4880#define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk
4881#define CAN_F6R2_FB31_Pos (31U)
4882#define CAN_F6R2_FB31_Msk (0x1UL << CAN_F6R2_FB31_Pos)
4883#define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk
4884
4885/******************* Bit definition for CAN_F7R2 register *******************/
4886#define CAN_F7R2_FB0_Pos (0U)
4887#define CAN_F7R2_FB0_Msk (0x1UL << CAN_F7R2_FB0_Pos)
4888#define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk
4889#define CAN_F7R2_FB1_Pos (1U)
4890#define CAN_F7R2_FB1_Msk (0x1UL << CAN_F7R2_FB1_Pos)
4891#define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk
4892#define CAN_F7R2_FB2_Pos (2U)
4893#define CAN_F7R2_FB2_Msk (0x1UL << CAN_F7R2_FB2_Pos)
4894#define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk
4895#define CAN_F7R2_FB3_Pos (3U)
4896#define CAN_F7R2_FB3_Msk (0x1UL << CAN_F7R2_FB3_Pos)
4897#define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk
4898#define CAN_F7R2_FB4_Pos (4U)
4899#define CAN_F7R2_FB4_Msk (0x1UL << CAN_F7R2_FB4_Pos)
4900#define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk
4901#define CAN_F7R2_FB5_Pos (5U)
4902#define CAN_F7R2_FB5_Msk (0x1UL << CAN_F7R2_FB5_Pos)
4903#define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk
4904#define CAN_F7R2_FB6_Pos (6U)
4905#define CAN_F7R2_FB6_Msk (0x1UL << CAN_F7R2_FB6_Pos)
4906#define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk
4907#define CAN_F7R2_FB7_Pos (7U)
4908#define CAN_F7R2_FB7_Msk (0x1UL << CAN_F7R2_FB7_Pos)
4909#define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk
4910#define CAN_F7R2_FB8_Pos (8U)
4911#define CAN_F7R2_FB8_Msk (0x1UL << CAN_F7R2_FB8_Pos)
4912#define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk
4913#define CAN_F7R2_FB9_Pos (9U)
4914#define CAN_F7R2_FB9_Msk (0x1UL << CAN_F7R2_FB9_Pos)
4915#define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk
4916#define CAN_F7R2_FB10_Pos (10U)
4917#define CAN_F7R2_FB10_Msk (0x1UL << CAN_F7R2_FB10_Pos)
4918#define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk
4919#define CAN_F7R2_FB11_Pos (11U)
4920#define CAN_F7R2_FB11_Msk (0x1UL << CAN_F7R2_FB11_Pos)
4921#define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk
4922#define CAN_F7R2_FB12_Pos (12U)
4923#define CAN_F7R2_FB12_Msk (0x1UL << CAN_F7R2_FB12_Pos)
4924#define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk
4925#define CAN_F7R2_FB13_Pos (13U)
4926#define CAN_F7R2_FB13_Msk (0x1UL << CAN_F7R2_FB13_Pos)
4927#define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk
4928#define CAN_F7R2_FB14_Pos (14U)
4929#define CAN_F7R2_FB14_Msk (0x1UL << CAN_F7R2_FB14_Pos)
4930#define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk
4931#define CAN_F7R2_FB15_Pos (15U)
4932#define CAN_F7R2_FB15_Msk (0x1UL << CAN_F7R2_FB15_Pos)
4933#define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk
4934#define CAN_F7R2_FB16_Pos (16U)
4935#define CAN_F7R2_FB16_Msk (0x1UL << CAN_F7R2_FB16_Pos)
4936#define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk
4937#define CAN_F7R2_FB17_Pos (17U)
4938#define CAN_F7R2_FB17_Msk (0x1UL << CAN_F7R2_FB17_Pos)
4939#define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk
4940#define CAN_F7R2_FB18_Pos (18U)
4941#define CAN_F7R2_FB18_Msk (0x1UL << CAN_F7R2_FB18_Pos)
4942#define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk
4943#define CAN_F7R2_FB19_Pos (19U)
4944#define CAN_F7R2_FB19_Msk (0x1UL << CAN_F7R2_FB19_Pos)
4945#define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk
4946#define CAN_F7R2_FB20_Pos (20U)
4947#define CAN_F7R2_FB20_Msk (0x1UL << CAN_F7R2_FB20_Pos)
4948#define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk
4949#define CAN_F7R2_FB21_Pos (21U)
4950#define CAN_F7R2_FB21_Msk (0x1UL << CAN_F7R2_FB21_Pos)
4951#define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk
4952#define CAN_F7R2_FB22_Pos (22U)
4953#define CAN_F7R2_FB22_Msk (0x1UL << CAN_F7R2_FB22_Pos)
4954#define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk
4955#define CAN_F7R2_FB23_Pos (23U)
4956#define CAN_F7R2_FB23_Msk (0x1UL << CAN_F7R2_FB23_Pos)
4957#define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk
4958#define CAN_F7R2_FB24_Pos (24U)
4959#define CAN_F7R2_FB24_Msk (0x1UL << CAN_F7R2_FB24_Pos)
4960#define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk
4961#define CAN_F7R2_FB25_Pos (25U)
4962#define CAN_F7R2_FB25_Msk (0x1UL << CAN_F7R2_FB25_Pos)
4963#define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk
4964#define CAN_F7R2_FB26_Pos (26U)
4965#define CAN_F7R2_FB26_Msk (0x1UL << CAN_F7R2_FB26_Pos)
4966#define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk
4967#define CAN_F7R2_FB27_Pos (27U)
4968#define CAN_F7R2_FB27_Msk (0x1UL << CAN_F7R2_FB27_Pos)
4969#define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk
4970#define CAN_F7R2_FB28_Pos (28U)
4971#define CAN_F7R2_FB28_Msk (0x1UL << CAN_F7R2_FB28_Pos)
4972#define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk
4973#define CAN_F7R2_FB29_Pos (29U)
4974#define CAN_F7R2_FB29_Msk (0x1UL << CAN_F7R2_FB29_Pos)
4975#define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk
4976#define CAN_F7R2_FB30_Pos (30U)
4977#define CAN_F7R2_FB30_Msk (0x1UL << CAN_F7R2_FB30_Pos)
4978#define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk
4979#define CAN_F7R2_FB31_Pos (31U)
4980#define CAN_F7R2_FB31_Msk (0x1UL << CAN_F7R2_FB31_Pos)
4981#define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk
4982
4983/******************* Bit definition for CAN_F8R2 register *******************/
4984#define CAN_F8R2_FB0_Pos (0U)
4985#define CAN_F8R2_FB0_Msk (0x1UL << CAN_F8R2_FB0_Pos)
4986#define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk
4987#define CAN_F8R2_FB1_Pos (1U)
4988#define CAN_F8R2_FB1_Msk (0x1UL << CAN_F8R2_FB1_Pos)
4989#define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk
4990#define CAN_F8R2_FB2_Pos (2U)
4991#define CAN_F8R2_FB2_Msk (0x1UL << CAN_F8R2_FB2_Pos)
4992#define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk
4993#define CAN_F8R2_FB3_Pos (3U)
4994#define CAN_F8R2_FB3_Msk (0x1UL << CAN_F8R2_FB3_Pos)
4995#define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk
4996#define CAN_F8R2_FB4_Pos (4U)
4997#define CAN_F8R2_FB4_Msk (0x1UL << CAN_F8R2_FB4_Pos)
4998#define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk
4999#define CAN_F8R2_FB5_Pos (5U)
5000#define CAN_F8R2_FB5_Msk (0x1UL << CAN_F8R2_FB5_Pos)
5001#define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk
5002#define CAN_F8R2_FB6_Pos (6U)
5003#define CAN_F8R2_FB6_Msk (0x1UL << CAN_F8R2_FB6_Pos)
5004#define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk
5005#define CAN_F8R2_FB7_Pos (7U)
5006#define CAN_F8R2_FB7_Msk (0x1UL << CAN_F8R2_FB7_Pos)
5007#define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk
5008#define CAN_F8R2_FB8_Pos (8U)
5009#define CAN_F8R2_FB8_Msk (0x1UL << CAN_F8R2_FB8_Pos)
5010#define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk
5011#define CAN_F8R2_FB9_Pos (9U)
5012#define CAN_F8R2_FB9_Msk (0x1UL << CAN_F8R2_FB9_Pos)
5013#define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk
5014#define CAN_F8R2_FB10_Pos (10U)
5015#define CAN_F8R2_FB10_Msk (0x1UL << CAN_F8R2_FB10_Pos)
5016#define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk
5017#define CAN_F8R2_FB11_Pos (11U)
5018#define CAN_F8R2_FB11_Msk (0x1UL << CAN_F8R2_FB11_Pos)
5019#define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk
5020#define CAN_F8R2_FB12_Pos (12U)
5021#define CAN_F8R2_FB12_Msk (0x1UL << CAN_F8R2_FB12_Pos)
5022#define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk
5023#define CAN_F8R2_FB13_Pos (13U)
5024#define CAN_F8R2_FB13_Msk (0x1UL << CAN_F8R2_FB13_Pos)
5025#define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk
5026#define CAN_F8R2_FB14_Pos (14U)
5027#define CAN_F8R2_FB14_Msk (0x1UL << CAN_F8R2_FB14_Pos)
5028#define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk
5029#define CAN_F8R2_FB15_Pos (15U)
5030#define CAN_F8R2_FB15_Msk (0x1UL << CAN_F8R2_FB15_Pos)
5031#define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk
5032#define CAN_F8R2_FB16_Pos (16U)
5033#define CAN_F8R2_FB16_Msk (0x1UL << CAN_F8R2_FB16_Pos)
5034#define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk
5035#define CAN_F8R2_FB17_Pos (17U)
5036#define CAN_F8R2_FB17_Msk (0x1UL << CAN_F8R2_FB17_Pos)
5037#define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk
5038#define CAN_F8R2_FB18_Pos (18U)
5039#define CAN_F8R2_FB18_Msk (0x1UL << CAN_F8R2_FB18_Pos)
5040#define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk
5041#define CAN_F8R2_FB19_Pos (19U)
5042#define CAN_F8R2_FB19_Msk (0x1UL << CAN_F8R2_FB19_Pos)
5043#define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk
5044#define CAN_F8R2_FB20_Pos (20U)
5045#define CAN_F8R2_FB20_Msk (0x1UL << CAN_F8R2_FB20_Pos)
5046#define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk
5047#define CAN_F8R2_FB21_Pos (21U)
5048#define CAN_F8R2_FB21_Msk (0x1UL << CAN_F8R2_FB21_Pos)
5049#define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk
5050#define CAN_F8R2_FB22_Pos (22U)
5051#define CAN_F8R2_FB22_Msk (0x1UL << CAN_F8R2_FB22_Pos)
5052#define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk
5053#define CAN_F8R2_FB23_Pos (23U)
5054#define CAN_F8R2_FB23_Msk (0x1UL << CAN_F8R2_FB23_Pos)
5055#define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk
5056#define CAN_F8R2_FB24_Pos (24U)
5057#define CAN_F8R2_FB24_Msk (0x1UL << CAN_F8R2_FB24_Pos)
5058#define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk
5059#define CAN_F8R2_FB25_Pos (25U)
5060#define CAN_F8R2_FB25_Msk (0x1UL << CAN_F8R2_FB25_Pos)
5061#define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk
5062#define CAN_F8R2_FB26_Pos (26U)
5063#define CAN_F8R2_FB26_Msk (0x1UL << CAN_F8R2_FB26_Pos)
5064#define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk
5065#define CAN_F8R2_FB27_Pos (27U)
5066#define CAN_F8R2_FB27_Msk (0x1UL << CAN_F8R2_FB27_Pos)
5067#define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk
5068#define CAN_F8R2_FB28_Pos (28U)
5069#define CAN_F8R2_FB28_Msk (0x1UL << CAN_F8R2_FB28_Pos)
5070#define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk
5071#define CAN_F8R2_FB29_Pos (29U)
5072#define CAN_F8R2_FB29_Msk (0x1UL << CAN_F8R2_FB29_Pos)
5073#define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk
5074#define CAN_F8R2_FB30_Pos (30U)
5075#define CAN_F8R2_FB30_Msk (0x1UL << CAN_F8R2_FB30_Pos)
5076#define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk
5077#define CAN_F8R2_FB31_Pos (31U)
5078#define CAN_F8R2_FB31_Msk (0x1UL << CAN_F8R2_FB31_Pos)
5079#define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk
5080
5081/******************* Bit definition for CAN_F9R2 register *******************/
5082#define CAN_F9R2_FB0_Pos (0U)
5083#define CAN_F9R2_FB0_Msk (0x1UL << CAN_F9R2_FB0_Pos)
5084#define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk
5085#define CAN_F9R2_FB1_Pos (1U)
5086#define CAN_F9R2_FB1_Msk (0x1UL << CAN_F9R2_FB1_Pos)
5087#define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk
5088#define CAN_F9R2_FB2_Pos (2U)
5089#define CAN_F9R2_FB2_Msk (0x1UL << CAN_F9R2_FB2_Pos)
5090#define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk
5091#define CAN_F9R2_FB3_Pos (3U)
5092#define CAN_F9R2_FB3_Msk (0x1UL << CAN_F9R2_FB3_Pos)
5093#define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk
5094#define CAN_F9R2_FB4_Pos (4U)
5095#define CAN_F9R2_FB4_Msk (0x1UL << CAN_F9R2_FB4_Pos)
5096#define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk
5097#define CAN_F9R2_FB5_Pos (5U)
5098#define CAN_F9R2_FB5_Msk (0x1UL << CAN_F9R2_FB5_Pos)
5099#define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk
5100#define CAN_F9R2_FB6_Pos (6U)
5101#define CAN_F9R2_FB6_Msk (0x1UL << CAN_F9R2_FB6_Pos)
5102#define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk
5103#define CAN_F9R2_FB7_Pos (7U)
5104#define CAN_F9R2_FB7_Msk (0x1UL << CAN_F9R2_FB7_Pos)
5105#define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk
5106#define CAN_F9R2_FB8_Pos (8U)
5107#define CAN_F9R2_FB8_Msk (0x1UL << CAN_F9R2_FB8_Pos)
5108#define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk
5109#define CAN_F9R2_FB9_Pos (9U)
5110#define CAN_F9R2_FB9_Msk (0x1UL << CAN_F9R2_FB9_Pos)
5111#define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk
5112#define CAN_F9R2_FB10_Pos (10U)
5113#define CAN_F9R2_FB10_Msk (0x1UL << CAN_F9R2_FB10_Pos)
5114#define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk
5115#define CAN_F9R2_FB11_Pos (11U)
5116#define CAN_F9R2_FB11_Msk (0x1UL << CAN_F9R2_FB11_Pos)
5117#define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk
5118#define CAN_F9R2_FB12_Pos (12U)
5119#define CAN_F9R2_FB12_Msk (0x1UL << CAN_F9R2_FB12_Pos)
5120#define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk
5121#define CAN_F9R2_FB13_Pos (13U)
5122#define CAN_F9R2_FB13_Msk (0x1UL << CAN_F9R2_FB13_Pos)
5123#define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk
5124#define CAN_F9R2_FB14_Pos (14U)
5125#define CAN_F9R2_FB14_Msk (0x1UL << CAN_F9R2_FB14_Pos)
5126#define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk
5127#define CAN_F9R2_FB15_Pos (15U)
5128#define CAN_F9R2_FB15_Msk (0x1UL << CAN_F9R2_FB15_Pos)
5129#define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk
5130#define CAN_F9R2_FB16_Pos (16U)
5131#define CAN_F9R2_FB16_Msk (0x1UL << CAN_F9R2_FB16_Pos)
5132#define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk
5133#define CAN_F9R2_FB17_Pos (17U)
5134#define CAN_F9R2_FB17_Msk (0x1UL << CAN_F9R2_FB17_Pos)
5135#define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk
5136#define CAN_F9R2_FB18_Pos (18U)
5137#define CAN_F9R2_FB18_Msk (0x1UL << CAN_F9R2_FB18_Pos)
5138#define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk
5139#define CAN_F9R2_FB19_Pos (19U)
5140#define CAN_F9R2_FB19_Msk (0x1UL << CAN_F9R2_FB19_Pos)
5141#define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk
5142#define CAN_F9R2_FB20_Pos (20U)
5143#define CAN_F9R2_FB20_Msk (0x1UL << CAN_F9R2_FB20_Pos)
5144#define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk
5145#define CAN_F9R2_FB21_Pos (21U)
5146#define CAN_F9R2_FB21_Msk (0x1UL << CAN_F9R2_FB21_Pos)
5147#define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk
5148#define CAN_F9R2_FB22_Pos (22U)
5149#define CAN_F9R2_FB22_Msk (0x1UL << CAN_F9R2_FB22_Pos)
5150#define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk
5151#define CAN_F9R2_FB23_Pos (23U)
5152#define CAN_F9R2_FB23_Msk (0x1UL << CAN_F9R2_FB23_Pos)
5153#define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk
5154#define CAN_F9R2_FB24_Pos (24U)
5155#define CAN_F9R2_FB24_Msk (0x1UL << CAN_F9R2_FB24_Pos)
5156#define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk
5157#define CAN_F9R2_FB25_Pos (25U)
5158#define CAN_F9R2_FB25_Msk (0x1UL << CAN_F9R2_FB25_Pos)
5159#define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk
5160#define CAN_F9R2_FB26_Pos (26U)
5161#define CAN_F9R2_FB26_Msk (0x1UL << CAN_F9R2_FB26_Pos)
5162#define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk
5163#define CAN_F9R2_FB27_Pos (27U)
5164#define CAN_F9R2_FB27_Msk (0x1UL << CAN_F9R2_FB27_Pos)
5165#define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk
5166#define CAN_F9R2_FB28_Pos (28U)
5167#define CAN_F9R2_FB28_Msk (0x1UL << CAN_F9R2_FB28_Pos)
5168#define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk
5169#define CAN_F9R2_FB29_Pos (29U)
5170#define CAN_F9R2_FB29_Msk (0x1UL << CAN_F9R2_FB29_Pos)
5171#define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk
5172#define CAN_F9R2_FB30_Pos (30U)
5173#define CAN_F9R2_FB30_Msk (0x1UL << CAN_F9R2_FB30_Pos)
5174#define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk
5175#define CAN_F9R2_FB31_Pos (31U)
5176#define CAN_F9R2_FB31_Msk (0x1UL << CAN_F9R2_FB31_Pos)
5177#define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk
5178
5179/******************* Bit definition for CAN_F10R2 register ******************/
5180#define CAN_F10R2_FB0_Pos (0U)
5181#define CAN_F10R2_FB0_Msk (0x1UL << CAN_F10R2_FB0_Pos)
5182#define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk
5183#define CAN_F10R2_FB1_Pos (1U)
5184#define CAN_F10R2_FB1_Msk (0x1UL << CAN_F10R2_FB1_Pos)
5185#define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk
5186#define CAN_F10R2_FB2_Pos (2U)
5187#define CAN_F10R2_FB2_Msk (0x1UL << CAN_F10R2_FB2_Pos)
5188#define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk
5189#define CAN_F10R2_FB3_Pos (3U)
5190#define CAN_F10R2_FB3_Msk (0x1UL << CAN_F10R2_FB3_Pos)
5191#define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk
5192#define CAN_F10R2_FB4_Pos (4U)
5193#define CAN_F10R2_FB4_Msk (0x1UL << CAN_F10R2_FB4_Pos)
5194#define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk
5195#define CAN_F10R2_FB5_Pos (5U)
5196#define CAN_F10R2_FB5_Msk (0x1UL << CAN_F10R2_FB5_Pos)
5197#define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk
5198#define CAN_F10R2_FB6_Pos (6U)
5199#define CAN_F10R2_FB6_Msk (0x1UL << CAN_F10R2_FB6_Pos)
5200#define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk
5201#define CAN_F10R2_FB7_Pos (7U)
5202#define CAN_F10R2_FB7_Msk (0x1UL << CAN_F10R2_FB7_Pos)
5203#define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk
5204#define CAN_F10R2_FB8_Pos (8U)
5205#define CAN_F10R2_FB8_Msk (0x1UL << CAN_F10R2_FB8_Pos)
5206#define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk
5207#define CAN_F10R2_FB9_Pos (9U)
5208#define CAN_F10R2_FB9_Msk (0x1UL << CAN_F10R2_FB9_Pos)
5209#define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk
5210#define CAN_F10R2_FB10_Pos (10U)
5211#define CAN_F10R2_FB10_Msk (0x1UL << CAN_F10R2_FB10_Pos)
5212#define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk
5213#define CAN_F10R2_FB11_Pos (11U)
5214#define CAN_F10R2_FB11_Msk (0x1UL << CAN_F10R2_FB11_Pos)
5215#define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk
5216#define CAN_F10R2_FB12_Pos (12U)
5217#define CAN_F10R2_FB12_Msk (0x1UL << CAN_F10R2_FB12_Pos)
5218#define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk
5219#define CAN_F10R2_FB13_Pos (13U)
5220#define CAN_F10R2_FB13_Msk (0x1UL << CAN_F10R2_FB13_Pos)
5221#define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk
5222#define CAN_F10R2_FB14_Pos (14U)
5223#define CAN_F10R2_FB14_Msk (0x1UL << CAN_F10R2_FB14_Pos)
5224#define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk
5225#define CAN_F10R2_FB15_Pos (15U)
5226#define CAN_F10R2_FB15_Msk (0x1UL << CAN_F10R2_FB15_Pos)
5227#define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk
5228#define CAN_F10R2_FB16_Pos (16U)
5229#define CAN_F10R2_FB16_Msk (0x1UL << CAN_F10R2_FB16_Pos)
5230#define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk
5231#define CAN_F10R2_FB17_Pos (17U)
5232#define CAN_F10R2_FB17_Msk (0x1UL << CAN_F10R2_FB17_Pos)
5233#define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk
5234#define CAN_F10R2_FB18_Pos (18U)
5235#define CAN_F10R2_FB18_Msk (0x1UL << CAN_F10R2_FB18_Pos)
5236#define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk
5237#define CAN_F10R2_FB19_Pos (19U)
5238#define CAN_F10R2_FB19_Msk (0x1UL << CAN_F10R2_FB19_Pos)
5239#define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk
5240#define CAN_F10R2_FB20_Pos (20U)
5241#define CAN_F10R2_FB20_Msk (0x1UL << CAN_F10R2_FB20_Pos)
5242#define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk
5243#define CAN_F10R2_FB21_Pos (21U)
5244#define CAN_F10R2_FB21_Msk (0x1UL << CAN_F10R2_FB21_Pos)
5245#define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk
5246#define CAN_F10R2_FB22_Pos (22U)
5247#define CAN_F10R2_FB22_Msk (0x1UL << CAN_F10R2_FB22_Pos)
5248#define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk
5249#define CAN_F10R2_FB23_Pos (23U)
5250#define CAN_F10R2_FB23_Msk (0x1UL << CAN_F10R2_FB23_Pos)
5251#define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk
5252#define CAN_F10R2_FB24_Pos (24U)
5253#define CAN_F10R2_FB24_Msk (0x1UL << CAN_F10R2_FB24_Pos)
5254#define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk
5255#define CAN_F10R2_FB25_Pos (25U)
5256#define CAN_F10R2_FB25_Msk (0x1UL << CAN_F10R2_FB25_Pos)
5257#define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk
5258#define CAN_F10R2_FB26_Pos (26U)
5259#define CAN_F10R2_FB26_Msk (0x1UL << CAN_F10R2_FB26_Pos)
5260#define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk
5261#define CAN_F10R2_FB27_Pos (27U)
5262#define CAN_F10R2_FB27_Msk (0x1UL << CAN_F10R2_FB27_Pos)
5263#define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk
5264#define CAN_F10R2_FB28_Pos (28U)
5265#define CAN_F10R2_FB28_Msk (0x1UL << CAN_F10R2_FB28_Pos)
5266#define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk
5267#define CAN_F10R2_FB29_Pos (29U)
5268#define CAN_F10R2_FB29_Msk (0x1UL << CAN_F10R2_FB29_Pos)
5269#define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk
5270#define CAN_F10R2_FB30_Pos (30U)
5271#define CAN_F10R2_FB30_Msk (0x1UL << CAN_F10R2_FB30_Pos)
5272#define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk
5273#define CAN_F10R2_FB31_Pos (31U)
5274#define CAN_F10R2_FB31_Msk (0x1UL << CAN_F10R2_FB31_Pos)
5275#define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk
5276
5277/******************* Bit definition for CAN_F11R2 register ******************/
5278#define CAN_F11R2_FB0_Pos (0U)
5279#define CAN_F11R2_FB0_Msk (0x1UL << CAN_F11R2_FB0_Pos)
5280#define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk
5281#define CAN_F11R2_FB1_Pos (1U)
5282#define CAN_F11R2_FB1_Msk (0x1UL << CAN_F11R2_FB1_Pos)
5283#define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk
5284#define CAN_F11R2_FB2_Pos (2U)
5285#define CAN_F11R2_FB2_Msk (0x1UL << CAN_F11R2_FB2_Pos)
5286#define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk
5287#define CAN_F11R2_FB3_Pos (3U)
5288#define CAN_F11R2_FB3_Msk (0x1UL << CAN_F11R2_FB3_Pos)
5289#define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk
5290#define CAN_F11R2_FB4_Pos (4U)
5291#define CAN_F11R2_FB4_Msk (0x1UL << CAN_F11R2_FB4_Pos)
5292#define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk
5293#define CAN_F11R2_FB5_Pos (5U)
5294#define CAN_F11R2_FB5_Msk (0x1UL << CAN_F11R2_FB5_Pos)
5295#define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk
5296#define CAN_F11R2_FB6_Pos (6U)
5297#define CAN_F11R2_FB6_Msk (0x1UL << CAN_F11R2_FB6_Pos)
5298#define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk
5299#define CAN_F11R2_FB7_Pos (7U)
5300#define CAN_F11R2_FB7_Msk (0x1UL << CAN_F11R2_FB7_Pos)
5301#define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk
5302#define CAN_F11R2_FB8_Pos (8U)
5303#define CAN_F11R2_FB8_Msk (0x1UL << CAN_F11R2_FB8_Pos)
5304#define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk
5305#define CAN_F11R2_FB9_Pos (9U)
5306#define CAN_F11R2_FB9_Msk (0x1UL << CAN_F11R2_FB9_Pos)
5307#define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk
5308#define CAN_F11R2_FB10_Pos (10U)
5309#define CAN_F11R2_FB10_Msk (0x1UL << CAN_F11R2_FB10_Pos)
5310#define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk
5311#define CAN_F11R2_FB11_Pos (11U)
5312#define CAN_F11R2_FB11_Msk (0x1UL << CAN_F11R2_FB11_Pos)
5313#define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk
5314#define CAN_F11R2_FB12_Pos (12U)
5315#define CAN_F11R2_FB12_Msk (0x1UL << CAN_F11R2_FB12_Pos)
5316#define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk
5317#define CAN_F11R2_FB13_Pos (13U)
5318#define CAN_F11R2_FB13_Msk (0x1UL << CAN_F11R2_FB13_Pos)
5319#define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk
5320#define CAN_F11R2_FB14_Pos (14U)
5321#define CAN_F11R2_FB14_Msk (0x1UL << CAN_F11R2_FB14_Pos)
5322#define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk
5323#define CAN_F11R2_FB15_Pos (15U)
5324#define CAN_F11R2_FB15_Msk (0x1UL << CAN_F11R2_FB15_Pos)
5325#define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk
5326#define CAN_F11R2_FB16_Pos (16U)
5327#define CAN_F11R2_FB16_Msk (0x1UL << CAN_F11R2_FB16_Pos)
5328#define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk
5329#define CAN_F11R2_FB17_Pos (17U)
5330#define CAN_F11R2_FB17_Msk (0x1UL << CAN_F11R2_FB17_Pos)
5331#define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk
5332#define CAN_F11R2_FB18_Pos (18U)
5333#define CAN_F11R2_FB18_Msk (0x1UL << CAN_F11R2_FB18_Pos)
5334#define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk
5335#define CAN_F11R2_FB19_Pos (19U)
5336#define CAN_F11R2_FB19_Msk (0x1UL << CAN_F11R2_FB19_Pos)
5337#define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk
5338#define CAN_F11R2_FB20_Pos (20U)
5339#define CAN_F11R2_FB20_Msk (0x1UL << CAN_F11R2_FB20_Pos)
5340#define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk
5341#define CAN_F11R2_FB21_Pos (21U)
5342#define CAN_F11R2_FB21_Msk (0x1UL << CAN_F11R2_FB21_Pos)
5343#define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk
5344#define CAN_F11R2_FB22_Pos (22U)
5345#define CAN_F11R2_FB22_Msk (0x1UL << CAN_F11R2_FB22_Pos)
5346#define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk
5347#define CAN_F11R2_FB23_Pos (23U)
5348#define CAN_F11R2_FB23_Msk (0x1UL << CAN_F11R2_FB23_Pos)
5349#define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk
5350#define CAN_F11R2_FB24_Pos (24U)
5351#define CAN_F11R2_FB24_Msk (0x1UL << CAN_F11R2_FB24_Pos)
5352#define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk
5353#define CAN_F11R2_FB25_Pos (25U)
5354#define CAN_F11R2_FB25_Msk (0x1UL << CAN_F11R2_FB25_Pos)
5355#define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk
5356#define CAN_F11R2_FB26_Pos (26U)
5357#define CAN_F11R2_FB26_Msk (0x1UL << CAN_F11R2_FB26_Pos)
5358#define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk
5359#define CAN_F11R2_FB27_Pos (27U)
5360#define CAN_F11R2_FB27_Msk (0x1UL << CAN_F11R2_FB27_Pos)
5361#define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk
5362#define CAN_F11R2_FB28_Pos (28U)
5363#define CAN_F11R2_FB28_Msk (0x1UL << CAN_F11R2_FB28_Pos)
5364#define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk
5365#define CAN_F11R2_FB29_Pos (29U)
5366#define CAN_F11R2_FB29_Msk (0x1UL << CAN_F11R2_FB29_Pos)
5367#define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk
5368#define CAN_F11R2_FB30_Pos (30U)
5369#define CAN_F11R2_FB30_Msk (0x1UL << CAN_F11R2_FB30_Pos)
5370#define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk
5371#define CAN_F11R2_FB31_Pos (31U)
5372#define CAN_F11R2_FB31_Msk (0x1UL << CAN_F11R2_FB31_Pos)
5373#define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk
5374
5375/******************* Bit definition for CAN_F12R2 register ******************/
5376#define CAN_F12R2_FB0_Pos (0U)
5377#define CAN_F12R2_FB0_Msk (0x1UL << CAN_F12R2_FB0_Pos)
5378#define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk
5379#define CAN_F12R2_FB1_Pos (1U)
5380#define CAN_F12R2_FB1_Msk (0x1UL << CAN_F12R2_FB1_Pos)
5381#define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk
5382#define CAN_F12R2_FB2_Pos (2U)
5383#define CAN_F12R2_FB2_Msk (0x1UL << CAN_F12R2_FB2_Pos)
5384#define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk
5385#define CAN_F12R2_FB3_Pos (3U)
5386#define CAN_F12R2_FB3_Msk (0x1UL << CAN_F12R2_FB3_Pos)
5387#define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk
5388#define CAN_F12R2_FB4_Pos (4U)
5389#define CAN_F12R2_FB4_Msk (0x1UL << CAN_F12R2_FB4_Pos)
5390#define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk
5391#define CAN_F12R2_FB5_Pos (5U)
5392#define CAN_F12R2_FB5_Msk (0x1UL << CAN_F12R2_FB5_Pos)
5393#define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk
5394#define CAN_F12R2_FB6_Pos (6U)
5395#define CAN_F12R2_FB6_Msk (0x1UL << CAN_F12R2_FB6_Pos)
5396#define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk
5397#define CAN_F12R2_FB7_Pos (7U)
5398#define CAN_F12R2_FB7_Msk (0x1UL << CAN_F12R2_FB7_Pos)
5399#define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk
5400#define CAN_F12R2_FB8_Pos (8U)
5401#define CAN_F12R2_FB8_Msk (0x1UL << CAN_F12R2_FB8_Pos)
5402#define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk
5403#define CAN_F12R2_FB9_Pos (9U)
5404#define CAN_F12R2_FB9_Msk (0x1UL << CAN_F12R2_FB9_Pos)
5405#define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk
5406#define CAN_F12R2_FB10_Pos (10U)
5407#define CAN_F12R2_FB10_Msk (0x1UL << CAN_F12R2_FB10_Pos)
5408#define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk
5409#define CAN_F12R2_FB11_Pos (11U)
5410#define CAN_F12R2_FB11_Msk (0x1UL << CAN_F12R2_FB11_Pos)
5411#define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk
5412#define CAN_F12R2_FB12_Pos (12U)
5413#define CAN_F12R2_FB12_Msk (0x1UL << CAN_F12R2_FB12_Pos)
5414#define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk
5415#define CAN_F12R2_FB13_Pos (13U)
5416#define CAN_F12R2_FB13_Msk (0x1UL << CAN_F12R2_FB13_Pos)
5417#define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk
5418#define CAN_F12R2_FB14_Pos (14U)
5419#define CAN_F12R2_FB14_Msk (0x1UL << CAN_F12R2_FB14_Pos)
5420#define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk
5421#define CAN_F12R2_FB15_Pos (15U)
5422#define CAN_F12R2_FB15_Msk (0x1UL << CAN_F12R2_FB15_Pos)
5423#define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk
5424#define CAN_F12R2_FB16_Pos (16U)
5425#define CAN_F12R2_FB16_Msk (0x1UL << CAN_F12R2_FB16_Pos)
5426#define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk
5427#define CAN_F12R2_FB17_Pos (17U)
5428#define CAN_F12R2_FB17_Msk (0x1UL << CAN_F12R2_FB17_Pos)
5429#define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk
5430#define CAN_F12R2_FB18_Pos (18U)
5431#define CAN_F12R2_FB18_Msk (0x1UL << CAN_F12R2_FB18_Pos)
5432#define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk
5433#define CAN_F12R2_FB19_Pos (19U)
5434#define CAN_F12R2_FB19_Msk (0x1UL << CAN_F12R2_FB19_Pos)
5435#define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk
5436#define CAN_F12R2_FB20_Pos (20U)
5437#define CAN_F12R2_FB20_Msk (0x1UL << CAN_F12R2_FB20_Pos)
5438#define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk
5439#define CAN_F12R2_FB21_Pos (21U)
5440#define CAN_F12R2_FB21_Msk (0x1UL << CAN_F12R2_FB21_Pos)
5441#define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk
5442#define CAN_F12R2_FB22_Pos (22U)
5443#define CAN_F12R2_FB22_Msk (0x1UL << CAN_F12R2_FB22_Pos)
5444#define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk
5445#define CAN_F12R2_FB23_Pos (23U)
5446#define CAN_F12R2_FB23_Msk (0x1UL << CAN_F12R2_FB23_Pos)
5447#define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk
5448#define CAN_F12R2_FB24_Pos (24U)
5449#define CAN_F12R2_FB24_Msk (0x1UL << CAN_F12R2_FB24_Pos)
5450#define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk
5451#define CAN_F12R2_FB25_Pos (25U)
5452#define CAN_F12R2_FB25_Msk (0x1UL << CAN_F12R2_FB25_Pos)
5453#define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk
5454#define CAN_F12R2_FB26_Pos (26U)
5455#define CAN_F12R2_FB26_Msk (0x1UL << CAN_F12R2_FB26_Pos)
5456#define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk
5457#define CAN_F12R2_FB27_Pos (27U)
5458#define CAN_F12R2_FB27_Msk (0x1UL << CAN_F12R2_FB27_Pos)
5459#define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk
5460#define CAN_F12R2_FB28_Pos (28U)
5461#define CAN_F12R2_FB28_Msk (0x1UL << CAN_F12R2_FB28_Pos)
5462#define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk
5463#define CAN_F12R2_FB29_Pos (29U)
5464#define CAN_F12R2_FB29_Msk (0x1UL << CAN_F12R2_FB29_Pos)
5465#define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk
5466#define CAN_F12R2_FB30_Pos (30U)
5467#define CAN_F12R2_FB30_Msk (0x1UL << CAN_F12R2_FB30_Pos)
5468#define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk
5469#define CAN_F12R2_FB31_Pos (31U)
5470#define CAN_F12R2_FB31_Msk (0x1UL << CAN_F12R2_FB31_Pos)
5471#define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk
5472
5473/******************* Bit definition for CAN_F13R2 register ******************/
5474#define CAN_F13R2_FB0_Pos (0U)
5475#define CAN_F13R2_FB0_Msk (0x1UL << CAN_F13R2_FB0_Pos)
5476#define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk
5477#define CAN_F13R2_FB1_Pos (1U)
5478#define CAN_F13R2_FB1_Msk (0x1UL << CAN_F13R2_FB1_Pos)
5479#define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk
5480#define CAN_F13R2_FB2_Pos (2U)
5481#define CAN_F13R2_FB2_Msk (0x1UL << CAN_F13R2_FB2_Pos)
5482#define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk
5483#define CAN_F13R2_FB3_Pos (3U)
5484#define CAN_F13R2_FB3_Msk (0x1UL << CAN_F13R2_FB3_Pos)
5485#define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk
5486#define CAN_F13R2_FB4_Pos (4U)
5487#define CAN_F13R2_FB4_Msk (0x1UL << CAN_F13R2_FB4_Pos)
5488#define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk
5489#define CAN_F13R2_FB5_Pos (5U)
5490#define CAN_F13R2_FB5_Msk (0x1UL << CAN_F13R2_FB5_Pos)
5491#define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk
5492#define CAN_F13R2_FB6_Pos (6U)
5493#define CAN_F13R2_FB6_Msk (0x1UL << CAN_F13R2_FB6_Pos)
5494#define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk
5495#define CAN_F13R2_FB7_Pos (7U)
5496#define CAN_F13R2_FB7_Msk (0x1UL << CAN_F13R2_FB7_Pos)
5497#define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk
5498#define CAN_F13R2_FB8_Pos (8U)
5499#define CAN_F13R2_FB8_Msk (0x1UL << CAN_F13R2_FB8_Pos)
5500#define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk
5501#define CAN_F13R2_FB9_Pos (9U)
5502#define CAN_F13R2_FB9_Msk (0x1UL << CAN_F13R2_FB9_Pos)
5503#define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk
5504#define CAN_F13R2_FB10_Pos (10U)
5505#define CAN_F13R2_FB10_Msk (0x1UL << CAN_F13R2_FB10_Pos)
5506#define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk
5507#define CAN_F13R2_FB11_Pos (11U)
5508#define CAN_F13R2_FB11_Msk (0x1UL << CAN_F13R2_FB11_Pos)
5509#define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk
5510#define CAN_F13R2_FB12_Pos (12U)
5511#define CAN_F13R2_FB12_Msk (0x1UL << CAN_F13R2_FB12_Pos)
5512#define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk
5513#define CAN_F13R2_FB13_Pos (13U)
5514#define CAN_F13R2_FB13_Msk (0x1UL << CAN_F13R2_FB13_Pos)
5515#define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk
5516#define CAN_F13R2_FB14_Pos (14U)
5517#define CAN_F13R2_FB14_Msk (0x1UL << CAN_F13R2_FB14_Pos)
5518#define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk
5519#define CAN_F13R2_FB15_Pos (15U)
5520#define CAN_F13R2_FB15_Msk (0x1UL << CAN_F13R2_FB15_Pos)
5521#define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk
5522#define CAN_F13R2_FB16_Pos (16U)
5523#define CAN_F13R2_FB16_Msk (0x1UL << CAN_F13R2_FB16_Pos)
5524#define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk
5525#define CAN_F13R2_FB17_Pos (17U)
5526#define CAN_F13R2_FB17_Msk (0x1UL << CAN_F13R2_FB17_Pos)
5527#define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk
5528#define CAN_F13R2_FB18_Pos (18U)
5529#define CAN_F13R2_FB18_Msk (0x1UL << CAN_F13R2_FB18_Pos)
5530#define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk
5531#define CAN_F13R2_FB19_Pos (19U)
5532#define CAN_F13R2_FB19_Msk (0x1UL << CAN_F13R2_FB19_Pos)
5533#define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk
5534#define CAN_F13R2_FB20_Pos (20U)
5535#define CAN_F13R2_FB20_Msk (0x1UL << CAN_F13R2_FB20_Pos)
5536#define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk
5537#define CAN_F13R2_FB21_Pos (21U)
5538#define CAN_F13R2_FB21_Msk (0x1UL << CAN_F13R2_FB21_Pos)
5539#define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk
5540#define CAN_F13R2_FB22_Pos (22U)
5541#define CAN_F13R2_FB22_Msk (0x1UL << CAN_F13R2_FB22_Pos)
5542#define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk
5543#define CAN_F13R2_FB23_Pos (23U)
5544#define CAN_F13R2_FB23_Msk (0x1UL << CAN_F13R2_FB23_Pos)
5545#define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk
5546#define CAN_F13R2_FB24_Pos (24U)
5547#define CAN_F13R2_FB24_Msk (0x1UL << CAN_F13R2_FB24_Pos)
5548#define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk
5549#define CAN_F13R2_FB25_Pos (25U)
5550#define CAN_F13R2_FB25_Msk (0x1UL << CAN_F13R2_FB25_Pos)
5551#define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk
5552#define CAN_F13R2_FB26_Pos (26U)
5553#define CAN_F13R2_FB26_Msk (0x1UL << CAN_F13R2_FB26_Pos)
5554#define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk
5555#define CAN_F13R2_FB27_Pos (27U)
5556#define CAN_F13R2_FB27_Msk (0x1UL << CAN_F13R2_FB27_Pos)
5557#define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk
5558#define CAN_F13R2_FB28_Pos (28U)
5559#define CAN_F13R2_FB28_Msk (0x1UL << CAN_F13R2_FB28_Pos)
5560#define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk
5561#define CAN_F13R2_FB29_Pos (29U)
5562#define CAN_F13R2_FB29_Msk (0x1UL << CAN_F13R2_FB29_Pos)
5563#define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk
5564#define CAN_F13R2_FB30_Pos (30U)
5565#define CAN_F13R2_FB30_Msk (0x1UL << CAN_F13R2_FB30_Pos)
5566#define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk
5567#define CAN_F13R2_FB31_Pos (31U)
5568#define CAN_F13R2_FB31_Msk (0x1UL << CAN_F13R2_FB31_Pos)
5569#define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk
5570
5571/******************************************************************************/
5572/* */
5573/* CRC calculation unit */
5574/* */
5575/******************************************************************************/
5576/******************* Bit definition for CRC_DR register *********************/
5577#define CRC_DR_DR_Pos (0U)
5578#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos)
5579#define CRC_DR_DR CRC_DR_DR_Msk
5580
5581
5582/******************* Bit definition for CRC_IDR register ********************/
5583#define CRC_IDR_IDR_Pos (0U)
5584#define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos)
5585#define CRC_IDR_IDR CRC_IDR_IDR_Msk
5586
5587
5588/******************** Bit definition for CRC_CR register ********************/
5589#define CRC_CR_RESET_Pos (0U)
5590#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos)
5591#define CRC_CR_RESET CRC_CR_RESET_Msk
5592
5593/******************************************************************************/
5594/* */
5595/* Digital to Analog Converter */
5596/* */
5597/******************************************************************************/
5598/*
5599 * @brief Specific device feature definitions (not present on all devices in the STM32F4 series)
5600 */
5601#define DAC_CHANNEL2_SUPPORT
5602/******************** Bit definition for DAC_CR register ********************/
5603#define DAC_CR_EN1_Pos (0U)
5604#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos)
5605#define DAC_CR_EN1 DAC_CR_EN1_Msk
5606#define DAC_CR_BOFF1_Pos (1U)
5607#define DAC_CR_BOFF1_Msk (0x1UL << DAC_CR_BOFF1_Pos)
5608#define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk
5609#define DAC_CR_TEN1_Pos (2U)
5610#define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos)
5611#define DAC_CR_TEN1 DAC_CR_TEN1_Msk
5612
5613#define DAC_CR_TSEL1_Pos (3U)
5614#define DAC_CR_TSEL1_Msk (0x7UL << DAC_CR_TSEL1_Pos)
5615#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk
5616#define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos)
5617#define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos)
5618#define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos)
5619
5620#define DAC_CR_WAVE1_Pos (6U)
5621#define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos)
5622#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk
5623#define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos)
5624#define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos)
5625
5626#define DAC_CR_MAMP1_Pos (8U)
5627#define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos)
5628#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk
5629#define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos)
5630#define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos)
5631#define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos)
5632#define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos)
5633
5634#define DAC_CR_DMAEN1_Pos (12U)
5635#define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos)
5636#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk
5637#define DAC_CR_DMAUDRIE1_Pos (13U)
5638#define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos)
5639#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk
5640#define DAC_CR_EN2_Pos (16U)
5641#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos)
5642#define DAC_CR_EN2 DAC_CR_EN2_Msk
5643#define DAC_CR_BOFF2_Pos (17U)
5644#define DAC_CR_BOFF2_Msk (0x1UL << DAC_CR_BOFF2_Pos)
5645#define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk
5646#define DAC_CR_TEN2_Pos (18U)
5647#define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos)
5648#define DAC_CR_TEN2 DAC_CR_TEN2_Msk
5649
5650#define DAC_CR_TSEL2_Pos (19U)
5651#define DAC_CR_TSEL2_Msk (0x7UL << DAC_CR_TSEL2_Pos)
5652#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk
5653#define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos)
5654#define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos)
5655#define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos)
5656
5657#define DAC_CR_WAVE2_Pos (22U)
5658#define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos)
5659#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk
5660#define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos)
5661#define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos)
5662
5663#define DAC_CR_MAMP2_Pos (24U)
5664#define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos)
5665#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk
5666#define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos)
5667#define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos)
5668#define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos)
5669#define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos)
5670
5671#define DAC_CR_DMAEN2_Pos (28U)
5672#define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos)
5673#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk
5674#define DAC_CR_DMAUDRIE2_Pos (29U)
5675#define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos)
5676#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk
5677
5678/***************** Bit definition for DAC_SWTRIGR register ******************/
5679#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
5680#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)
5681#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk
5682#define DAC_SWTRIGR_SWTRIG2_Pos (1U)
5683#define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)
5684#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk
5685
5686/***************** Bit definition for DAC_DHR12R1 register ******************/
5687#define DAC_DHR12R1_DACC1DHR_Pos (0U)
5688#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)
5689#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk
5690
5691/***************** Bit definition for DAC_DHR12L1 register ******************/
5692#define DAC_DHR12L1_DACC1DHR_Pos (4U)
5693#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)
5694#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk
5695
5696/****************** Bit definition for DAC_DHR8R1 register ******************/
5697#define DAC_DHR8R1_DACC1DHR_Pos (0U)
5698#define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)
5699#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk
5700
5701/***************** Bit definition for DAC_DHR12R2 register ******************/
5702#define DAC_DHR12R2_DACC2DHR_Pos (0U)
5703#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)
5704#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk
5705
5706/***************** Bit definition for DAC_DHR12L2 register ******************/
5707#define DAC_DHR12L2_DACC2DHR_Pos (4U)
5708#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)
5709#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk
5710
5711/****************** Bit definition for DAC_DHR8R2 register ******************/
5712#define DAC_DHR8R2_DACC2DHR_Pos (0U)
5713#define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)
5714#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk
5715
5716/***************** Bit definition for DAC_DHR12RD register ******************/
5717#define DAC_DHR12RD_DACC1DHR_Pos (0U)
5718#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)
5719#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk
5720#define DAC_DHR12RD_DACC2DHR_Pos (16U)
5721#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)
5722#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk
5723
5724/***************** Bit definition for DAC_DHR12LD register ******************/
5725#define DAC_DHR12LD_DACC1DHR_Pos (4U)
5726#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)
5727#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk
5728#define DAC_DHR12LD_DACC2DHR_Pos (20U)
5729#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)
5730#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk
5731
5732/****************** Bit definition for DAC_DHR8RD register ******************/
5733#define DAC_DHR8RD_DACC1DHR_Pos (0U)
5734#define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)
5735#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk
5736#define DAC_DHR8RD_DACC2DHR_Pos (8U)
5737#define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)
5738#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk
5739
5740/******************* Bit definition for DAC_DOR1 register *******************/
5741#define DAC_DOR1_DACC1DOR_Pos (0U)
5742#define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)
5743#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk
5744
5745/******************* Bit definition for DAC_DOR2 register *******************/
5746#define DAC_DOR2_DACC2DOR_Pos (0U)
5747#define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)
5748#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk
5749
5750/******************** Bit definition for DAC_SR register ********************/
5751#define DAC_SR_DMAUDR1_Pos (13U)
5752#define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos)
5753#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk
5754#define DAC_SR_DMAUDR2_Pos (29U)
5755#define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos)
5756#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk
5757
5758/******************************************************************************/
5759/* */
5760/* DCMI */
5761/* */
5762/******************************************************************************/
5763/******************** Bits definition for DCMI_CR register ******************/
5764#define DCMI_CR_CAPTURE_Pos (0U)
5765#define DCMI_CR_CAPTURE_Msk (0x1UL << DCMI_CR_CAPTURE_Pos)
5766#define DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk
5767#define DCMI_CR_CM_Pos (1U)
5768#define DCMI_CR_CM_Msk (0x1UL << DCMI_CR_CM_Pos)
5769#define DCMI_CR_CM DCMI_CR_CM_Msk
5770#define DCMI_CR_CROP_Pos (2U)
5771#define DCMI_CR_CROP_Msk (0x1UL << DCMI_CR_CROP_Pos)
5772#define DCMI_CR_CROP DCMI_CR_CROP_Msk
5773#define DCMI_CR_JPEG_Pos (3U)
5774#define DCMI_CR_JPEG_Msk (0x1UL << DCMI_CR_JPEG_Pos)
5775#define DCMI_CR_JPEG DCMI_CR_JPEG_Msk
5776#define DCMI_CR_ESS_Pos (4U)
5777#define DCMI_CR_ESS_Msk (0x1UL << DCMI_CR_ESS_Pos)
5778#define DCMI_CR_ESS DCMI_CR_ESS_Msk
5779#define DCMI_CR_PCKPOL_Pos (5U)
5780#define DCMI_CR_PCKPOL_Msk (0x1UL << DCMI_CR_PCKPOL_Pos)
5781#define DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk
5782#define DCMI_CR_HSPOL_Pos (6U)
5783#define DCMI_CR_HSPOL_Msk (0x1UL << DCMI_CR_HSPOL_Pos)
5784#define DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk
5785#define DCMI_CR_VSPOL_Pos (7U)
5786#define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos)
5787#define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
5788#define DCMI_CR_FCRC_0 0x00000100U
5789#define DCMI_CR_FCRC_1 0x00000200U
5790#define DCMI_CR_EDM_0 0x00000400U
5791#define DCMI_CR_EDM_1 0x00000800U
5792#define DCMI_CR_CRE_Pos (12U)
5793#define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos)
5794#define DCMI_CR_CRE DCMI_CR_CRE_Msk
5795#define DCMI_CR_ENABLE_Pos (14U)
5796#define DCMI_CR_ENABLE_Msk (0x1UL << DCMI_CR_ENABLE_Pos)
5797#define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk
5798
5799/******************** Bits definition for DCMI_SR register ******************/
5800#define DCMI_SR_HSYNC_Pos (0U)
5801#define DCMI_SR_HSYNC_Msk (0x1UL << DCMI_SR_HSYNC_Pos)
5802#define DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk
5803#define DCMI_SR_VSYNC_Pos (1U)
5804#define DCMI_SR_VSYNC_Msk (0x1UL << DCMI_SR_VSYNC_Pos)
5805#define DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk
5806#define DCMI_SR_FNE_Pos (2U)
5807#define DCMI_SR_FNE_Msk (0x1UL << DCMI_SR_FNE_Pos)
5808#define DCMI_SR_FNE DCMI_SR_FNE_Msk
5809
5810/******************** Bits definition for DCMI_RIS register *****************/
5811#define DCMI_RIS_FRAME_RIS_Pos (0U)
5812#define DCMI_RIS_FRAME_RIS_Msk (0x1UL << DCMI_RIS_FRAME_RIS_Pos)
5813#define DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk
5814#define DCMI_RIS_OVR_RIS_Pos (1U)
5815#define DCMI_RIS_OVR_RIS_Msk (0x1UL << DCMI_RIS_OVR_RIS_Pos)
5816#define DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk
5817#define DCMI_RIS_ERR_RIS_Pos (2U)
5818#define DCMI_RIS_ERR_RIS_Msk (0x1UL << DCMI_RIS_ERR_RIS_Pos)
5819#define DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk
5820#define DCMI_RIS_VSYNC_RIS_Pos (3U)
5821#define DCMI_RIS_VSYNC_RIS_Msk (0x1UL << DCMI_RIS_VSYNC_RIS_Pos)
5822#define DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk
5823#define DCMI_RIS_LINE_RIS_Pos (4U)
5824#define DCMI_RIS_LINE_RIS_Msk (0x1UL << DCMI_RIS_LINE_RIS_Pos)
5825#define DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk
5826/* Legacy defines */
5827#define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS
5828#define DCMI_RISR_OVR_RIS DCMI_RIS_OVR_RIS
5829#define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS
5830#define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS
5831#define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS
5832#define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS
5833
5834/******************** Bits definition for DCMI_IER register *****************/
5835#define DCMI_IER_FRAME_IE_Pos (0U)
5836#define DCMI_IER_FRAME_IE_Msk (0x1UL << DCMI_IER_FRAME_IE_Pos)
5837#define DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk
5838#define DCMI_IER_OVR_IE_Pos (1U)
5839#define DCMI_IER_OVR_IE_Msk (0x1UL << DCMI_IER_OVR_IE_Pos)
5840#define DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk
5841#define DCMI_IER_ERR_IE_Pos (2U)
5842#define DCMI_IER_ERR_IE_Msk (0x1UL << DCMI_IER_ERR_IE_Pos)
5843#define DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk
5844#define DCMI_IER_VSYNC_IE_Pos (3U)
5845#define DCMI_IER_VSYNC_IE_Msk (0x1UL << DCMI_IER_VSYNC_IE_Pos)
5846#define DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk
5847#define DCMI_IER_LINE_IE_Pos (4U)
5848#define DCMI_IER_LINE_IE_Msk (0x1UL << DCMI_IER_LINE_IE_Pos)
5849#define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk
5850/* Legacy defines */
5851#define DCMI_IER_OVF_IE DCMI_IER_OVR_IE
5852
5853/******************** Bits definition for DCMI_MIS register *****************/
5854#define DCMI_MIS_FRAME_MIS_Pos (0U)
5855#define DCMI_MIS_FRAME_MIS_Msk (0x1UL << DCMI_MIS_FRAME_MIS_Pos)
5856#define DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk
5857#define DCMI_MIS_OVR_MIS_Pos (1U)
5858#define DCMI_MIS_OVR_MIS_Msk (0x1UL << DCMI_MIS_OVR_MIS_Pos)
5859#define DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk
5860#define DCMI_MIS_ERR_MIS_Pos (2U)
5861#define DCMI_MIS_ERR_MIS_Msk (0x1UL << DCMI_MIS_ERR_MIS_Pos)
5862#define DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk
5863#define DCMI_MIS_VSYNC_MIS_Pos (3U)
5864#define DCMI_MIS_VSYNC_MIS_Msk (0x1UL << DCMI_MIS_VSYNC_MIS_Pos)
5865#define DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk
5866#define DCMI_MIS_LINE_MIS_Pos (4U)
5867#define DCMI_MIS_LINE_MIS_Msk (0x1UL << DCMI_MIS_LINE_MIS_Pos)
5868#define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk
5869
5870/* Legacy defines */
5871#define DCMI_MISR_FRAME_MIS DCMI_MIS_FRAME_MIS
5872#define DCMI_MISR_OVF_MIS DCMI_MIS_OVR_MIS
5873#define DCMI_MISR_ERR_MIS DCMI_MIS_ERR_MIS
5874#define DCMI_MISR_VSYNC_MIS DCMI_MIS_VSYNC_MIS
5875#define DCMI_MISR_LINE_MIS DCMI_MIS_LINE_MIS
5876
5877/******************** Bits definition for DCMI_ICR register *****************/
5878#define DCMI_ICR_FRAME_ISC_Pos (0U)
5879#define DCMI_ICR_FRAME_ISC_Msk (0x1UL << DCMI_ICR_FRAME_ISC_Pos)
5880#define DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk
5881#define DCMI_ICR_OVR_ISC_Pos (1U)
5882#define DCMI_ICR_OVR_ISC_Msk (0x1UL << DCMI_ICR_OVR_ISC_Pos)
5883#define DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk
5884#define DCMI_ICR_ERR_ISC_Pos (2U)
5885#define DCMI_ICR_ERR_ISC_Msk (0x1UL << DCMI_ICR_ERR_ISC_Pos)
5886#define DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk
5887#define DCMI_ICR_VSYNC_ISC_Pos (3U)
5888#define DCMI_ICR_VSYNC_ISC_Msk (0x1UL << DCMI_ICR_VSYNC_ISC_Pos)
5889#define DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk
5890#define DCMI_ICR_LINE_ISC_Pos (4U)
5891#define DCMI_ICR_LINE_ISC_Msk (0x1UL << DCMI_ICR_LINE_ISC_Pos)
5892#define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk
5893
5894/* Legacy defines */
5895#define DCMI_ICR_OVF_ISC DCMI_ICR_OVR_ISC
5896
5897/******************** Bits definition for DCMI_ESCR register ******************/
5898#define DCMI_ESCR_FSC_Pos (0U)
5899#define DCMI_ESCR_FSC_Msk (0xFFUL << DCMI_ESCR_FSC_Pos)
5900#define DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk
5901#define DCMI_ESCR_LSC_Pos (8U)
5902#define DCMI_ESCR_LSC_Msk (0xFFUL << DCMI_ESCR_LSC_Pos)
5903#define DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk
5904#define DCMI_ESCR_LEC_Pos (16U)
5905#define DCMI_ESCR_LEC_Msk (0xFFUL << DCMI_ESCR_LEC_Pos)
5906#define DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk
5907#define DCMI_ESCR_FEC_Pos (24U)
5908#define DCMI_ESCR_FEC_Msk (0xFFUL << DCMI_ESCR_FEC_Pos)
5909#define DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk
5910
5911/******************** Bits definition for DCMI_ESUR register ******************/
5912#define DCMI_ESUR_FSU_Pos (0U)
5913#define DCMI_ESUR_FSU_Msk (0xFFUL << DCMI_ESUR_FSU_Pos)
5914#define DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk
5915#define DCMI_ESUR_LSU_Pos (8U)
5916#define DCMI_ESUR_LSU_Msk (0xFFUL << DCMI_ESUR_LSU_Pos)
5917#define DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk
5918#define DCMI_ESUR_LEU_Pos (16U)
5919#define DCMI_ESUR_LEU_Msk (0xFFUL << DCMI_ESUR_LEU_Pos)
5920#define DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk
5921#define DCMI_ESUR_FEU_Pos (24U)
5922#define DCMI_ESUR_FEU_Msk (0xFFUL << DCMI_ESUR_FEU_Pos)
5923#define DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk
5924
5925/******************** Bits definition for DCMI_CWSTRT register ******************/
5926#define DCMI_CWSTRT_HOFFCNT_Pos (0U)
5927#define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos)
5928#define DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk
5929#define DCMI_CWSTRT_VST_Pos (16U)
5930#define DCMI_CWSTRT_VST_Msk (0x1FFFUL << DCMI_CWSTRT_VST_Pos)
5931#define DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk
5932
5933/******************** Bits definition for DCMI_CWSIZE register ******************/
5934#define DCMI_CWSIZE_CAPCNT_Pos (0U)
5935#define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos)
5936#define DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk
5937#define DCMI_CWSIZE_VLINE_Pos (16U)
5938#define DCMI_CWSIZE_VLINE_Msk (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos)
5939#define DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk
5940
5941/******************** Bits definition for DCMI_DR register *********************/
5942#define DCMI_DR_BYTE0_Pos (0U)
5943#define DCMI_DR_BYTE0_Msk (0xFFUL << DCMI_DR_BYTE0_Pos)
5944#define DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk
5945#define DCMI_DR_BYTE1_Pos (8U)
5946#define DCMI_DR_BYTE1_Msk (0xFFUL << DCMI_DR_BYTE1_Pos)
5947#define DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk
5948#define DCMI_DR_BYTE2_Pos (16U)
5949#define DCMI_DR_BYTE2_Msk (0xFFUL << DCMI_DR_BYTE2_Pos)
5950#define DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk
5951#define DCMI_DR_BYTE3_Pos (24U)
5952#define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos)
5953#define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk
5954
5955/******************************************************************************/
5956/* */
5957/* DMA Controller */
5958/* */
5959/******************************************************************************/
5960/******************** Bits definition for DMA_SxCR register *****************/
5961#define DMA_SxCR_CHSEL_Pos (25U)
5962#define DMA_SxCR_CHSEL_Msk (0x7UL << DMA_SxCR_CHSEL_Pos)
5963#define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk
5964#define DMA_SxCR_CHSEL_0 (0x1UL << DMA_SxCR_CHSEL_Pos)
5965#define DMA_SxCR_CHSEL_1 (0x2UL << DMA_SxCR_CHSEL_Pos)
5966#define DMA_SxCR_CHSEL_2 (0x4UL << DMA_SxCR_CHSEL_Pos)
5967#define DMA_SxCR_MBURST_Pos (23U)
5968#define DMA_SxCR_MBURST_Msk (0x3UL << DMA_SxCR_MBURST_Pos)
5969#define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
5970#define DMA_SxCR_MBURST_0 (0x1UL << DMA_SxCR_MBURST_Pos)
5971#define DMA_SxCR_MBURST_1 (0x2UL << DMA_SxCR_MBURST_Pos)
5972#define DMA_SxCR_PBURST_Pos (21U)
5973#define DMA_SxCR_PBURST_Msk (0x3UL << DMA_SxCR_PBURST_Pos)
5974#define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
5975#define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos)
5976#define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos)
5977#define DMA_SxCR_CT_Pos (19U)
5978#define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos)
5979#define DMA_SxCR_CT DMA_SxCR_CT_Msk
5980#define DMA_SxCR_DBM_Pos (18U)
5981#define DMA_SxCR_DBM_Msk (0x1UL << DMA_SxCR_DBM_Pos)
5982#define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
5983#define DMA_SxCR_PL_Pos (16U)
5984#define DMA_SxCR_PL_Msk (0x3UL << DMA_SxCR_PL_Pos)
5985#define DMA_SxCR_PL DMA_SxCR_PL_Msk
5986#define DMA_SxCR_PL_0 (0x1UL << DMA_SxCR_PL_Pos)
5987#define DMA_SxCR_PL_1 (0x2UL << DMA_SxCR_PL_Pos)
5988#define DMA_SxCR_PINCOS_Pos (15U)
5989#define DMA_SxCR_PINCOS_Msk (0x1UL << DMA_SxCR_PINCOS_Pos)
5990#define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
5991#define DMA_SxCR_MSIZE_Pos (13U)
5992#define DMA_SxCR_MSIZE_Msk (0x3UL << DMA_SxCR_MSIZE_Pos)
5993#define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
5994#define DMA_SxCR_MSIZE_0 (0x1UL << DMA_SxCR_MSIZE_Pos)
5995#define DMA_SxCR_MSIZE_1 (0x2UL << DMA_SxCR_MSIZE_Pos)
5996#define DMA_SxCR_PSIZE_Pos (11U)
5997#define DMA_SxCR_PSIZE_Msk (0x3UL << DMA_SxCR_PSIZE_Pos)
5998#define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk
5999#define DMA_SxCR_PSIZE_0 (0x1UL << DMA_SxCR_PSIZE_Pos)
6000#define DMA_SxCR_PSIZE_1 (0x2UL << DMA_SxCR_PSIZE_Pos)
6001#define DMA_SxCR_MINC_Pos (10U)
6002#define DMA_SxCR_MINC_Msk (0x1UL << DMA_SxCR_MINC_Pos)
6003#define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
6004#define DMA_SxCR_PINC_Pos (9U)
6005#define DMA_SxCR_PINC_Msk (0x1UL << DMA_SxCR_PINC_Pos)
6006#define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
6007#define DMA_SxCR_CIRC_Pos (8U)
6008#define DMA_SxCR_CIRC_Msk (0x1UL << DMA_SxCR_CIRC_Pos)
6009#define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
6010#define DMA_SxCR_DIR_Pos (6U)
6011#define DMA_SxCR_DIR_Msk (0x3UL << DMA_SxCR_DIR_Pos)
6012#define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
6013#define DMA_SxCR_DIR_0 (0x1UL << DMA_SxCR_DIR_Pos)
6014#define DMA_SxCR_DIR_1 (0x2UL << DMA_SxCR_DIR_Pos)
6015#define DMA_SxCR_PFCTRL_Pos (5U)
6016#define DMA_SxCR_PFCTRL_Msk (0x1UL << DMA_SxCR_PFCTRL_Pos)
6017#define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
6018#define DMA_SxCR_TCIE_Pos (4U)
6019#define DMA_SxCR_TCIE_Msk (0x1UL << DMA_SxCR_TCIE_Pos)
6020#define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
6021#define DMA_SxCR_HTIE_Pos (3U)
6022#define DMA_SxCR_HTIE_Msk (0x1UL << DMA_SxCR_HTIE_Pos)
6023#define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
6024#define DMA_SxCR_TEIE_Pos (2U)
6025#define DMA_SxCR_TEIE_Msk (0x1UL << DMA_SxCR_TEIE_Pos)
6026#define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
6027#define DMA_SxCR_DMEIE_Pos (1U)
6028#define DMA_SxCR_DMEIE_Msk (0x1UL << DMA_SxCR_DMEIE_Pos)
6029#define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
6030#define DMA_SxCR_EN_Pos (0U)
6031#define DMA_SxCR_EN_Msk (0x1UL << DMA_SxCR_EN_Pos)
6032#define DMA_SxCR_EN DMA_SxCR_EN_Msk
6033
6034/* Legacy defines */
6035#define DMA_SxCR_ACK_Pos (20U)
6036#define DMA_SxCR_ACK_Msk (0x1UL << DMA_SxCR_ACK_Pos)
6037#define DMA_SxCR_ACK DMA_SxCR_ACK_Msk
6038
6039/******************** Bits definition for DMA_SxCNDTR register **************/
6040#define DMA_SxNDT_Pos (0U)
6041#define DMA_SxNDT_Msk (0xFFFFUL << DMA_SxNDT_Pos)
6042#define DMA_SxNDT DMA_SxNDT_Msk
6043#define DMA_SxNDT_0 (0x0001UL << DMA_SxNDT_Pos)
6044#define DMA_SxNDT_1 (0x0002UL << DMA_SxNDT_Pos)
6045#define DMA_SxNDT_2 (0x0004UL << DMA_SxNDT_Pos)
6046#define DMA_SxNDT_3 (0x0008UL << DMA_SxNDT_Pos)
6047#define DMA_SxNDT_4 (0x0010UL << DMA_SxNDT_Pos)
6048#define DMA_SxNDT_5 (0x0020UL << DMA_SxNDT_Pos)
6049#define DMA_SxNDT_6 (0x0040UL << DMA_SxNDT_Pos)
6050#define DMA_SxNDT_7 (0x0080UL << DMA_SxNDT_Pos)
6051#define DMA_SxNDT_8 (0x0100UL << DMA_SxNDT_Pos)
6052#define DMA_SxNDT_9 (0x0200UL << DMA_SxNDT_Pos)
6053#define DMA_SxNDT_10 (0x0400UL << DMA_SxNDT_Pos)
6054#define DMA_SxNDT_11 (0x0800UL << DMA_SxNDT_Pos)
6055#define DMA_SxNDT_12 (0x1000UL << DMA_SxNDT_Pos)
6056#define DMA_SxNDT_13 (0x2000UL << DMA_SxNDT_Pos)
6057#define DMA_SxNDT_14 (0x4000UL << DMA_SxNDT_Pos)
6058#define DMA_SxNDT_15 (0x8000UL << DMA_SxNDT_Pos)
6059
6060/******************** Bits definition for DMA_SxFCR register ****************/
6061#define DMA_SxFCR_FEIE_Pos (7U)
6062#define DMA_SxFCR_FEIE_Msk (0x1UL << DMA_SxFCR_FEIE_Pos)
6063#define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
6064#define DMA_SxFCR_FS_Pos (3U)
6065#define DMA_SxFCR_FS_Msk (0x7UL << DMA_SxFCR_FS_Pos)
6066#define DMA_SxFCR_FS DMA_SxFCR_FS_Msk
6067#define DMA_SxFCR_FS_0 (0x1UL << DMA_SxFCR_FS_Pos)
6068#define DMA_SxFCR_FS_1 (0x2UL << DMA_SxFCR_FS_Pos)
6069#define DMA_SxFCR_FS_2 (0x4UL << DMA_SxFCR_FS_Pos)
6070#define DMA_SxFCR_DMDIS_Pos (2U)
6071#define DMA_SxFCR_DMDIS_Msk (0x1UL << DMA_SxFCR_DMDIS_Pos)
6072#define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
6073#define DMA_SxFCR_FTH_Pos (0U)
6074#define DMA_SxFCR_FTH_Msk (0x3UL << DMA_SxFCR_FTH_Pos)
6075#define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
6076#define DMA_SxFCR_FTH_0 (0x1UL << DMA_SxFCR_FTH_Pos)
6077#define DMA_SxFCR_FTH_1 (0x2UL << DMA_SxFCR_FTH_Pos)
6078
6079/******************** Bits definition for DMA_LISR register *****************/
6080#define DMA_LISR_TCIF3_Pos (27U)
6081#define DMA_LISR_TCIF3_Msk (0x1UL << DMA_LISR_TCIF3_Pos)
6082#define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
6083#define DMA_LISR_HTIF3_Pos (26U)
6084#define DMA_LISR_HTIF3_Msk (0x1UL << DMA_LISR_HTIF3_Pos)
6085#define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
6086#define DMA_LISR_TEIF3_Pos (25U)
6087#define DMA_LISR_TEIF3_Msk (0x1UL << DMA_LISR_TEIF3_Pos)
6088#define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
6089#define DMA_LISR_DMEIF3_Pos (24U)
6090#define DMA_LISR_DMEIF3_Msk (0x1UL << DMA_LISR_DMEIF3_Pos)
6091#define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
6092#define DMA_LISR_FEIF3_Pos (22U)
6093#define DMA_LISR_FEIF3_Msk (0x1UL << DMA_LISR_FEIF3_Pos)
6094#define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
6095#define DMA_LISR_TCIF2_Pos (21U)
6096#define DMA_LISR_TCIF2_Msk (0x1UL << DMA_LISR_TCIF2_Pos)
6097#define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
6098#define DMA_LISR_HTIF2_Pos (20U)
6099#define DMA_LISR_HTIF2_Msk (0x1UL << DMA_LISR_HTIF2_Pos)
6100#define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
6101#define DMA_LISR_TEIF2_Pos (19U)
6102#define DMA_LISR_TEIF2_Msk (0x1UL << DMA_LISR_TEIF2_Pos)
6103#define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
6104#define DMA_LISR_DMEIF2_Pos (18U)
6105#define DMA_LISR_DMEIF2_Msk (0x1UL << DMA_LISR_DMEIF2_Pos)
6106#define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
6107#define DMA_LISR_FEIF2_Pos (16U)
6108#define DMA_LISR_FEIF2_Msk (0x1UL << DMA_LISR_FEIF2_Pos)
6109#define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
6110#define DMA_LISR_TCIF1_Pos (11U)
6111#define DMA_LISR_TCIF1_Msk (0x1UL << DMA_LISR_TCIF1_Pos)
6112#define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
6113#define DMA_LISR_HTIF1_Pos (10U)
6114#define DMA_LISR_HTIF1_Msk (0x1UL << DMA_LISR_HTIF1_Pos)
6115#define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
6116#define DMA_LISR_TEIF1_Pos (9U)
6117#define DMA_LISR_TEIF1_Msk (0x1UL << DMA_LISR_TEIF1_Pos)
6118#define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
6119#define DMA_LISR_DMEIF1_Pos (8U)
6120#define DMA_LISR_DMEIF1_Msk (0x1UL << DMA_LISR_DMEIF1_Pos)
6121#define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
6122#define DMA_LISR_FEIF1_Pos (6U)
6123#define DMA_LISR_FEIF1_Msk (0x1UL << DMA_LISR_FEIF1_Pos)
6124#define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
6125#define DMA_LISR_TCIF0_Pos (5U)
6126#define DMA_LISR_TCIF0_Msk (0x1UL << DMA_LISR_TCIF0_Pos)
6127#define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
6128#define DMA_LISR_HTIF0_Pos (4U)
6129#define DMA_LISR_HTIF0_Msk (0x1UL << DMA_LISR_HTIF0_Pos)
6130#define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
6131#define DMA_LISR_TEIF0_Pos (3U)
6132#define DMA_LISR_TEIF0_Msk (0x1UL << DMA_LISR_TEIF0_Pos)
6133#define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
6134#define DMA_LISR_DMEIF0_Pos (2U)
6135#define DMA_LISR_DMEIF0_Msk (0x1UL << DMA_LISR_DMEIF0_Pos)
6136#define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
6137#define DMA_LISR_FEIF0_Pos (0U)
6138#define DMA_LISR_FEIF0_Msk (0x1UL << DMA_LISR_FEIF0_Pos)
6139#define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
6140
6141/******************** Bits definition for DMA_HISR register *****************/
6142#define DMA_HISR_TCIF7_Pos (27U)
6143#define DMA_HISR_TCIF7_Msk (0x1UL << DMA_HISR_TCIF7_Pos)
6144#define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
6145#define DMA_HISR_HTIF7_Pos (26U)
6146#define DMA_HISR_HTIF7_Msk (0x1UL << DMA_HISR_HTIF7_Pos)
6147#define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
6148#define DMA_HISR_TEIF7_Pos (25U)
6149#define DMA_HISR_TEIF7_Msk (0x1UL << DMA_HISR_TEIF7_Pos)
6150#define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
6151#define DMA_HISR_DMEIF7_Pos (24U)
6152#define DMA_HISR_DMEIF7_Msk (0x1UL << DMA_HISR_DMEIF7_Pos)
6153#define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
6154#define DMA_HISR_FEIF7_Pos (22U)
6155#define DMA_HISR_FEIF7_Msk (0x1UL << DMA_HISR_FEIF7_Pos)
6156#define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
6157#define DMA_HISR_TCIF6_Pos (21U)
6158#define DMA_HISR_TCIF6_Msk (0x1UL << DMA_HISR_TCIF6_Pos)
6159#define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
6160#define DMA_HISR_HTIF6_Pos (20U)
6161#define DMA_HISR_HTIF6_Msk (0x1UL << DMA_HISR_HTIF6_Pos)
6162#define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
6163#define DMA_HISR_TEIF6_Pos (19U)
6164#define DMA_HISR_TEIF6_Msk (0x1UL << DMA_HISR_TEIF6_Pos)
6165#define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
6166#define DMA_HISR_DMEIF6_Pos (18U)
6167#define DMA_HISR_DMEIF6_Msk (0x1UL << DMA_HISR_DMEIF6_Pos)
6168#define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
6169#define DMA_HISR_FEIF6_Pos (16U)
6170#define DMA_HISR_FEIF6_Msk (0x1UL << DMA_HISR_FEIF6_Pos)
6171#define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
6172#define DMA_HISR_TCIF5_Pos (11U)
6173#define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos)
6174#define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
6175#define DMA_HISR_HTIF5_Pos (10U)
6176#define DMA_HISR_HTIF5_Msk (0x1UL << DMA_HISR_HTIF5_Pos)
6177#define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
6178#define DMA_HISR_TEIF5_Pos (9U)
6179#define DMA_HISR_TEIF5_Msk (0x1UL << DMA_HISR_TEIF5_Pos)
6180#define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
6181#define DMA_HISR_DMEIF5_Pos (8U)
6182#define DMA_HISR_DMEIF5_Msk (0x1UL << DMA_HISR_DMEIF5_Pos)
6183#define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
6184#define DMA_HISR_FEIF5_Pos (6U)
6185#define DMA_HISR_FEIF5_Msk (0x1UL << DMA_HISR_FEIF5_Pos)
6186#define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
6187#define DMA_HISR_TCIF4_Pos (5U)
6188#define DMA_HISR_TCIF4_Msk (0x1UL << DMA_HISR_TCIF4_Pos)
6189#define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
6190#define DMA_HISR_HTIF4_Pos (4U)
6191#define DMA_HISR_HTIF4_Msk (0x1UL << DMA_HISR_HTIF4_Pos)
6192#define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
6193#define DMA_HISR_TEIF4_Pos (3U)
6194#define DMA_HISR_TEIF4_Msk (0x1UL << DMA_HISR_TEIF4_Pos)
6195#define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
6196#define DMA_HISR_DMEIF4_Pos (2U)
6197#define DMA_HISR_DMEIF4_Msk (0x1UL << DMA_HISR_DMEIF4_Pos)
6198#define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
6199#define DMA_HISR_FEIF4_Pos (0U)
6200#define DMA_HISR_FEIF4_Msk (0x1UL << DMA_HISR_FEIF4_Pos)
6201#define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
6202
6203/******************** Bits definition for DMA_LIFCR register ****************/
6204#define DMA_LIFCR_CTCIF3_Pos (27U)
6205#define DMA_LIFCR_CTCIF3_Msk (0x1UL << DMA_LIFCR_CTCIF3_Pos)
6206#define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
6207#define DMA_LIFCR_CHTIF3_Pos (26U)
6208#define DMA_LIFCR_CHTIF3_Msk (0x1UL << DMA_LIFCR_CHTIF3_Pos)
6209#define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
6210#define DMA_LIFCR_CTEIF3_Pos (25U)
6211#define DMA_LIFCR_CTEIF3_Msk (0x1UL << DMA_LIFCR_CTEIF3_Pos)
6212#define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
6213#define DMA_LIFCR_CDMEIF3_Pos (24U)
6214#define DMA_LIFCR_CDMEIF3_Msk (0x1UL << DMA_LIFCR_CDMEIF3_Pos)
6215#define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
6216#define DMA_LIFCR_CFEIF3_Pos (22U)
6217#define DMA_LIFCR_CFEIF3_Msk (0x1UL << DMA_LIFCR_CFEIF3_Pos)
6218#define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
6219#define DMA_LIFCR_CTCIF2_Pos (21U)
6220#define DMA_LIFCR_CTCIF2_Msk (0x1UL << DMA_LIFCR_CTCIF2_Pos)
6221#define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
6222#define DMA_LIFCR_CHTIF2_Pos (20U)
6223#define DMA_LIFCR_CHTIF2_Msk (0x1UL << DMA_LIFCR_CHTIF2_Pos)
6224#define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
6225#define DMA_LIFCR_CTEIF2_Pos (19U)
6226#define DMA_LIFCR_CTEIF2_Msk (0x1UL << DMA_LIFCR_CTEIF2_Pos)
6227#define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
6228#define DMA_LIFCR_CDMEIF2_Pos (18U)
6229#define DMA_LIFCR_CDMEIF2_Msk (0x1UL << DMA_LIFCR_CDMEIF2_Pos)
6230#define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
6231#define DMA_LIFCR_CFEIF2_Pos (16U)
6232#define DMA_LIFCR_CFEIF2_Msk (0x1UL << DMA_LIFCR_CFEIF2_Pos)
6233#define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
6234#define DMA_LIFCR_CTCIF1_Pos (11U)
6235#define DMA_LIFCR_CTCIF1_Msk (0x1UL << DMA_LIFCR_CTCIF1_Pos)
6236#define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
6237#define DMA_LIFCR_CHTIF1_Pos (10U)
6238#define DMA_LIFCR_CHTIF1_Msk (0x1UL << DMA_LIFCR_CHTIF1_Pos)
6239#define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
6240#define DMA_LIFCR_CTEIF1_Pos (9U)
6241#define DMA_LIFCR_CTEIF1_Msk (0x1UL << DMA_LIFCR_CTEIF1_Pos)
6242#define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
6243#define DMA_LIFCR_CDMEIF1_Pos (8U)
6244#define DMA_LIFCR_CDMEIF1_Msk (0x1UL << DMA_LIFCR_CDMEIF1_Pos)
6245#define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
6246#define DMA_LIFCR_CFEIF1_Pos (6U)
6247#define DMA_LIFCR_CFEIF1_Msk (0x1UL << DMA_LIFCR_CFEIF1_Pos)
6248#define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
6249#define DMA_LIFCR_CTCIF0_Pos (5U)
6250#define DMA_LIFCR_CTCIF0_Msk (0x1UL << DMA_LIFCR_CTCIF0_Pos)
6251#define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
6252#define DMA_LIFCR_CHTIF0_Pos (4U)
6253#define DMA_LIFCR_CHTIF0_Msk (0x1UL << DMA_LIFCR_CHTIF0_Pos)
6254#define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
6255#define DMA_LIFCR_CTEIF0_Pos (3U)
6256#define DMA_LIFCR_CTEIF0_Msk (0x1UL << DMA_LIFCR_CTEIF0_Pos)
6257#define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
6258#define DMA_LIFCR_CDMEIF0_Pos (2U)
6259#define DMA_LIFCR_CDMEIF0_Msk (0x1UL << DMA_LIFCR_CDMEIF0_Pos)
6260#define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
6261#define DMA_LIFCR_CFEIF0_Pos (0U)
6262#define DMA_LIFCR_CFEIF0_Msk (0x1UL << DMA_LIFCR_CFEIF0_Pos)
6263#define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
6264
6265/******************** Bits definition for DMA_HIFCR register ****************/
6266#define DMA_HIFCR_CTCIF7_Pos (27U)
6267#define DMA_HIFCR_CTCIF7_Msk (0x1UL << DMA_HIFCR_CTCIF7_Pos)
6268#define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
6269#define DMA_HIFCR_CHTIF7_Pos (26U)
6270#define DMA_HIFCR_CHTIF7_Msk (0x1UL << DMA_HIFCR_CHTIF7_Pos)
6271#define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
6272#define DMA_HIFCR_CTEIF7_Pos (25U)
6273#define DMA_HIFCR_CTEIF7_Msk (0x1UL << DMA_HIFCR_CTEIF7_Pos)
6274#define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
6275#define DMA_HIFCR_CDMEIF7_Pos (24U)
6276#define DMA_HIFCR_CDMEIF7_Msk (0x1UL << DMA_HIFCR_CDMEIF7_Pos)
6277#define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
6278#define DMA_HIFCR_CFEIF7_Pos (22U)
6279#define DMA_HIFCR_CFEIF7_Msk (0x1UL << DMA_HIFCR_CFEIF7_Pos)
6280#define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
6281#define DMA_HIFCR_CTCIF6_Pos (21U)
6282#define DMA_HIFCR_CTCIF6_Msk (0x1UL << DMA_HIFCR_CTCIF6_Pos)
6283#define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
6284#define DMA_HIFCR_CHTIF6_Pos (20U)
6285#define DMA_HIFCR_CHTIF6_Msk (0x1UL << DMA_HIFCR_CHTIF6_Pos)
6286#define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
6287#define DMA_HIFCR_CTEIF6_Pos (19U)
6288#define DMA_HIFCR_CTEIF6_Msk (0x1UL << DMA_HIFCR_CTEIF6_Pos)
6289#define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
6290#define DMA_HIFCR_CDMEIF6_Pos (18U)
6291#define DMA_HIFCR_CDMEIF6_Msk (0x1UL << DMA_HIFCR_CDMEIF6_Pos)
6292#define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
6293#define DMA_HIFCR_CFEIF6_Pos (16U)
6294#define DMA_HIFCR_CFEIF6_Msk (0x1UL << DMA_HIFCR_CFEIF6_Pos)
6295#define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
6296#define DMA_HIFCR_CTCIF5_Pos (11U)
6297#define DMA_HIFCR_CTCIF5_Msk (0x1UL << DMA_HIFCR_CTCIF5_Pos)
6298#define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
6299#define DMA_HIFCR_CHTIF5_Pos (10U)
6300#define DMA_HIFCR_CHTIF5_Msk (0x1UL << DMA_HIFCR_CHTIF5_Pos)
6301#define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
6302#define DMA_HIFCR_CTEIF5_Pos (9U)
6303#define DMA_HIFCR_CTEIF5_Msk (0x1UL << DMA_HIFCR_CTEIF5_Pos)
6304#define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
6305#define DMA_HIFCR_CDMEIF5_Pos (8U)
6306#define DMA_HIFCR_CDMEIF5_Msk (0x1UL << DMA_HIFCR_CDMEIF5_Pos)
6307#define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
6308#define DMA_HIFCR_CFEIF5_Pos (6U)
6309#define DMA_HIFCR_CFEIF5_Msk (0x1UL << DMA_HIFCR_CFEIF5_Pos)
6310#define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
6311#define DMA_HIFCR_CTCIF4_Pos (5U)
6312#define DMA_HIFCR_CTCIF4_Msk (0x1UL << DMA_HIFCR_CTCIF4_Pos)
6313#define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
6314#define DMA_HIFCR_CHTIF4_Pos (4U)
6315#define DMA_HIFCR_CHTIF4_Msk (0x1UL << DMA_HIFCR_CHTIF4_Pos)
6316#define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
6317#define DMA_HIFCR_CTEIF4_Pos (3U)
6318#define DMA_HIFCR_CTEIF4_Msk (0x1UL << DMA_HIFCR_CTEIF4_Pos)
6319#define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
6320#define DMA_HIFCR_CDMEIF4_Pos (2U)
6321#define DMA_HIFCR_CDMEIF4_Msk (0x1UL << DMA_HIFCR_CDMEIF4_Pos)
6322#define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
6323#define DMA_HIFCR_CFEIF4_Pos (0U)
6324#define DMA_HIFCR_CFEIF4_Msk (0x1UL << DMA_HIFCR_CFEIF4_Pos)
6325#define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
6326
6327/****************** Bit definition for DMA_SxPAR register ********************/
6328#define DMA_SxPAR_PA_Pos (0U)
6329#define DMA_SxPAR_PA_Msk (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos)
6330#define DMA_SxPAR_PA DMA_SxPAR_PA_Msk
6331
6332/****************** Bit definition for DMA_SxM0AR register ********************/
6333#define DMA_SxM0AR_M0A_Pos (0U)
6334#define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos)
6335#define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk
6336
6337/****************** Bit definition for DMA_SxM1AR register ********************/
6338#define DMA_SxM1AR_M1A_Pos (0U)
6339#define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos)
6340#define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk
6341
6342
6343/******************************************************************************/
6344/* */
6345/* AHB Master DMA2D Controller (DMA2D) */
6346/* */
6347/******************************************************************************/
6348
6349/******************** Bit definition for DMA2D_CR register ******************/
6350
6351#define DMA2D_CR_START_Pos (0U)
6352#define DMA2D_CR_START_Msk (0x1UL << DMA2D_CR_START_Pos)
6353#define DMA2D_CR_START DMA2D_CR_START_Msk
6354#define DMA2D_CR_SUSP_Pos (1U)
6355#define DMA2D_CR_SUSP_Msk (0x1UL << DMA2D_CR_SUSP_Pos)
6356#define DMA2D_CR_SUSP DMA2D_CR_SUSP_Msk
6357#define DMA2D_CR_ABORT_Pos (2U)
6358#define DMA2D_CR_ABORT_Msk (0x1UL << DMA2D_CR_ABORT_Pos)
6359#define DMA2D_CR_ABORT DMA2D_CR_ABORT_Msk
6360#define DMA2D_CR_TEIE_Pos (8U)
6361#define DMA2D_CR_TEIE_Msk (0x1UL << DMA2D_CR_TEIE_Pos)
6362#define DMA2D_CR_TEIE DMA2D_CR_TEIE_Msk
6363#define DMA2D_CR_TCIE_Pos (9U)
6364#define DMA2D_CR_TCIE_Msk (0x1UL << DMA2D_CR_TCIE_Pos)
6365#define DMA2D_CR_TCIE DMA2D_CR_TCIE_Msk
6366#define DMA2D_CR_TWIE_Pos (10U)
6367#define DMA2D_CR_TWIE_Msk (0x1UL << DMA2D_CR_TWIE_Pos)
6368#define DMA2D_CR_TWIE DMA2D_CR_TWIE_Msk
6369#define DMA2D_CR_CAEIE_Pos (11U)
6370#define DMA2D_CR_CAEIE_Msk (0x1UL << DMA2D_CR_CAEIE_Pos)
6371#define DMA2D_CR_CAEIE DMA2D_CR_CAEIE_Msk
6372#define DMA2D_CR_CTCIE_Pos (12U)
6373#define DMA2D_CR_CTCIE_Msk (0x1UL << DMA2D_CR_CTCIE_Pos)
6374#define DMA2D_CR_CTCIE DMA2D_CR_CTCIE_Msk
6375#define DMA2D_CR_CEIE_Pos (13U)
6376#define DMA2D_CR_CEIE_Msk (0x1UL << DMA2D_CR_CEIE_Pos)
6377#define DMA2D_CR_CEIE DMA2D_CR_CEIE_Msk
6378#define DMA2D_CR_MODE_Pos (16U)
6379#define DMA2D_CR_MODE_Msk (0x3UL << DMA2D_CR_MODE_Pos)
6380#define DMA2D_CR_MODE DMA2D_CR_MODE_Msk
6381#define DMA2D_CR_MODE_0 (0x1UL << DMA2D_CR_MODE_Pos)
6382#define DMA2D_CR_MODE_1 (0x2UL << DMA2D_CR_MODE_Pos)
6383
6384/******************** Bit definition for DMA2D_ISR register *****************/
6385
6386#define DMA2D_ISR_TEIF_Pos (0U)
6387#define DMA2D_ISR_TEIF_Msk (0x1UL << DMA2D_ISR_TEIF_Pos)
6388#define DMA2D_ISR_TEIF DMA2D_ISR_TEIF_Msk
6389#define DMA2D_ISR_TCIF_Pos (1U)
6390#define DMA2D_ISR_TCIF_Msk (0x1UL << DMA2D_ISR_TCIF_Pos)
6391#define DMA2D_ISR_TCIF DMA2D_ISR_TCIF_Msk
6392#define DMA2D_ISR_TWIF_Pos (2U)
6393#define DMA2D_ISR_TWIF_Msk (0x1UL << DMA2D_ISR_TWIF_Pos)
6394#define DMA2D_ISR_TWIF DMA2D_ISR_TWIF_Msk
6395#define DMA2D_ISR_CAEIF_Pos (3U)
6396#define DMA2D_ISR_CAEIF_Msk (0x1UL << DMA2D_ISR_CAEIF_Pos)
6397#define DMA2D_ISR_CAEIF DMA2D_ISR_CAEIF_Msk
6398#define DMA2D_ISR_CTCIF_Pos (4U)
6399#define DMA2D_ISR_CTCIF_Msk (0x1UL << DMA2D_ISR_CTCIF_Pos)
6400#define DMA2D_ISR_CTCIF DMA2D_ISR_CTCIF_Msk
6401#define DMA2D_ISR_CEIF_Pos (5U)
6402#define DMA2D_ISR_CEIF_Msk (0x1UL << DMA2D_ISR_CEIF_Pos)
6403#define DMA2D_ISR_CEIF DMA2D_ISR_CEIF_Msk
6404
6405/******************** Bit definition for DMA2D_IFCR register ****************/
6406
6407#define DMA2D_IFCR_CTEIF_Pos (0U)
6408#define DMA2D_IFCR_CTEIF_Msk (0x1UL << DMA2D_IFCR_CTEIF_Pos)
6409#define DMA2D_IFCR_CTEIF DMA2D_IFCR_CTEIF_Msk
6410#define DMA2D_IFCR_CTCIF_Pos (1U)
6411#define DMA2D_IFCR_CTCIF_Msk (0x1UL << DMA2D_IFCR_CTCIF_Pos)
6412#define DMA2D_IFCR_CTCIF DMA2D_IFCR_CTCIF_Msk
6413#define DMA2D_IFCR_CTWIF_Pos (2U)
6414#define DMA2D_IFCR_CTWIF_Msk (0x1UL << DMA2D_IFCR_CTWIF_Pos)
6415#define DMA2D_IFCR_CTWIF DMA2D_IFCR_CTWIF_Msk
6416#define DMA2D_IFCR_CAECIF_Pos (3U)
6417#define DMA2D_IFCR_CAECIF_Msk (0x1UL << DMA2D_IFCR_CAECIF_Pos)
6418#define DMA2D_IFCR_CAECIF DMA2D_IFCR_CAECIF_Msk
6419#define DMA2D_IFCR_CCTCIF_Pos (4U)
6420#define DMA2D_IFCR_CCTCIF_Msk (0x1UL << DMA2D_IFCR_CCTCIF_Pos)
6421#define DMA2D_IFCR_CCTCIF DMA2D_IFCR_CCTCIF_Msk
6422#define DMA2D_IFCR_CCEIF_Pos (5U)
6423#define DMA2D_IFCR_CCEIF_Msk (0x1UL << DMA2D_IFCR_CCEIF_Pos)
6424#define DMA2D_IFCR_CCEIF DMA2D_IFCR_CCEIF_Msk
6425
6426/* Legacy defines */
6427#define DMA2D_IFSR_CTEIF DMA2D_IFCR_CTEIF
6428#define DMA2D_IFSR_CTCIF DMA2D_IFCR_CTCIF
6429#define DMA2D_IFSR_CTWIF DMA2D_IFCR_CTWIF
6430#define DMA2D_IFSR_CCAEIF DMA2D_IFCR_CAECIF
6431#define DMA2D_IFSR_CCTCIF DMA2D_IFCR_CCTCIF
6432#define DMA2D_IFSR_CCEIF DMA2D_IFCR_CCEIF
6433
6434/******************** Bit definition for DMA2D_FGMAR register ***************/
6435
6436#define DMA2D_FGMAR_MA_Pos (0U)
6437#define DMA2D_FGMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_FGMAR_MA_Pos)
6438#define DMA2D_FGMAR_MA DMA2D_FGMAR_MA_Msk
6439
6440/******************** Bit definition for DMA2D_FGOR register ****************/
6441
6442#define DMA2D_FGOR_LO_Pos (0U)
6443#define DMA2D_FGOR_LO_Msk (0x3FFFUL << DMA2D_FGOR_LO_Pos)
6444#define DMA2D_FGOR_LO DMA2D_FGOR_LO_Msk
6445
6446/******************** Bit definition for DMA2D_BGMAR register ***************/
6447
6448#define DMA2D_BGMAR_MA_Pos (0U)
6449#define DMA2D_BGMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_BGMAR_MA_Pos)
6450#define DMA2D_BGMAR_MA DMA2D_BGMAR_MA_Msk
6451
6452/******************** Bit definition for DMA2D_BGOR register ****************/
6453
6454#define DMA2D_BGOR_LO_Pos (0U)
6455#define DMA2D_BGOR_LO_Msk (0x3FFFUL << DMA2D_BGOR_LO_Pos)
6456#define DMA2D_BGOR_LO DMA2D_BGOR_LO_Msk
6457
6458/******************** Bit definition for DMA2D_FGPFCCR register *************/
6459
6460#define DMA2D_FGPFCCR_CM_Pos (0U)
6461#define DMA2D_FGPFCCR_CM_Msk (0xFUL << DMA2D_FGPFCCR_CM_Pos)
6462#define DMA2D_FGPFCCR_CM DMA2D_FGPFCCR_CM_Msk
6463#define DMA2D_FGPFCCR_CM_0 (0x1UL << DMA2D_FGPFCCR_CM_Pos)
6464#define DMA2D_FGPFCCR_CM_1 (0x2UL << DMA2D_FGPFCCR_CM_Pos)
6465#define DMA2D_FGPFCCR_CM_2 (0x4UL << DMA2D_FGPFCCR_CM_Pos)
6466#define DMA2D_FGPFCCR_CM_3 (0x8UL << DMA2D_FGPFCCR_CM_Pos)
6467#define DMA2D_FGPFCCR_CCM_Pos (4U)
6468#define DMA2D_FGPFCCR_CCM_Msk (0x1UL << DMA2D_FGPFCCR_CCM_Pos)
6469#define DMA2D_FGPFCCR_CCM DMA2D_FGPFCCR_CCM_Msk
6470#define DMA2D_FGPFCCR_START_Pos (5U)
6471#define DMA2D_FGPFCCR_START_Msk (0x1UL << DMA2D_FGPFCCR_START_Pos)
6472#define DMA2D_FGPFCCR_START DMA2D_FGPFCCR_START_Msk
6473#define DMA2D_FGPFCCR_CS_Pos (8U)
6474#define DMA2D_FGPFCCR_CS_Msk (0xFFUL << DMA2D_FGPFCCR_CS_Pos)
6475#define DMA2D_FGPFCCR_CS DMA2D_FGPFCCR_CS_Msk
6476#define DMA2D_FGPFCCR_AM_Pos (16U)
6477#define DMA2D_FGPFCCR_AM_Msk (0x3UL << DMA2D_FGPFCCR_AM_Pos)
6478#define DMA2D_FGPFCCR_AM DMA2D_FGPFCCR_AM_Msk
6479#define DMA2D_FGPFCCR_AM_0 (0x1UL << DMA2D_FGPFCCR_AM_Pos)
6480#define DMA2D_FGPFCCR_AM_1 (0x2UL << DMA2D_FGPFCCR_AM_Pos)
6481#define DMA2D_FGPFCCR_ALPHA_Pos (24U)
6482#define DMA2D_FGPFCCR_ALPHA_Msk (0xFFUL << DMA2D_FGPFCCR_ALPHA_Pos)
6483#define DMA2D_FGPFCCR_ALPHA DMA2D_FGPFCCR_ALPHA_Msk
6484
6485/******************** Bit definition for DMA2D_FGCOLR register **************/
6486
6487#define DMA2D_FGCOLR_BLUE_Pos (0U)
6488#define DMA2D_FGCOLR_BLUE_Msk (0xFFUL << DMA2D_FGCOLR_BLUE_Pos)
6489#define DMA2D_FGCOLR_BLUE DMA2D_FGCOLR_BLUE_Msk
6490#define DMA2D_FGCOLR_GREEN_Pos (8U)
6491#define DMA2D_FGCOLR_GREEN_Msk (0xFFUL << DMA2D_FGCOLR_GREEN_Pos)
6492#define DMA2D_FGCOLR_GREEN DMA2D_FGCOLR_GREEN_Msk
6493#define DMA2D_FGCOLR_RED_Pos (16U)
6494#define DMA2D_FGCOLR_RED_Msk (0xFFUL << DMA2D_FGCOLR_RED_Pos)
6495#define DMA2D_FGCOLR_RED DMA2D_FGCOLR_RED_Msk
6496
6497/******************** Bit definition for DMA2D_BGPFCCR register *************/
6498
6499#define DMA2D_BGPFCCR_CM_Pos (0U)
6500#define DMA2D_BGPFCCR_CM_Msk (0xFUL << DMA2D_BGPFCCR_CM_Pos)
6501#define DMA2D_BGPFCCR_CM DMA2D_BGPFCCR_CM_Msk
6502#define DMA2D_BGPFCCR_CM_0 (0x1UL << DMA2D_BGPFCCR_CM_Pos)
6503#define DMA2D_BGPFCCR_CM_1 (0x2UL << DMA2D_BGPFCCR_CM_Pos)
6504#define DMA2D_BGPFCCR_CM_2 (0x4UL << DMA2D_BGPFCCR_CM_Pos)
6505#define DMA2D_BGPFCCR_CM_3 0x00000008U
6506#define DMA2D_BGPFCCR_CCM_Pos (4U)
6507#define DMA2D_BGPFCCR_CCM_Msk (0x1UL << DMA2D_BGPFCCR_CCM_Pos)
6508#define DMA2D_BGPFCCR_CCM DMA2D_BGPFCCR_CCM_Msk
6509#define DMA2D_BGPFCCR_START_Pos (5U)
6510#define DMA2D_BGPFCCR_START_Msk (0x1UL << DMA2D_BGPFCCR_START_Pos)
6511#define DMA2D_BGPFCCR_START DMA2D_BGPFCCR_START_Msk
6512#define DMA2D_BGPFCCR_CS_Pos (8U)
6513#define DMA2D_BGPFCCR_CS_Msk (0xFFUL << DMA2D_BGPFCCR_CS_Pos)
6514#define DMA2D_BGPFCCR_CS DMA2D_BGPFCCR_CS_Msk
6515#define DMA2D_BGPFCCR_AM_Pos (16U)
6516#define DMA2D_BGPFCCR_AM_Msk (0x3UL << DMA2D_BGPFCCR_AM_Pos)
6517#define DMA2D_BGPFCCR_AM DMA2D_BGPFCCR_AM_Msk
6518#define DMA2D_BGPFCCR_AM_0 (0x1UL << DMA2D_BGPFCCR_AM_Pos)
6519#define DMA2D_BGPFCCR_AM_1 (0x2UL << DMA2D_BGPFCCR_AM_Pos)
6520#define DMA2D_BGPFCCR_ALPHA_Pos (24U)
6521#define DMA2D_BGPFCCR_ALPHA_Msk (0xFFUL << DMA2D_BGPFCCR_ALPHA_Pos)
6522#define DMA2D_BGPFCCR_ALPHA DMA2D_BGPFCCR_ALPHA_Msk
6523
6524/******************** Bit definition for DMA2D_BGCOLR register **************/
6525
6526#define DMA2D_BGCOLR_BLUE_Pos (0U)
6527#define DMA2D_BGCOLR_BLUE_Msk (0xFFUL << DMA2D_BGCOLR_BLUE_Pos)
6528#define DMA2D_BGCOLR_BLUE DMA2D_BGCOLR_BLUE_Msk
6529#define DMA2D_BGCOLR_GREEN_Pos (8U)
6530#define DMA2D_BGCOLR_GREEN_Msk (0xFFUL << DMA2D_BGCOLR_GREEN_Pos)
6531#define DMA2D_BGCOLR_GREEN DMA2D_BGCOLR_GREEN_Msk
6532#define DMA2D_BGCOLR_RED_Pos (16U)
6533#define DMA2D_BGCOLR_RED_Msk (0xFFUL << DMA2D_BGCOLR_RED_Pos)
6534#define DMA2D_BGCOLR_RED DMA2D_BGCOLR_RED_Msk
6535
6536/******************** Bit definition for DMA2D_FGCMAR register **************/
6537
6538#define DMA2D_FGCMAR_MA_Pos (0U)
6539#define DMA2D_FGCMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_FGCMAR_MA_Pos)
6540#define DMA2D_FGCMAR_MA DMA2D_FGCMAR_MA_Msk
6541
6542/******************** Bit definition for DMA2D_BGCMAR register **************/
6543
6544#define DMA2D_BGCMAR_MA_Pos (0U)
6545#define DMA2D_BGCMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_BGCMAR_MA_Pos)
6546#define DMA2D_BGCMAR_MA DMA2D_BGCMAR_MA_Msk
6547
6548/******************** Bit definition for DMA2D_OPFCCR register **************/
6549
6550#define DMA2D_OPFCCR_CM_Pos (0U)
6551#define DMA2D_OPFCCR_CM_Msk (0x7UL << DMA2D_OPFCCR_CM_Pos)
6552#define DMA2D_OPFCCR_CM DMA2D_OPFCCR_CM_Msk
6553#define DMA2D_OPFCCR_CM_0 (0x1UL << DMA2D_OPFCCR_CM_Pos)
6554#define DMA2D_OPFCCR_CM_1 (0x2UL << DMA2D_OPFCCR_CM_Pos)
6555#define DMA2D_OPFCCR_CM_2 (0x4UL << DMA2D_OPFCCR_CM_Pos)
6556
6557/******************** Bit definition for DMA2D_OCOLR register ***************/
6558
6560
6561#define DMA2D_OCOLR_BLUE_1 0x000000FFU
6562#define DMA2D_OCOLR_GREEN_1 0x0000FF00U
6563#define DMA2D_OCOLR_RED_1 0x00FF0000U
6564#define DMA2D_OCOLR_ALPHA_1 0xFF000000U
6565
6567#define DMA2D_OCOLR_BLUE_2 0x0000001FU
6568#define DMA2D_OCOLR_GREEN_2 0x000007E0U
6569#define DMA2D_OCOLR_RED_2 0x0000F800U
6570
6572#define DMA2D_OCOLR_BLUE_3 0x0000001FU
6573#define DMA2D_OCOLR_GREEN_3 0x000003E0U
6574#define DMA2D_OCOLR_RED_3 0x00007C00U
6575#define DMA2D_OCOLR_ALPHA_3 0x00008000U
6576
6578#define DMA2D_OCOLR_BLUE_4 0x0000000FU
6579#define DMA2D_OCOLR_GREEN_4 0x000000F0U
6580#define DMA2D_OCOLR_RED_4 0x00000F00U
6581#define DMA2D_OCOLR_ALPHA_4 0x0000F000U
6582
6583/******************** Bit definition for DMA2D_OMAR register ****************/
6584
6585#define DMA2D_OMAR_MA_Pos (0U)
6586#define DMA2D_OMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_OMAR_MA_Pos)
6587#define DMA2D_OMAR_MA DMA2D_OMAR_MA_Msk
6588
6589/******************** Bit definition for DMA2D_OOR register *****************/
6590
6591#define DMA2D_OOR_LO_Pos (0U)
6592#define DMA2D_OOR_LO_Msk (0x3FFFUL << DMA2D_OOR_LO_Pos)
6593#define DMA2D_OOR_LO DMA2D_OOR_LO_Msk
6594
6595/******************** Bit definition for DMA2D_NLR register *****************/
6596
6597#define DMA2D_NLR_NL_Pos (0U)
6598#define DMA2D_NLR_NL_Msk (0xFFFFUL << DMA2D_NLR_NL_Pos)
6599#define DMA2D_NLR_NL DMA2D_NLR_NL_Msk
6600#define DMA2D_NLR_PL_Pos (16U)
6601#define DMA2D_NLR_PL_Msk (0x3FFFUL << DMA2D_NLR_PL_Pos)
6602#define DMA2D_NLR_PL DMA2D_NLR_PL_Msk
6603
6604/******************** Bit definition for DMA2D_LWR register *****************/
6605
6606#define DMA2D_LWR_LW_Pos (0U)
6607#define DMA2D_LWR_LW_Msk (0xFFFFUL << DMA2D_LWR_LW_Pos)
6608#define DMA2D_LWR_LW DMA2D_LWR_LW_Msk
6609
6610/******************** Bit definition for DMA2D_AMTCR register ***************/
6611
6612#define DMA2D_AMTCR_EN_Pos (0U)
6613#define DMA2D_AMTCR_EN_Msk (0x1UL << DMA2D_AMTCR_EN_Pos)
6614#define DMA2D_AMTCR_EN DMA2D_AMTCR_EN_Msk
6615#define DMA2D_AMTCR_DT_Pos (8U)
6616#define DMA2D_AMTCR_DT_Msk (0xFFUL << DMA2D_AMTCR_DT_Pos)
6617#define DMA2D_AMTCR_DT DMA2D_AMTCR_DT_Msk
6618
6619/******************** Bit definition for DMA2D_FGCLUT register **************/
6620
6621/******************** Bit definition for DMA2D_BGCLUT register **************/
6622
6623
6624/******************************************************************************/
6625/* */
6626/* External Interrupt/Event Controller */
6627/* */
6628/******************************************************************************/
6629/******************* Bit definition for EXTI_IMR register *******************/
6630#define EXTI_IMR_MR0_Pos (0U)
6631#define EXTI_IMR_MR0_Msk (0x1UL << EXTI_IMR_MR0_Pos)
6632#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk
6633#define EXTI_IMR_MR1_Pos (1U)
6634#define EXTI_IMR_MR1_Msk (0x1UL << EXTI_IMR_MR1_Pos)
6635#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk
6636#define EXTI_IMR_MR2_Pos (2U)
6637#define EXTI_IMR_MR2_Msk (0x1UL << EXTI_IMR_MR2_Pos)
6638#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk
6639#define EXTI_IMR_MR3_Pos (3U)
6640#define EXTI_IMR_MR3_Msk (0x1UL << EXTI_IMR_MR3_Pos)
6641#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk
6642#define EXTI_IMR_MR4_Pos (4U)
6643#define EXTI_IMR_MR4_Msk (0x1UL << EXTI_IMR_MR4_Pos)
6644#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk
6645#define EXTI_IMR_MR5_Pos (5U)
6646#define EXTI_IMR_MR5_Msk (0x1UL << EXTI_IMR_MR5_Pos)
6647#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk
6648#define EXTI_IMR_MR6_Pos (6U)
6649#define EXTI_IMR_MR6_Msk (0x1UL << EXTI_IMR_MR6_Pos)
6650#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk
6651#define EXTI_IMR_MR7_Pos (7U)
6652#define EXTI_IMR_MR7_Msk (0x1UL << EXTI_IMR_MR7_Pos)
6653#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk
6654#define EXTI_IMR_MR8_Pos (8U)
6655#define EXTI_IMR_MR8_Msk (0x1UL << EXTI_IMR_MR8_Pos)
6656#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk
6657#define EXTI_IMR_MR9_Pos (9U)
6658#define EXTI_IMR_MR9_Msk (0x1UL << EXTI_IMR_MR9_Pos)
6659#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk
6660#define EXTI_IMR_MR10_Pos (10U)
6661#define EXTI_IMR_MR10_Msk (0x1UL << EXTI_IMR_MR10_Pos)
6662#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk
6663#define EXTI_IMR_MR11_Pos (11U)
6664#define EXTI_IMR_MR11_Msk (0x1UL << EXTI_IMR_MR11_Pos)
6665#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk
6666#define EXTI_IMR_MR12_Pos (12U)
6667#define EXTI_IMR_MR12_Msk (0x1UL << EXTI_IMR_MR12_Pos)
6668#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk
6669#define EXTI_IMR_MR13_Pos (13U)
6670#define EXTI_IMR_MR13_Msk (0x1UL << EXTI_IMR_MR13_Pos)
6671#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk
6672#define EXTI_IMR_MR14_Pos (14U)
6673#define EXTI_IMR_MR14_Msk (0x1UL << EXTI_IMR_MR14_Pos)
6674#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk
6675#define EXTI_IMR_MR15_Pos (15U)
6676#define EXTI_IMR_MR15_Msk (0x1UL << EXTI_IMR_MR15_Pos)
6677#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk
6678#define EXTI_IMR_MR16_Pos (16U)
6679#define EXTI_IMR_MR16_Msk (0x1UL << EXTI_IMR_MR16_Pos)
6680#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk
6681#define EXTI_IMR_MR17_Pos (17U)
6682#define EXTI_IMR_MR17_Msk (0x1UL << EXTI_IMR_MR17_Pos)
6683#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk
6684#define EXTI_IMR_MR18_Pos (18U)
6685#define EXTI_IMR_MR18_Msk (0x1UL << EXTI_IMR_MR18_Pos)
6686#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk
6687#define EXTI_IMR_MR19_Pos (19U)
6688#define EXTI_IMR_MR19_Msk (0x1UL << EXTI_IMR_MR19_Pos)
6689#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk
6690#define EXTI_IMR_MR20_Pos (20U)
6691#define EXTI_IMR_MR20_Msk (0x1UL << EXTI_IMR_MR20_Pos)
6692#define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk
6693#define EXTI_IMR_MR21_Pos (21U)
6694#define EXTI_IMR_MR21_Msk (0x1UL << EXTI_IMR_MR21_Pos)
6695#define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk
6696#define EXTI_IMR_MR22_Pos (22U)
6697#define EXTI_IMR_MR22_Msk (0x1UL << EXTI_IMR_MR22_Pos)
6698#define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk
6699
6700/* Reference Defines */
6701#define EXTI_IMR_IM0 EXTI_IMR_MR0
6702#define EXTI_IMR_IM1 EXTI_IMR_MR1
6703#define EXTI_IMR_IM2 EXTI_IMR_MR2
6704#define EXTI_IMR_IM3 EXTI_IMR_MR3
6705#define EXTI_IMR_IM4 EXTI_IMR_MR4
6706#define EXTI_IMR_IM5 EXTI_IMR_MR5
6707#define EXTI_IMR_IM6 EXTI_IMR_MR6
6708#define EXTI_IMR_IM7 EXTI_IMR_MR7
6709#define EXTI_IMR_IM8 EXTI_IMR_MR8
6710#define EXTI_IMR_IM9 EXTI_IMR_MR9
6711#define EXTI_IMR_IM10 EXTI_IMR_MR10
6712#define EXTI_IMR_IM11 EXTI_IMR_MR11
6713#define EXTI_IMR_IM12 EXTI_IMR_MR12
6714#define EXTI_IMR_IM13 EXTI_IMR_MR13
6715#define EXTI_IMR_IM14 EXTI_IMR_MR14
6716#define EXTI_IMR_IM15 EXTI_IMR_MR15
6717#define EXTI_IMR_IM16 EXTI_IMR_MR16
6718#define EXTI_IMR_IM17 EXTI_IMR_MR17
6719#define EXTI_IMR_IM18 EXTI_IMR_MR18
6720#define EXTI_IMR_IM19 EXTI_IMR_MR19
6721#define EXTI_IMR_IM20 EXTI_IMR_MR20
6722#define EXTI_IMR_IM21 EXTI_IMR_MR21
6723#define EXTI_IMR_IM22 EXTI_IMR_MR22
6724#define EXTI_IMR_IM_Pos (0U)
6725#define EXTI_IMR_IM_Msk (0x7FFFFFUL << EXTI_IMR_IM_Pos)
6726#define EXTI_IMR_IM EXTI_IMR_IM_Msk
6727
6728/******************* Bit definition for EXTI_EMR register *******************/
6729#define EXTI_EMR_MR0_Pos (0U)
6730#define EXTI_EMR_MR0_Msk (0x1UL << EXTI_EMR_MR0_Pos)
6731#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk
6732#define EXTI_EMR_MR1_Pos (1U)
6733#define EXTI_EMR_MR1_Msk (0x1UL << EXTI_EMR_MR1_Pos)
6734#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk
6735#define EXTI_EMR_MR2_Pos (2U)
6736#define EXTI_EMR_MR2_Msk (0x1UL << EXTI_EMR_MR2_Pos)
6737#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk
6738#define EXTI_EMR_MR3_Pos (3U)
6739#define EXTI_EMR_MR3_Msk (0x1UL << EXTI_EMR_MR3_Pos)
6740#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk
6741#define EXTI_EMR_MR4_Pos (4U)
6742#define EXTI_EMR_MR4_Msk (0x1UL << EXTI_EMR_MR4_Pos)
6743#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk
6744#define EXTI_EMR_MR5_Pos (5U)
6745#define EXTI_EMR_MR5_Msk (0x1UL << EXTI_EMR_MR5_Pos)
6746#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk
6747#define EXTI_EMR_MR6_Pos (6U)
6748#define EXTI_EMR_MR6_Msk (0x1UL << EXTI_EMR_MR6_Pos)
6749#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk
6750#define EXTI_EMR_MR7_Pos (7U)
6751#define EXTI_EMR_MR7_Msk (0x1UL << EXTI_EMR_MR7_Pos)
6752#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk
6753#define EXTI_EMR_MR8_Pos (8U)
6754#define EXTI_EMR_MR8_Msk (0x1UL << EXTI_EMR_MR8_Pos)
6755#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk
6756#define EXTI_EMR_MR9_Pos (9U)
6757#define EXTI_EMR_MR9_Msk (0x1UL << EXTI_EMR_MR9_Pos)
6758#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk
6759#define EXTI_EMR_MR10_Pos (10U)
6760#define EXTI_EMR_MR10_Msk (0x1UL << EXTI_EMR_MR10_Pos)
6761#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk
6762#define EXTI_EMR_MR11_Pos (11U)
6763#define EXTI_EMR_MR11_Msk (0x1UL << EXTI_EMR_MR11_Pos)
6764#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk
6765#define EXTI_EMR_MR12_Pos (12U)
6766#define EXTI_EMR_MR12_Msk (0x1UL << EXTI_EMR_MR12_Pos)
6767#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk
6768#define EXTI_EMR_MR13_Pos (13U)
6769#define EXTI_EMR_MR13_Msk (0x1UL << EXTI_EMR_MR13_Pos)
6770#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk
6771#define EXTI_EMR_MR14_Pos (14U)
6772#define EXTI_EMR_MR14_Msk (0x1UL << EXTI_EMR_MR14_Pos)
6773#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk
6774#define EXTI_EMR_MR15_Pos (15U)
6775#define EXTI_EMR_MR15_Msk (0x1UL << EXTI_EMR_MR15_Pos)
6776#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk
6777#define EXTI_EMR_MR16_Pos (16U)
6778#define EXTI_EMR_MR16_Msk (0x1UL << EXTI_EMR_MR16_Pos)
6779#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk
6780#define EXTI_EMR_MR17_Pos (17U)
6781#define EXTI_EMR_MR17_Msk (0x1UL << EXTI_EMR_MR17_Pos)
6782#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk
6783#define EXTI_EMR_MR18_Pos (18U)
6784#define EXTI_EMR_MR18_Msk (0x1UL << EXTI_EMR_MR18_Pos)
6785#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk
6786#define EXTI_EMR_MR19_Pos (19U)
6787#define EXTI_EMR_MR19_Msk (0x1UL << EXTI_EMR_MR19_Pos)
6788#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk
6789#define EXTI_EMR_MR20_Pos (20U)
6790#define EXTI_EMR_MR20_Msk (0x1UL << EXTI_EMR_MR20_Pos)
6791#define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk
6792#define EXTI_EMR_MR21_Pos (21U)
6793#define EXTI_EMR_MR21_Msk (0x1UL << EXTI_EMR_MR21_Pos)
6794#define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk
6795#define EXTI_EMR_MR22_Pos (22U)
6796#define EXTI_EMR_MR22_Msk (0x1UL << EXTI_EMR_MR22_Pos)
6797#define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk
6798
6799/* Reference Defines */
6800#define EXTI_EMR_EM0 EXTI_EMR_MR0
6801#define EXTI_EMR_EM1 EXTI_EMR_MR1
6802#define EXTI_EMR_EM2 EXTI_EMR_MR2
6803#define EXTI_EMR_EM3 EXTI_EMR_MR3
6804#define EXTI_EMR_EM4 EXTI_EMR_MR4
6805#define EXTI_EMR_EM5 EXTI_EMR_MR5
6806#define EXTI_EMR_EM6 EXTI_EMR_MR6
6807#define EXTI_EMR_EM7 EXTI_EMR_MR7
6808#define EXTI_EMR_EM8 EXTI_EMR_MR8
6809#define EXTI_EMR_EM9 EXTI_EMR_MR9
6810#define EXTI_EMR_EM10 EXTI_EMR_MR10
6811#define EXTI_EMR_EM11 EXTI_EMR_MR11
6812#define EXTI_EMR_EM12 EXTI_EMR_MR12
6813#define EXTI_EMR_EM13 EXTI_EMR_MR13
6814#define EXTI_EMR_EM14 EXTI_EMR_MR14
6815#define EXTI_EMR_EM15 EXTI_EMR_MR15
6816#define EXTI_EMR_EM16 EXTI_EMR_MR16
6817#define EXTI_EMR_EM17 EXTI_EMR_MR17
6818#define EXTI_EMR_EM18 EXTI_EMR_MR18
6819#define EXTI_EMR_EM19 EXTI_EMR_MR19
6820#define EXTI_EMR_EM20 EXTI_EMR_MR20
6821#define EXTI_EMR_EM21 EXTI_EMR_MR21
6822#define EXTI_EMR_EM22 EXTI_EMR_MR22
6823
6824/****************** Bit definition for EXTI_RTSR register *******************/
6825#define EXTI_RTSR_TR0_Pos (0U)
6826#define EXTI_RTSR_TR0_Msk (0x1UL << EXTI_RTSR_TR0_Pos)
6827#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk
6828#define EXTI_RTSR_TR1_Pos (1U)
6829#define EXTI_RTSR_TR1_Msk (0x1UL << EXTI_RTSR_TR1_Pos)
6830#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk
6831#define EXTI_RTSR_TR2_Pos (2U)
6832#define EXTI_RTSR_TR2_Msk (0x1UL << EXTI_RTSR_TR2_Pos)
6833#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk
6834#define EXTI_RTSR_TR3_Pos (3U)
6835#define EXTI_RTSR_TR3_Msk (0x1UL << EXTI_RTSR_TR3_Pos)
6836#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk
6837#define EXTI_RTSR_TR4_Pos (4U)
6838#define EXTI_RTSR_TR4_Msk (0x1UL << EXTI_RTSR_TR4_Pos)
6839#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk
6840#define EXTI_RTSR_TR5_Pos (5U)
6841#define EXTI_RTSR_TR5_Msk (0x1UL << EXTI_RTSR_TR5_Pos)
6842#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk
6843#define EXTI_RTSR_TR6_Pos (6U)
6844#define EXTI_RTSR_TR6_Msk (0x1UL << EXTI_RTSR_TR6_Pos)
6845#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk
6846#define EXTI_RTSR_TR7_Pos (7U)
6847#define EXTI_RTSR_TR7_Msk (0x1UL << EXTI_RTSR_TR7_Pos)
6848#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk
6849#define EXTI_RTSR_TR8_Pos (8U)
6850#define EXTI_RTSR_TR8_Msk (0x1UL << EXTI_RTSR_TR8_Pos)
6851#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk
6852#define EXTI_RTSR_TR9_Pos (9U)
6853#define EXTI_RTSR_TR9_Msk (0x1UL << EXTI_RTSR_TR9_Pos)
6854#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk
6855#define EXTI_RTSR_TR10_Pos (10U)
6856#define EXTI_RTSR_TR10_Msk (0x1UL << EXTI_RTSR_TR10_Pos)
6857#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk
6858#define EXTI_RTSR_TR11_Pos (11U)
6859#define EXTI_RTSR_TR11_Msk (0x1UL << EXTI_RTSR_TR11_Pos)
6860#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk
6861#define EXTI_RTSR_TR12_Pos (12U)
6862#define EXTI_RTSR_TR12_Msk (0x1UL << EXTI_RTSR_TR12_Pos)
6863#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk
6864#define EXTI_RTSR_TR13_Pos (13U)
6865#define EXTI_RTSR_TR13_Msk (0x1UL << EXTI_RTSR_TR13_Pos)
6866#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk
6867#define EXTI_RTSR_TR14_Pos (14U)
6868#define EXTI_RTSR_TR14_Msk (0x1UL << EXTI_RTSR_TR14_Pos)
6869#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk
6870#define EXTI_RTSR_TR15_Pos (15U)
6871#define EXTI_RTSR_TR15_Msk (0x1UL << EXTI_RTSR_TR15_Pos)
6872#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk
6873#define EXTI_RTSR_TR16_Pos (16U)
6874#define EXTI_RTSR_TR16_Msk (0x1UL << EXTI_RTSR_TR16_Pos)
6875#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk
6876#define EXTI_RTSR_TR17_Pos (17U)
6877#define EXTI_RTSR_TR17_Msk (0x1UL << EXTI_RTSR_TR17_Pos)
6878#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk
6879#define EXTI_RTSR_TR18_Pos (18U)
6880#define EXTI_RTSR_TR18_Msk (0x1UL << EXTI_RTSR_TR18_Pos)
6881#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk
6882#define EXTI_RTSR_TR19_Pos (19U)
6883#define EXTI_RTSR_TR19_Msk (0x1UL << EXTI_RTSR_TR19_Pos)
6884#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk
6885#define EXTI_RTSR_TR20_Pos (20U)
6886#define EXTI_RTSR_TR20_Msk (0x1UL << EXTI_RTSR_TR20_Pos)
6887#define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk
6888#define EXTI_RTSR_TR21_Pos (21U)
6889#define EXTI_RTSR_TR21_Msk (0x1UL << EXTI_RTSR_TR21_Pos)
6890#define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk
6891#define EXTI_RTSR_TR22_Pos (22U)
6892#define EXTI_RTSR_TR22_Msk (0x1UL << EXTI_RTSR_TR22_Pos)
6893#define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk
6894
6895/****************** Bit definition for EXTI_FTSR register *******************/
6896#define EXTI_FTSR_TR0_Pos (0U)
6897#define EXTI_FTSR_TR0_Msk (0x1UL << EXTI_FTSR_TR0_Pos)
6898#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk
6899#define EXTI_FTSR_TR1_Pos (1U)
6900#define EXTI_FTSR_TR1_Msk (0x1UL << EXTI_FTSR_TR1_Pos)
6901#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk
6902#define EXTI_FTSR_TR2_Pos (2U)
6903#define EXTI_FTSR_TR2_Msk (0x1UL << EXTI_FTSR_TR2_Pos)
6904#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk
6905#define EXTI_FTSR_TR3_Pos (3U)
6906#define EXTI_FTSR_TR3_Msk (0x1UL << EXTI_FTSR_TR3_Pos)
6907#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk
6908#define EXTI_FTSR_TR4_Pos (4U)
6909#define EXTI_FTSR_TR4_Msk (0x1UL << EXTI_FTSR_TR4_Pos)
6910#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk
6911#define EXTI_FTSR_TR5_Pos (5U)
6912#define EXTI_FTSR_TR5_Msk (0x1UL << EXTI_FTSR_TR5_Pos)
6913#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk
6914#define EXTI_FTSR_TR6_Pos (6U)
6915#define EXTI_FTSR_TR6_Msk (0x1UL << EXTI_FTSR_TR6_Pos)
6916#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk
6917#define EXTI_FTSR_TR7_Pos (7U)
6918#define EXTI_FTSR_TR7_Msk (0x1UL << EXTI_FTSR_TR7_Pos)
6919#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk
6920#define EXTI_FTSR_TR8_Pos (8U)
6921#define EXTI_FTSR_TR8_Msk (0x1UL << EXTI_FTSR_TR8_Pos)
6922#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk
6923#define EXTI_FTSR_TR9_Pos (9U)
6924#define EXTI_FTSR_TR9_Msk (0x1UL << EXTI_FTSR_TR9_Pos)
6925#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk
6926#define EXTI_FTSR_TR10_Pos (10U)
6927#define EXTI_FTSR_TR10_Msk (0x1UL << EXTI_FTSR_TR10_Pos)
6928#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk
6929#define EXTI_FTSR_TR11_Pos (11U)
6930#define EXTI_FTSR_TR11_Msk (0x1UL << EXTI_FTSR_TR11_Pos)
6931#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk
6932#define EXTI_FTSR_TR12_Pos (12U)
6933#define EXTI_FTSR_TR12_Msk (0x1UL << EXTI_FTSR_TR12_Pos)
6934#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk
6935#define EXTI_FTSR_TR13_Pos (13U)
6936#define EXTI_FTSR_TR13_Msk (0x1UL << EXTI_FTSR_TR13_Pos)
6937#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk
6938#define EXTI_FTSR_TR14_Pos (14U)
6939#define EXTI_FTSR_TR14_Msk (0x1UL << EXTI_FTSR_TR14_Pos)
6940#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk
6941#define EXTI_FTSR_TR15_Pos (15U)
6942#define EXTI_FTSR_TR15_Msk (0x1UL << EXTI_FTSR_TR15_Pos)
6943#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk
6944#define EXTI_FTSR_TR16_Pos (16U)
6945#define EXTI_FTSR_TR16_Msk (0x1UL << EXTI_FTSR_TR16_Pos)
6946#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk
6947#define EXTI_FTSR_TR17_Pos (17U)
6948#define EXTI_FTSR_TR17_Msk (0x1UL << EXTI_FTSR_TR17_Pos)
6949#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk
6950#define EXTI_FTSR_TR18_Pos (18U)
6951#define EXTI_FTSR_TR18_Msk (0x1UL << EXTI_FTSR_TR18_Pos)
6952#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk
6953#define EXTI_FTSR_TR19_Pos (19U)
6954#define EXTI_FTSR_TR19_Msk (0x1UL << EXTI_FTSR_TR19_Pos)
6955#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk
6956#define EXTI_FTSR_TR20_Pos (20U)
6957#define EXTI_FTSR_TR20_Msk (0x1UL << EXTI_FTSR_TR20_Pos)
6958#define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk
6959#define EXTI_FTSR_TR21_Pos (21U)
6960#define EXTI_FTSR_TR21_Msk (0x1UL << EXTI_FTSR_TR21_Pos)
6961#define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk
6962#define EXTI_FTSR_TR22_Pos (22U)
6963#define EXTI_FTSR_TR22_Msk (0x1UL << EXTI_FTSR_TR22_Pos)
6964#define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk
6965
6966/****************** Bit definition for EXTI_SWIER register ******************/
6967#define EXTI_SWIER_SWIER0_Pos (0U)
6968#define EXTI_SWIER_SWIER0_Msk (0x1UL << EXTI_SWIER_SWIER0_Pos)
6969#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk
6970#define EXTI_SWIER_SWIER1_Pos (1U)
6971#define EXTI_SWIER_SWIER1_Msk (0x1UL << EXTI_SWIER_SWIER1_Pos)
6972#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk
6973#define EXTI_SWIER_SWIER2_Pos (2U)
6974#define EXTI_SWIER_SWIER2_Msk (0x1UL << EXTI_SWIER_SWIER2_Pos)
6975#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk
6976#define EXTI_SWIER_SWIER3_Pos (3U)
6977#define EXTI_SWIER_SWIER3_Msk (0x1UL << EXTI_SWIER_SWIER3_Pos)
6978#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk
6979#define EXTI_SWIER_SWIER4_Pos (4U)
6980#define EXTI_SWIER_SWIER4_Msk (0x1UL << EXTI_SWIER_SWIER4_Pos)
6981#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk
6982#define EXTI_SWIER_SWIER5_Pos (5U)
6983#define EXTI_SWIER_SWIER5_Msk (0x1UL << EXTI_SWIER_SWIER5_Pos)
6984#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk
6985#define EXTI_SWIER_SWIER6_Pos (6U)
6986#define EXTI_SWIER_SWIER6_Msk (0x1UL << EXTI_SWIER_SWIER6_Pos)
6987#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk
6988#define EXTI_SWIER_SWIER7_Pos (7U)
6989#define EXTI_SWIER_SWIER7_Msk (0x1UL << EXTI_SWIER_SWIER7_Pos)
6990#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk
6991#define EXTI_SWIER_SWIER8_Pos (8U)
6992#define EXTI_SWIER_SWIER8_Msk (0x1UL << EXTI_SWIER_SWIER8_Pos)
6993#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk
6994#define EXTI_SWIER_SWIER9_Pos (9U)
6995#define EXTI_SWIER_SWIER9_Msk (0x1UL << EXTI_SWIER_SWIER9_Pos)
6996#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk
6997#define EXTI_SWIER_SWIER10_Pos (10U)
6998#define EXTI_SWIER_SWIER10_Msk (0x1UL << EXTI_SWIER_SWIER10_Pos)
6999#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk
7000#define EXTI_SWIER_SWIER11_Pos (11U)
7001#define EXTI_SWIER_SWIER11_Msk (0x1UL << EXTI_SWIER_SWIER11_Pos)
7002#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk
7003#define EXTI_SWIER_SWIER12_Pos (12U)
7004#define EXTI_SWIER_SWIER12_Msk (0x1UL << EXTI_SWIER_SWIER12_Pos)
7005#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk
7006#define EXTI_SWIER_SWIER13_Pos (13U)
7007#define EXTI_SWIER_SWIER13_Msk (0x1UL << EXTI_SWIER_SWIER13_Pos)
7008#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk
7009#define EXTI_SWIER_SWIER14_Pos (14U)
7010#define EXTI_SWIER_SWIER14_Msk (0x1UL << EXTI_SWIER_SWIER14_Pos)
7011#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk
7012#define EXTI_SWIER_SWIER15_Pos (15U)
7013#define EXTI_SWIER_SWIER15_Msk (0x1UL << EXTI_SWIER_SWIER15_Pos)
7014#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk
7015#define EXTI_SWIER_SWIER16_Pos (16U)
7016#define EXTI_SWIER_SWIER16_Msk (0x1UL << EXTI_SWIER_SWIER16_Pos)
7017#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk
7018#define EXTI_SWIER_SWIER17_Pos (17U)
7019#define EXTI_SWIER_SWIER17_Msk (0x1UL << EXTI_SWIER_SWIER17_Pos)
7020#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk
7021#define EXTI_SWIER_SWIER18_Pos (18U)
7022#define EXTI_SWIER_SWIER18_Msk (0x1UL << EXTI_SWIER_SWIER18_Pos)
7023#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk
7024#define EXTI_SWIER_SWIER19_Pos (19U)
7025#define EXTI_SWIER_SWIER19_Msk (0x1UL << EXTI_SWIER_SWIER19_Pos)
7026#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk
7027#define EXTI_SWIER_SWIER20_Pos (20U)
7028#define EXTI_SWIER_SWIER20_Msk (0x1UL << EXTI_SWIER_SWIER20_Pos)
7029#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk
7030#define EXTI_SWIER_SWIER21_Pos (21U)
7031#define EXTI_SWIER_SWIER21_Msk (0x1UL << EXTI_SWIER_SWIER21_Pos)
7032#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk
7033#define EXTI_SWIER_SWIER22_Pos (22U)
7034#define EXTI_SWIER_SWIER22_Msk (0x1UL << EXTI_SWIER_SWIER22_Pos)
7035#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk
7036
7037/******************* Bit definition for EXTI_PR register ********************/
7038#define EXTI_PR_PR0_Pos (0U)
7039#define EXTI_PR_PR0_Msk (0x1UL << EXTI_PR_PR0_Pos)
7040#define EXTI_PR_PR0 EXTI_PR_PR0_Msk
7041#define EXTI_PR_PR1_Pos (1U)
7042#define EXTI_PR_PR1_Msk (0x1UL << EXTI_PR_PR1_Pos)
7043#define EXTI_PR_PR1 EXTI_PR_PR1_Msk
7044#define EXTI_PR_PR2_Pos (2U)
7045#define EXTI_PR_PR2_Msk (0x1UL << EXTI_PR_PR2_Pos)
7046#define EXTI_PR_PR2 EXTI_PR_PR2_Msk
7047#define EXTI_PR_PR3_Pos (3U)
7048#define EXTI_PR_PR3_Msk (0x1UL << EXTI_PR_PR3_Pos)
7049#define EXTI_PR_PR3 EXTI_PR_PR3_Msk
7050#define EXTI_PR_PR4_Pos (4U)
7051#define EXTI_PR_PR4_Msk (0x1UL << EXTI_PR_PR4_Pos)
7052#define EXTI_PR_PR4 EXTI_PR_PR4_Msk
7053#define EXTI_PR_PR5_Pos (5U)
7054#define EXTI_PR_PR5_Msk (0x1UL << EXTI_PR_PR5_Pos)
7055#define EXTI_PR_PR5 EXTI_PR_PR5_Msk
7056#define EXTI_PR_PR6_Pos (6U)
7057#define EXTI_PR_PR6_Msk (0x1UL << EXTI_PR_PR6_Pos)
7058#define EXTI_PR_PR6 EXTI_PR_PR6_Msk
7059#define EXTI_PR_PR7_Pos (7U)
7060#define EXTI_PR_PR7_Msk (0x1UL << EXTI_PR_PR7_Pos)
7061#define EXTI_PR_PR7 EXTI_PR_PR7_Msk
7062#define EXTI_PR_PR8_Pos (8U)
7063#define EXTI_PR_PR8_Msk (0x1UL << EXTI_PR_PR8_Pos)
7064#define EXTI_PR_PR8 EXTI_PR_PR8_Msk
7065#define EXTI_PR_PR9_Pos (9U)
7066#define EXTI_PR_PR9_Msk (0x1UL << EXTI_PR_PR9_Pos)
7067#define EXTI_PR_PR9 EXTI_PR_PR9_Msk
7068#define EXTI_PR_PR10_Pos (10U)
7069#define EXTI_PR_PR10_Msk (0x1UL << EXTI_PR_PR10_Pos)
7070#define EXTI_PR_PR10 EXTI_PR_PR10_Msk
7071#define EXTI_PR_PR11_Pos (11U)
7072#define EXTI_PR_PR11_Msk (0x1UL << EXTI_PR_PR11_Pos)
7073#define EXTI_PR_PR11 EXTI_PR_PR11_Msk
7074#define EXTI_PR_PR12_Pos (12U)
7075#define EXTI_PR_PR12_Msk (0x1UL << EXTI_PR_PR12_Pos)
7076#define EXTI_PR_PR12 EXTI_PR_PR12_Msk
7077#define EXTI_PR_PR13_Pos (13U)
7078#define EXTI_PR_PR13_Msk (0x1UL << EXTI_PR_PR13_Pos)
7079#define EXTI_PR_PR13 EXTI_PR_PR13_Msk
7080#define EXTI_PR_PR14_Pos (14U)
7081#define EXTI_PR_PR14_Msk (0x1UL << EXTI_PR_PR14_Pos)
7082#define EXTI_PR_PR14 EXTI_PR_PR14_Msk
7083#define EXTI_PR_PR15_Pos (15U)
7084#define EXTI_PR_PR15_Msk (0x1UL << EXTI_PR_PR15_Pos)
7085#define EXTI_PR_PR15 EXTI_PR_PR15_Msk
7086#define EXTI_PR_PR16_Pos (16U)
7087#define EXTI_PR_PR16_Msk (0x1UL << EXTI_PR_PR16_Pos)
7088#define EXTI_PR_PR16 EXTI_PR_PR16_Msk
7089#define EXTI_PR_PR17_Pos (17U)
7090#define EXTI_PR_PR17_Msk (0x1UL << EXTI_PR_PR17_Pos)
7091#define EXTI_PR_PR17 EXTI_PR_PR17_Msk
7092#define EXTI_PR_PR18_Pos (18U)
7093#define EXTI_PR_PR18_Msk (0x1UL << EXTI_PR_PR18_Pos)
7094#define EXTI_PR_PR18 EXTI_PR_PR18_Msk
7095#define EXTI_PR_PR19_Pos (19U)
7096#define EXTI_PR_PR19_Msk (0x1UL << EXTI_PR_PR19_Pos)
7097#define EXTI_PR_PR19 EXTI_PR_PR19_Msk
7098#define EXTI_PR_PR20_Pos (20U)
7099#define EXTI_PR_PR20_Msk (0x1UL << EXTI_PR_PR20_Pos)
7100#define EXTI_PR_PR20 EXTI_PR_PR20_Msk
7101#define EXTI_PR_PR21_Pos (21U)
7102#define EXTI_PR_PR21_Msk (0x1UL << EXTI_PR_PR21_Pos)
7103#define EXTI_PR_PR21 EXTI_PR_PR21_Msk
7104#define EXTI_PR_PR22_Pos (22U)
7105#define EXTI_PR_PR22_Msk (0x1UL << EXTI_PR_PR22_Pos)
7106#define EXTI_PR_PR22 EXTI_PR_PR22_Msk
7107
7108/******************************************************************************/
7109/* */
7110/* FLASH */
7111/* */
7112/******************************************************************************/
7113/******************* Bits definition for FLASH_ACR register *****************/
7114#define FLASH_ACR_LATENCY_Pos (0U)
7115#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos)
7116#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
7117#define FLASH_ACR_LATENCY_0WS 0x00000000U
7118#define FLASH_ACR_LATENCY_1WS 0x00000001U
7119#define FLASH_ACR_LATENCY_2WS 0x00000002U
7120#define FLASH_ACR_LATENCY_3WS 0x00000003U
7121#define FLASH_ACR_LATENCY_4WS 0x00000004U
7122#define FLASH_ACR_LATENCY_5WS 0x00000005U
7123#define FLASH_ACR_LATENCY_6WS 0x00000006U
7124#define FLASH_ACR_LATENCY_7WS 0x00000007U
7125
7126#define FLASH_ACR_LATENCY_8WS 0x00000008U
7127#define FLASH_ACR_LATENCY_9WS 0x00000009U
7128#define FLASH_ACR_LATENCY_10WS 0x0000000AU
7129#define FLASH_ACR_LATENCY_11WS 0x0000000BU
7130#define FLASH_ACR_LATENCY_12WS 0x0000000CU
7131#define FLASH_ACR_LATENCY_13WS 0x0000000DU
7132#define FLASH_ACR_LATENCY_14WS 0x0000000EU
7133#define FLASH_ACR_LATENCY_15WS 0x0000000FU
7134
7135#define FLASH_ACR_PRFTEN_Pos (8U)
7136#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos)
7137#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
7138#define FLASH_ACR_ICEN_Pos (9U)
7139#define FLASH_ACR_ICEN_Msk (0x1UL << FLASH_ACR_ICEN_Pos)
7140#define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
7141#define FLASH_ACR_DCEN_Pos (10U)
7142#define FLASH_ACR_DCEN_Msk (0x1UL << FLASH_ACR_DCEN_Pos)
7143#define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
7144#define FLASH_ACR_ICRST_Pos (11U)
7145#define FLASH_ACR_ICRST_Msk (0x1UL << FLASH_ACR_ICRST_Pos)
7146#define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
7147#define FLASH_ACR_DCRST_Pos (12U)
7148#define FLASH_ACR_DCRST_Msk (0x1UL << FLASH_ACR_DCRST_Pos)
7149#define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
7150
7151/******************* Bits definition for FLASH_SR register ******************/
7152#define FLASH_SR_EOP_Pos (0U)
7153#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos)
7154#define FLASH_SR_EOP FLASH_SR_EOP_Msk
7155#define FLASH_SR_OPERR_Pos (1U)
7156#define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos)
7157#define FLASH_SR_OPERR FLASH_SR_OPERR_Msk
7158#define FLASH_SR_WRPERR_Pos (4U)
7159#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos)
7160#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
7161#define FLASH_SR_PGAERR_Pos (5U)
7162#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos)
7163#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
7164#define FLASH_SR_PGPERR_Pos (6U)
7165#define FLASH_SR_PGPERR_Msk (0x1UL << FLASH_SR_PGPERR_Pos)
7166#define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk
7167#define FLASH_SR_PGSERR_Pos (7U)
7168#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos)
7169#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
7170#define FLASH_SR_RDERR_Pos (8U)
7171#define FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos)
7172#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
7173#define FLASH_SR_BSY_Pos (16U)
7174#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos)
7175#define FLASH_SR_BSY FLASH_SR_BSY_Msk
7176
7177/******************* Bits definition for FLASH_CR register ******************/
7178#define FLASH_CR_PG_Pos (0U)
7179#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos)
7180#define FLASH_CR_PG FLASH_CR_PG_Msk
7181#define FLASH_CR_SER_Pos (1U)
7182#define FLASH_CR_SER_Msk (0x1UL << FLASH_CR_SER_Pos)
7183#define FLASH_CR_SER FLASH_CR_SER_Msk
7184#define FLASH_CR_MER_Pos (2U)
7185#define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos)
7186#define FLASH_CR_MER FLASH_CR_MER_Msk
7187#define FLASH_CR_MER1 FLASH_CR_MER
7188#define FLASH_CR_SNB_Pos (3U)
7189#define FLASH_CR_SNB_Msk (0x1FUL << FLASH_CR_SNB_Pos)
7190#define FLASH_CR_SNB FLASH_CR_SNB_Msk
7191#define FLASH_CR_SNB_0 (0x01UL << FLASH_CR_SNB_Pos)
7192#define FLASH_CR_SNB_1 (0x02UL << FLASH_CR_SNB_Pos)
7193#define FLASH_CR_SNB_2 (0x04UL << FLASH_CR_SNB_Pos)
7194#define FLASH_CR_SNB_3 (0x08UL << FLASH_CR_SNB_Pos)
7195#define FLASH_CR_SNB_4 (0x10UL << FLASH_CR_SNB_Pos)
7196#define FLASH_CR_PSIZE_Pos (8U)
7197#define FLASH_CR_PSIZE_Msk (0x3UL << FLASH_CR_PSIZE_Pos)
7198#define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
7199#define FLASH_CR_PSIZE_0 (0x1UL << FLASH_CR_PSIZE_Pos)
7200#define FLASH_CR_PSIZE_1 (0x2UL << FLASH_CR_PSIZE_Pos)
7201#define FLASH_CR_MER2_Pos (15U)
7202#define FLASH_CR_MER2_Msk (0x1UL << FLASH_CR_MER2_Pos)
7203#define FLASH_CR_MER2 FLASH_CR_MER2_Msk
7204#define FLASH_CR_STRT_Pos (16U)
7205#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos)
7206#define FLASH_CR_STRT FLASH_CR_STRT_Msk
7207#define FLASH_CR_EOPIE_Pos (24U)
7208#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos)
7209#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
7210#define FLASH_CR_ERRIE_Pos (25U)
7211#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos)
7212#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk
7213#define FLASH_CR_LOCK_Pos (31U)
7214#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos)
7215#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
7216
7217/******************* Bits definition for FLASH_OPTCR register ***************/
7218#define FLASH_OPTCR_OPTLOCK_Pos (0U)
7219#define FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)
7220#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
7221#define FLASH_OPTCR_OPTSTRT_Pos (1U)
7222#define FLASH_OPTCR_OPTSTRT_Msk (0x1UL << FLASH_OPTCR_OPTSTRT_Pos)
7223#define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk
7224
7225#define FLASH_OPTCR_BOR_LEV_0 0x00000004U
7226#define FLASH_OPTCR_BOR_LEV_1 0x00000008U
7227#define FLASH_OPTCR_BOR_LEV_Pos (2U)
7228#define FLASH_OPTCR_BOR_LEV_Msk (0x3UL << FLASH_OPTCR_BOR_LEV_Pos)
7229#define FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk
7230#define FLASH_OPTCR_BFB2_Pos (4U)
7231#define FLASH_OPTCR_BFB2_Msk (0x1UL << FLASH_OPTCR_BFB2_Pos)
7232#define FLASH_OPTCR_BFB2 FLASH_OPTCR_BFB2_Msk
7233#define FLASH_OPTCR_WDG_SW_Pos (5U)
7234#define FLASH_OPTCR_WDG_SW_Msk (0x1UL << FLASH_OPTCR_WDG_SW_Pos)
7235#define FLASH_OPTCR_WDG_SW FLASH_OPTCR_WDG_SW_Msk
7236#define FLASH_OPTCR_nRST_STOP_Pos (6U)
7237#define FLASH_OPTCR_nRST_STOP_Msk (0x1UL << FLASH_OPTCR_nRST_STOP_Pos)
7238#define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk
7239#define FLASH_OPTCR_nRST_STDBY_Pos (7U)
7240#define FLASH_OPTCR_nRST_STDBY_Msk (0x1UL << FLASH_OPTCR_nRST_STDBY_Pos)
7241#define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk
7242#define FLASH_OPTCR_RDP_Pos (8U)
7243#define FLASH_OPTCR_RDP_Msk (0xFFUL << FLASH_OPTCR_RDP_Pos)
7244#define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk
7245#define FLASH_OPTCR_RDP_0 (0x01UL << FLASH_OPTCR_RDP_Pos)
7246#define FLASH_OPTCR_RDP_1 (0x02UL << FLASH_OPTCR_RDP_Pos)
7247#define FLASH_OPTCR_RDP_2 (0x04UL << FLASH_OPTCR_RDP_Pos)
7248#define FLASH_OPTCR_RDP_3 (0x08UL << FLASH_OPTCR_RDP_Pos)
7249#define FLASH_OPTCR_RDP_4 (0x10UL << FLASH_OPTCR_RDP_Pos)
7250#define FLASH_OPTCR_RDP_5 (0x20UL << FLASH_OPTCR_RDP_Pos)
7251#define FLASH_OPTCR_RDP_6 (0x40UL << FLASH_OPTCR_RDP_Pos)
7252#define FLASH_OPTCR_RDP_7 (0x80UL << FLASH_OPTCR_RDP_Pos)
7253#define FLASH_OPTCR_nWRP_Pos (16U)
7254#define FLASH_OPTCR_nWRP_Msk (0xFFFUL << FLASH_OPTCR_nWRP_Pos)
7255#define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk
7256#define FLASH_OPTCR_nWRP_0 0x00010000U
7257#define FLASH_OPTCR_nWRP_1 0x00020000U
7258#define FLASH_OPTCR_nWRP_2 0x00040000U
7259#define FLASH_OPTCR_nWRP_3 0x00080000U
7260#define FLASH_OPTCR_nWRP_4 0x00100000U
7261#define FLASH_OPTCR_nWRP_5 0x00200000U
7262#define FLASH_OPTCR_nWRP_6 0x00400000U
7263#define FLASH_OPTCR_nWRP_7 0x00800000U
7264#define FLASH_OPTCR_nWRP_8 0x01000000U
7265#define FLASH_OPTCR_nWRP_9 0x02000000U
7266#define FLASH_OPTCR_nWRP_10 0x04000000U
7267#define FLASH_OPTCR_nWRP_11 0x08000000U
7268#define FLASH_OPTCR_DB1M_Pos (30U)
7269#define FLASH_OPTCR_DB1M_Msk (0x1UL << FLASH_OPTCR_DB1M_Pos)
7270#define FLASH_OPTCR_DB1M FLASH_OPTCR_DB1M_Msk
7271#define FLASH_OPTCR_SPRMOD_Pos (31U)
7272#define FLASH_OPTCR_SPRMOD_Msk (0x1UL << FLASH_OPTCR_SPRMOD_Pos)
7273#define FLASH_OPTCR_SPRMOD FLASH_OPTCR_SPRMOD_Msk
7274
7275/****************** Bits definition for FLASH_OPTCR1 register ***************/
7276#define FLASH_OPTCR1_nWRP_Pos (16U)
7277#define FLASH_OPTCR1_nWRP_Msk (0xFFFUL << FLASH_OPTCR1_nWRP_Pos)
7278#define FLASH_OPTCR1_nWRP FLASH_OPTCR1_nWRP_Msk
7279#define FLASH_OPTCR1_nWRP_0 (0x001UL << FLASH_OPTCR1_nWRP_Pos)
7280#define FLASH_OPTCR1_nWRP_1 (0x002UL << FLASH_OPTCR1_nWRP_Pos)
7281#define FLASH_OPTCR1_nWRP_2 (0x004UL << FLASH_OPTCR1_nWRP_Pos)
7282#define FLASH_OPTCR1_nWRP_3 (0x008UL << FLASH_OPTCR1_nWRP_Pos)
7283#define FLASH_OPTCR1_nWRP_4 (0x010UL << FLASH_OPTCR1_nWRP_Pos)
7284#define FLASH_OPTCR1_nWRP_5 (0x020UL << FLASH_OPTCR1_nWRP_Pos)
7285#define FLASH_OPTCR1_nWRP_6 (0x040UL << FLASH_OPTCR1_nWRP_Pos)
7286#define FLASH_OPTCR1_nWRP_7 (0x080UL << FLASH_OPTCR1_nWRP_Pos)
7287#define FLASH_OPTCR1_nWRP_8 (0x100UL << FLASH_OPTCR1_nWRP_Pos)
7288#define FLASH_OPTCR1_nWRP_9 (0x200UL << FLASH_OPTCR1_nWRP_Pos)
7289#define FLASH_OPTCR1_nWRP_10 (0x400UL << FLASH_OPTCR1_nWRP_Pos)
7290#define FLASH_OPTCR1_nWRP_11 (0x800UL << FLASH_OPTCR1_nWRP_Pos)
7291/* Legacy defines */
7292#define FLASH_SR_SOP_Pos FLASH_SR_OPERR_Pos
7293#define FLASH_SR_SOP_Msk FLASH_SR_OPERR_Msk
7294#define FLASH_SR_SOP FLASH_SR_OPERR
7295#define FLASH_ACR_BYTE0_ADDRESS_Pos (10U)
7296#define FLASH_ACR_BYTE0_ADDRESS_Msk (0x10008FUL << FLASH_ACR_BYTE0_ADDRESS_Pos)
7297#define FLASH_ACR_BYTE0_ADDRESS FLASH_ACR_BYTE0_ADDRESS_Msk
7298#define FLASH_ACR_BYTE2_ADDRESS_Pos (0U)
7299#define FLASH_ACR_BYTE2_ADDRESS_Msk (0x40023C03UL << FLASH_ACR_BYTE2_ADDRESS_Pos)
7300#define FLASH_ACR_BYTE2_ADDRESS FLASH_ACR_BYTE2_ADDRESS_Msk
7301
7302/******************************************************************************/
7303/* */
7304/* Flexible Memory Controller */
7305/* */
7306/******************************************************************************/
7307/****************** Bit definition for FMC_BCR1 register *******************/
7308#define FMC_BCR1_MBKEN_Pos (0U)
7309#define FMC_BCR1_MBKEN_Msk (0x1UL << FMC_BCR1_MBKEN_Pos)
7310#define FMC_BCR1_MBKEN FMC_BCR1_MBKEN_Msk
7311#define FMC_BCR1_MUXEN_Pos (1U)
7312#define FMC_BCR1_MUXEN_Msk (0x1UL << FMC_BCR1_MUXEN_Pos)
7313#define FMC_BCR1_MUXEN FMC_BCR1_MUXEN_Msk
7314
7315#define FMC_BCR1_MTYP_Pos (2U)
7316#define FMC_BCR1_MTYP_Msk (0x3UL << FMC_BCR1_MTYP_Pos)
7317#define FMC_BCR1_MTYP FMC_BCR1_MTYP_Msk
7318#define FMC_BCR1_MTYP_0 (0x1UL << FMC_BCR1_MTYP_Pos)
7319#define FMC_BCR1_MTYP_1 (0x2UL << FMC_BCR1_MTYP_Pos)
7320
7321#define FMC_BCR1_MWID_Pos (4U)
7322#define FMC_BCR1_MWID_Msk (0x3UL << FMC_BCR1_MWID_Pos)
7323#define FMC_BCR1_MWID FMC_BCR1_MWID_Msk
7324#define FMC_BCR1_MWID_0 (0x1UL << FMC_BCR1_MWID_Pos)
7325#define FMC_BCR1_MWID_1 (0x2UL << FMC_BCR1_MWID_Pos)
7326
7327#define FMC_BCR1_FACCEN_Pos (6U)
7328#define FMC_BCR1_FACCEN_Msk (0x1UL << FMC_BCR1_FACCEN_Pos)
7329#define FMC_BCR1_FACCEN FMC_BCR1_FACCEN_Msk
7330#define FMC_BCR1_BURSTEN_Pos (8U)
7331#define FMC_BCR1_BURSTEN_Msk (0x1UL << FMC_BCR1_BURSTEN_Pos)
7332#define FMC_BCR1_BURSTEN FMC_BCR1_BURSTEN_Msk
7333#define FMC_BCR1_WAITPOL_Pos (9U)
7334#define FMC_BCR1_WAITPOL_Msk (0x1UL << FMC_BCR1_WAITPOL_Pos)
7335#define FMC_BCR1_WAITPOL FMC_BCR1_WAITPOL_Msk
7336#define FMC_BCR1_WRAPMOD_Pos (10U)
7337#define FMC_BCR1_WRAPMOD_Msk (0x1UL << FMC_BCR1_WRAPMOD_Pos)
7338#define FMC_BCR1_WRAPMOD FMC_BCR1_WRAPMOD_Msk
7339#define FMC_BCR1_WAITCFG_Pos (11U)
7340#define FMC_BCR1_WAITCFG_Msk (0x1UL << FMC_BCR1_WAITCFG_Pos)
7341#define FMC_BCR1_WAITCFG FMC_BCR1_WAITCFG_Msk
7342#define FMC_BCR1_WREN_Pos (12U)
7343#define FMC_BCR1_WREN_Msk (0x1UL << FMC_BCR1_WREN_Pos)
7344#define FMC_BCR1_WREN FMC_BCR1_WREN_Msk
7345#define FMC_BCR1_WAITEN_Pos (13U)
7346#define FMC_BCR1_WAITEN_Msk (0x1UL << FMC_BCR1_WAITEN_Pos)
7347#define FMC_BCR1_WAITEN FMC_BCR1_WAITEN_Msk
7348#define FMC_BCR1_EXTMOD_Pos (14U)
7349#define FMC_BCR1_EXTMOD_Msk (0x1UL << FMC_BCR1_EXTMOD_Pos)
7350#define FMC_BCR1_EXTMOD FMC_BCR1_EXTMOD_Msk
7351#define FMC_BCR1_ASYNCWAIT_Pos (15U)
7352#define FMC_BCR1_ASYNCWAIT_Msk (0x1UL << FMC_BCR1_ASYNCWAIT_Pos)
7353#define FMC_BCR1_ASYNCWAIT FMC_BCR1_ASYNCWAIT_Msk
7354#define FMC_BCR1_CPSIZE_Pos (16U)
7355#define FMC_BCR1_CPSIZE_Msk (0x7UL << FMC_BCR1_CPSIZE_Pos)
7356#define FMC_BCR1_CPSIZE FMC_BCR1_CPSIZE_Msk
7357#define FMC_BCR1_CPSIZE_0 (0x1UL << FMC_BCR1_CPSIZE_Pos)
7358#define FMC_BCR1_CPSIZE_1 (0x2UL << FMC_BCR1_CPSIZE_Pos)
7359#define FMC_BCR1_CPSIZE_2 (0x4UL << FMC_BCR1_CPSIZE_Pos)
7360#define FMC_BCR1_CBURSTRW_Pos (19U)
7361#define FMC_BCR1_CBURSTRW_Msk (0x1UL << FMC_BCR1_CBURSTRW_Pos)
7362#define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk
7363#define FMC_BCR1_CCLKEN_Pos (20U)
7364#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos)
7365#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk
7366
7367/****************** Bit definition for FMC_BCR2 register *******************/
7368#define FMC_BCR2_MBKEN_Pos (0U)
7369#define FMC_BCR2_MBKEN_Msk (0x1UL << FMC_BCR2_MBKEN_Pos)
7370#define FMC_BCR2_MBKEN FMC_BCR2_MBKEN_Msk
7371#define FMC_BCR2_MUXEN_Pos (1U)
7372#define FMC_BCR2_MUXEN_Msk (0x1UL << FMC_BCR2_MUXEN_Pos)
7373#define FMC_BCR2_MUXEN FMC_BCR2_MUXEN_Msk
7374
7375#define FMC_BCR2_MTYP_Pos (2U)
7376#define FMC_BCR2_MTYP_Msk (0x3UL << FMC_BCR2_MTYP_Pos)
7377#define FMC_BCR2_MTYP FMC_BCR2_MTYP_Msk
7378#define FMC_BCR2_MTYP_0 (0x1UL << FMC_BCR2_MTYP_Pos)
7379#define FMC_BCR2_MTYP_1 (0x2UL << FMC_BCR2_MTYP_Pos)
7380
7381#define FMC_BCR2_MWID_Pos (4U)
7382#define FMC_BCR2_MWID_Msk (0x3UL << FMC_BCR2_MWID_Pos)
7383#define FMC_BCR2_MWID FMC_BCR2_MWID_Msk
7384#define FMC_BCR2_MWID_0 (0x1UL << FMC_BCR2_MWID_Pos)
7385#define FMC_BCR2_MWID_1 (0x2UL << FMC_BCR2_MWID_Pos)
7386
7387#define FMC_BCR2_FACCEN_Pos (6U)
7388#define FMC_BCR2_FACCEN_Msk (0x1UL << FMC_BCR2_FACCEN_Pos)
7389#define FMC_BCR2_FACCEN FMC_BCR2_FACCEN_Msk
7390#define FMC_BCR2_BURSTEN_Pos (8U)
7391#define FMC_BCR2_BURSTEN_Msk (0x1UL << FMC_BCR2_BURSTEN_Pos)
7392#define FMC_BCR2_BURSTEN FMC_BCR2_BURSTEN_Msk
7393#define FMC_BCR2_WAITPOL_Pos (9U)
7394#define FMC_BCR2_WAITPOL_Msk (0x1UL << FMC_BCR2_WAITPOL_Pos)
7395#define FMC_BCR2_WAITPOL FMC_BCR2_WAITPOL_Msk
7396#define FMC_BCR2_WRAPMOD_Pos (10U)
7397#define FMC_BCR2_WRAPMOD_Msk (0x1UL << FMC_BCR2_WRAPMOD_Pos)
7398#define FMC_BCR2_WRAPMOD FMC_BCR2_WRAPMOD_Msk
7399#define FMC_BCR2_WAITCFG_Pos (11U)
7400#define FMC_BCR2_WAITCFG_Msk (0x1UL << FMC_BCR2_WAITCFG_Pos)
7401#define FMC_BCR2_WAITCFG FMC_BCR2_WAITCFG_Msk
7402#define FMC_BCR2_WREN_Pos (12U)
7403#define FMC_BCR2_WREN_Msk (0x1UL << FMC_BCR2_WREN_Pos)
7404#define FMC_BCR2_WREN FMC_BCR2_WREN_Msk
7405#define FMC_BCR2_WAITEN_Pos (13U)
7406#define FMC_BCR2_WAITEN_Msk (0x1UL << FMC_BCR2_WAITEN_Pos)
7407#define FMC_BCR2_WAITEN FMC_BCR2_WAITEN_Msk
7408#define FMC_BCR2_EXTMOD_Pos (14U)
7409#define FMC_BCR2_EXTMOD_Msk (0x1UL << FMC_BCR2_EXTMOD_Pos)
7410#define FMC_BCR2_EXTMOD FMC_BCR2_EXTMOD_Msk
7411#define FMC_BCR2_ASYNCWAIT_Pos (15U)
7412#define FMC_BCR2_ASYNCWAIT_Msk (0x1UL << FMC_BCR2_ASYNCWAIT_Pos)
7413#define FMC_BCR2_ASYNCWAIT FMC_BCR2_ASYNCWAIT_Msk
7414#define FMC_BCR2_CPSIZE_Pos (16U)
7415#define FMC_BCR2_CPSIZE_Msk (0x7UL << FMC_BCR2_CPSIZE_Pos)
7416#define FMC_BCR2_CPSIZE FMC_BCR2_CPSIZE_Msk
7417#define FMC_BCR2_CPSIZE_0 (0x1UL << FMC_BCR2_CPSIZE_Pos)
7418#define FMC_BCR2_CPSIZE_1 (0x2UL << FMC_BCR2_CPSIZE_Pos)
7419#define FMC_BCR2_CPSIZE_2 (0x4UL << FMC_BCR2_CPSIZE_Pos)
7420#define FMC_BCR2_CBURSTRW_Pos (19U)
7421#define FMC_BCR2_CBURSTRW_Msk (0x1UL << FMC_BCR2_CBURSTRW_Pos)
7422#define FMC_BCR2_CBURSTRW FMC_BCR2_CBURSTRW_Msk
7423
7424/****************** Bit definition for FMC_BCR3 register *******************/
7425#define FMC_BCR3_MBKEN_Pos (0U)
7426#define FMC_BCR3_MBKEN_Msk (0x1UL << FMC_BCR3_MBKEN_Pos)
7427#define FMC_BCR3_MBKEN FMC_BCR3_MBKEN_Msk
7428#define FMC_BCR3_MUXEN_Pos (1U)
7429#define FMC_BCR3_MUXEN_Msk (0x1UL << FMC_BCR3_MUXEN_Pos)
7430#define FMC_BCR3_MUXEN FMC_BCR3_MUXEN_Msk
7431
7432#define FMC_BCR3_MTYP_Pos (2U)
7433#define FMC_BCR3_MTYP_Msk (0x3UL << FMC_BCR3_MTYP_Pos)
7434#define FMC_BCR3_MTYP FMC_BCR3_MTYP_Msk
7435#define FMC_BCR3_MTYP_0 (0x1UL << FMC_BCR3_MTYP_Pos)
7436#define FMC_BCR3_MTYP_1 (0x2UL << FMC_BCR3_MTYP_Pos)
7437
7438#define FMC_BCR3_MWID_Pos (4U)
7439#define FMC_BCR3_MWID_Msk (0x3UL << FMC_BCR3_MWID_Pos)
7440#define FMC_BCR3_MWID FMC_BCR3_MWID_Msk
7441#define FMC_BCR3_MWID_0 (0x1UL << FMC_BCR3_MWID_Pos)
7442#define FMC_BCR3_MWID_1 (0x2UL << FMC_BCR3_MWID_Pos)
7443
7444#define FMC_BCR3_FACCEN_Pos (6U)
7445#define FMC_BCR3_FACCEN_Msk (0x1UL << FMC_BCR3_FACCEN_Pos)
7446#define FMC_BCR3_FACCEN FMC_BCR3_FACCEN_Msk
7447#define FMC_BCR3_BURSTEN_Pos (8U)
7448#define FMC_BCR3_BURSTEN_Msk (0x1UL << FMC_BCR3_BURSTEN_Pos)
7449#define FMC_BCR3_BURSTEN FMC_BCR3_BURSTEN_Msk
7450#define FMC_BCR3_WAITPOL_Pos (9U)
7451#define FMC_BCR3_WAITPOL_Msk (0x1UL << FMC_BCR3_WAITPOL_Pos)
7452#define FMC_BCR3_WAITPOL FMC_BCR3_WAITPOL_Msk
7453#define FMC_BCR3_WRAPMOD_Pos (10U)
7454#define FMC_BCR3_WRAPMOD_Msk (0x1UL << FMC_BCR3_WRAPMOD_Pos)
7455#define FMC_BCR3_WRAPMOD FMC_BCR3_WRAPMOD_Msk
7456#define FMC_BCR3_WAITCFG_Pos (11U)
7457#define FMC_BCR3_WAITCFG_Msk (0x1UL << FMC_BCR3_WAITCFG_Pos)
7458#define FMC_BCR3_WAITCFG FMC_BCR3_WAITCFG_Msk
7459#define FMC_BCR3_WREN_Pos (12U)
7460#define FMC_BCR3_WREN_Msk (0x1UL << FMC_BCR3_WREN_Pos)
7461#define FMC_BCR3_WREN FMC_BCR3_WREN_Msk
7462#define FMC_BCR3_WAITEN_Pos (13U)
7463#define FMC_BCR3_WAITEN_Msk (0x1UL << FMC_BCR3_WAITEN_Pos)
7464#define FMC_BCR3_WAITEN FMC_BCR3_WAITEN_Msk
7465#define FMC_BCR3_EXTMOD_Pos (14U)
7466#define FMC_BCR3_EXTMOD_Msk (0x1UL << FMC_BCR3_EXTMOD_Pos)
7467#define FMC_BCR3_EXTMOD FMC_BCR3_EXTMOD_Msk
7468#define FMC_BCR3_ASYNCWAIT_Pos (15U)
7469#define FMC_BCR3_ASYNCWAIT_Msk (0x1UL << FMC_BCR3_ASYNCWAIT_Pos)
7470#define FMC_BCR3_ASYNCWAIT FMC_BCR3_ASYNCWAIT_Msk
7471#define FMC_BCR3_CPSIZE_Pos (16U)
7472#define FMC_BCR3_CPSIZE_Msk (0x7UL << FMC_BCR3_CPSIZE_Pos)
7473#define FMC_BCR3_CPSIZE FMC_BCR3_CPSIZE_Msk
7474#define FMC_BCR3_CPSIZE_0 (0x1UL << FMC_BCR3_CPSIZE_Pos)
7475#define FMC_BCR3_CPSIZE_1 (0x2UL << FMC_BCR3_CPSIZE_Pos)
7476#define FMC_BCR3_CPSIZE_2 (0x4UL << FMC_BCR3_CPSIZE_Pos)
7477#define FMC_BCR3_CBURSTRW_Pos (19U)
7478#define FMC_BCR3_CBURSTRW_Msk (0x1UL << FMC_BCR3_CBURSTRW_Pos)
7479#define FMC_BCR3_CBURSTRW FMC_BCR3_CBURSTRW_Msk
7480
7481/****************** Bit definition for FMC_BCR4 register *******************/
7482#define FMC_BCR4_MBKEN_Pos (0U)
7483#define FMC_BCR4_MBKEN_Msk (0x1UL << FMC_BCR4_MBKEN_Pos)
7484#define FMC_BCR4_MBKEN FMC_BCR4_MBKEN_Msk
7485#define FMC_BCR4_MUXEN_Pos (1U)
7486#define FMC_BCR4_MUXEN_Msk (0x1UL << FMC_BCR4_MUXEN_Pos)
7487#define FMC_BCR4_MUXEN FMC_BCR4_MUXEN_Msk
7488
7489#define FMC_BCR4_MTYP_Pos (2U)
7490#define FMC_BCR4_MTYP_Msk (0x3UL << FMC_BCR4_MTYP_Pos)
7491#define FMC_BCR4_MTYP FMC_BCR4_MTYP_Msk
7492#define FMC_BCR4_MTYP_0 (0x1UL << FMC_BCR4_MTYP_Pos)
7493#define FMC_BCR4_MTYP_1 (0x2UL << FMC_BCR4_MTYP_Pos)
7494
7495#define FMC_BCR4_MWID_Pos (4U)
7496#define FMC_BCR4_MWID_Msk (0x3UL << FMC_BCR4_MWID_Pos)
7497#define FMC_BCR4_MWID FMC_BCR4_MWID_Msk
7498#define FMC_BCR4_MWID_0 (0x1UL << FMC_BCR4_MWID_Pos)
7499#define FMC_BCR4_MWID_1 (0x2UL << FMC_BCR4_MWID_Pos)
7500
7501#define FMC_BCR4_FACCEN_Pos (6U)
7502#define FMC_BCR4_FACCEN_Msk (0x1UL << FMC_BCR4_FACCEN_Pos)
7503#define FMC_BCR4_FACCEN FMC_BCR4_FACCEN_Msk
7504#define FMC_BCR4_BURSTEN_Pos (8U)
7505#define FMC_BCR4_BURSTEN_Msk (0x1UL << FMC_BCR4_BURSTEN_Pos)
7506#define FMC_BCR4_BURSTEN FMC_BCR4_BURSTEN_Msk
7507#define FMC_BCR4_WAITPOL_Pos (9U)
7508#define FMC_BCR4_WAITPOL_Msk (0x1UL << FMC_BCR4_WAITPOL_Pos)
7509#define FMC_BCR4_WAITPOL FMC_BCR4_WAITPOL_Msk
7510#define FMC_BCR4_WRAPMOD_Pos (10U)
7511#define FMC_BCR4_WRAPMOD_Msk (0x1UL << FMC_BCR4_WRAPMOD_Pos)
7512#define FMC_BCR4_WRAPMOD FMC_BCR4_WRAPMOD_Msk
7513#define FMC_BCR4_WAITCFG_Pos (11U)
7514#define FMC_BCR4_WAITCFG_Msk (0x1UL << FMC_BCR4_WAITCFG_Pos)
7515#define FMC_BCR4_WAITCFG FMC_BCR4_WAITCFG_Msk
7516#define FMC_BCR4_WREN_Pos (12U)
7517#define FMC_BCR4_WREN_Msk (0x1UL << FMC_BCR4_WREN_Pos)
7518#define FMC_BCR4_WREN FMC_BCR4_WREN_Msk
7519#define FMC_BCR4_WAITEN_Pos (13U)
7520#define FMC_BCR4_WAITEN_Msk (0x1UL << FMC_BCR4_WAITEN_Pos)
7521#define FMC_BCR4_WAITEN FMC_BCR4_WAITEN_Msk
7522#define FMC_BCR4_EXTMOD_Pos (14U)
7523#define FMC_BCR4_EXTMOD_Msk (0x1UL << FMC_BCR4_EXTMOD_Pos)
7524#define FMC_BCR4_EXTMOD FMC_BCR4_EXTMOD_Msk
7525#define FMC_BCR4_ASYNCWAIT_Pos (15U)
7526#define FMC_BCR4_ASYNCWAIT_Msk (0x1UL << FMC_BCR4_ASYNCWAIT_Pos)
7527#define FMC_BCR4_ASYNCWAIT FMC_BCR4_ASYNCWAIT_Msk
7528#define FMC_BCR4_CPSIZE_Pos (16U)
7529#define FMC_BCR4_CPSIZE_Msk (0x7UL << FMC_BCR4_CPSIZE_Pos)
7530#define FMC_BCR4_CPSIZE FMC_BCR4_CPSIZE_Msk
7531#define FMC_BCR4_CPSIZE_0 (0x1UL << FMC_BCR4_CPSIZE_Pos)
7532#define FMC_BCR4_CPSIZE_1 (0x2UL << FMC_BCR4_CPSIZE_Pos)
7533#define FMC_BCR4_CPSIZE_2 (0x4UL << FMC_BCR4_CPSIZE_Pos)
7534#define FMC_BCR4_CBURSTRW_Pos (19U)
7535#define FMC_BCR4_CBURSTRW_Msk (0x1UL << FMC_BCR4_CBURSTRW_Pos)
7536#define FMC_BCR4_CBURSTRW FMC_BCR4_CBURSTRW_Msk
7537
7538/****************** Bit definition for FMC_BTR1 register ******************/
7539#define FMC_BTR1_ADDSET_Pos (0U)
7540#define FMC_BTR1_ADDSET_Msk (0xFUL << FMC_BTR1_ADDSET_Pos)
7541#define FMC_BTR1_ADDSET FMC_BTR1_ADDSET_Msk
7542#define FMC_BTR1_ADDSET_0 (0x1UL << FMC_BTR1_ADDSET_Pos)
7543#define FMC_BTR1_ADDSET_1 (0x2UL << FMC_BTR1_ADDSET_Pos)
7544#define FMC_BTR1_ADDSET_2 (0x4UL << FMC_BTR1_ADDSET_Pos)
7545#define FMC_BTR1_ADDSET_3 (0x8UL << FMC_BTR1_ADDSET_Pos)
7546
7547#define FMC_BTR1_ADDHLD_Pos (4U)
7548#define FMC_BTR1_ADDHLD_Msk (0xFUL << FMC_BTR1_ADDHLD_Pos)
7549#define FMC_BTR1_ADDHLD FMC_BTR1_ADDHLD_Msk
7550#define FMC_BTR1_ADDHLD_0 (0x1UL << FMC_BTR1_ADDHLD_Pos)
7551#define FMC_BTR1_ADDHLD_1 (0x2UL << FMC_BTR1_ADDHLD_Pos)
7552#define FMC_BTR1_ADDHLD_2 (0x4UL << FMC_BTR1_ADDHLD_Pos)
7553#define FMC_BTR1_ADDHLD_3 (0x8UL << FMC_BTR1_ADDHLD_Pos)
7554
7555#define FMC_BTR1_DATAST_Pos (8U)
7556#define FMC_BTR1_DATAST_Msk (0xFFUL << FMC_BTR1_DATAST_Pos)
7557#define FMC_BTR1_DATAST FMC_BTR1_DATAST_Msk
7558#define FMC_BTR1_DATAST_0 (0x01UL << FMC_BTR1_DATAST_Pos)
7559#define FMC_BTR1_DATAST_1 (0x02UL << FMC_BTR1_DATAST_Pos)
7560#define FMC_BTR1_DATAST_2 (0x04UL << FMC_BTR1_DATAST_Pos)
7561#define FMC_BTR1_DATAST_3 (0x08UL << FMC_BTR1_DATAST_Pos)
7562#define FMC_BTR1_DATAST_4 (0x10UL << FMC_BTR1_DATAST_Pos)
7563#define FMC_BTR1_DATAST_5 (0x20UL << FMC_BTR1_DATAST_Pos)
7564#define FMC_BTR1_DATAST_6 (0x40UL << FMC_BTR1_DATAST_Pos)
7565#define FMC_BTR1_DATAST_7 (0x80UL << FMC_BTR1_DATAST_Pos)
7566
7567#define FMC_BTR1_BUSTURN_Pos (16U)
7568#define FMC_BTR1_BUSTURN_Msk (0xFUL << FMC_BTR1_BUSTURN_Pos)
7569#define FMC_BTR1_BUSTURN FMC_BTR1_BUSTURN_Msk
7570#define FMC_BTR1_BUSTURN_0 (0x1UL << FMC_BTR1_BUSTURN_Pos)
7571#define FMC_BTR1_BUSTURN_1 (0x2UL << FMC_BTR1_BUSTURN_Pos)
7572#define FMC_BTR1_BUSTURN_2 (0x4UL << FMC_BTR1_BUSTURN_Pos)
7573#define FMC_BTR1_BUSTURN_3 (0x8UL << FMC_BTR1_BUSTURN_Pos)
7574
7575#define FMC_BTR1_CLKDIV_Pos (20U)
7576#define FMC_BTR1_CLKDIV_Msk (0xFUL << FMC_BTR1_CLKDIV_Pos)
7577#define FMC_BTR1_CLKDIV FMC_BTR1_CLKDIV_Msk
7578#define FMC_BTR1_CLKDIV_0 (0x1UL << FMC_BTR1_CLKDIV_Pos)
7579#define FMC_BTR1_CLKDIV_1 (0x2UL << FMC_BTR1_CLKDIV_Pos)
7580#define FMC_BTR1_CLKDIV_2 (0x4UL << FMC_BTR1_CLKDIV_Pos)
7581#define FMC_BTR1_CLKDIV_3 (0x8UL << FMC_BTR1_CLKDIV_Pos)
7582
7583#define FMC_BTR1_DATLAT_Pos (24U)
7584#define FMC_BTR1_DATLAT_Msk (0xFUL << FMC_BTR1_DATLAT_Pos)
7585#define FMC_BTR1_DATLAT FMC_BTR1_DATLAT_Msk
7586#define FMC_BTR1_DATLAT_0 (0x1UL << FMC_BTR1_DATLAT_Pos)
7587#define FMC_BTR1_DATLAT_1 (0x2UL << FMC_BTR1_DATLAT_Pos)
7588#define FMC_BTR1_DATLAT_2 (0x4UL << FMC_BTR1_DATLAT_Pos)
7589#define FMC_BTR1_DATLAT_3 (0x8UL << FMC_BTR1_DATLAT_Pos)
7590
7591#define FMC_BTR1_ACCMOD_Pos (28U)
7592#define FMC_BTR1_ACCMOD_Msk (0x3UL << FMC_BTR1_ACCMOD_Pos)
7593#define FMC_BTR1_ACCMOD FMC_BTR1_ACCMOD_Msk
7594#define FMC_BTR1_ACCMOD_0 (0x1UL << FMC_BTR1_ACCMOD_Pos)
7595#define FMC_BTR1_ACCMOD_1 (0x2UL << FMC_BTR1_ACCMOD_Pos)
7596
7597/****************** Bit definition for FMC_BTR2 register *******************/
7598#define FMC_BTR2_ADDSET_Pos (0U)
7599#define FMC_BTR2_ADDSET_Msk (0xFUL << FMC_BTR2_ADDSET_Pos)
7600#define FMC_BTR2_ADDSET FMC_BTR2_ADDSET_Msk
7601#define FMC_BTR2_ADDSET_0 (0x1UL << FMC_BTR2_ADDSET_Pos)
7602#define FMC_BTR2_ADDSET_1 (0x2UL << FMC_BTR2_ADDSET_Pos)
7603#define FMC_BTR2_ADDSET_2 (0x4UL << FMC_BTR2_ADDSET_Pos)
7604#define FMC_BTR2_ADDSET_3 (0x8UL << FMC_BTR2_ADDSET_Pos)
7605
7606#define FMC_BTR2_ADDHLD_Pos (4U)
7607#define FMC_BTR2_ADDHLD_Msk (0xFUL << FMC_BTR2_ADDHLD_Pos)
7608#define FMC_BTR2_ADDHLD FMC_BTR2_ADDHLD_Msk
7609#define FMC_BTR2_ADDHLD_0 (0x1UL << FMC_BTR2_ADDHLD_Pos)
7610#define FMC_BTR2_ADDHLD_1 (0x2UL << FMC_BTR2_ADDHLD_Pos)
7611#define FMC_BTR2_ADDHLD_2 (0x4UL << FMC_BTR2_ADDHLD_Pos)
7612#define FMC_BTR2_ADDHLD_3 (0x8UL << FMC_BTR2_ADDHLD_Pos)
7613
7614#define FMC_BTR2_DATAST_Pos (8U)
7615#define FMC_BTR2_DATAST_Msk (0xFFUL << FMC_BTR2_DATAST_Pos)
7616#define FMC_BTR2_DATAST FMC_BTR2_DATAST_Msk
7617#define FMC_BTR2_DATAST_0 (0x01UL << FMC_BTR2_DATAST_Pos)
7618#define FMC_BTR2_DATAST_1 (0x02UL << FMC_BTR2_DATAST_Pos)
7619#define FMC_BTR2_DATAST_2 (0x04UL << FMC_BTR2_DATAST_Pos)
7620#define FMC_BTR2_DATAST_3 (0x08UL << FMC_BTR2_DATAST_Pos)
7621#define FMC_BTR2_DATAST_4 (0x10UL << FMC_BTR2_DATAST_Pos)
7622#define FMC_BTR2_DATAST_5 (0x20UL << FMC_BTR2_DATAST_Pos)
7623#define FMC_BTR2_DATAST_6 (0x40UL << FMC_BTR2_DATAST_Pos)
7624#define FMC_BTR2_DATAST_7 (0x80UL << FMC_BTR2_DATAST_Pos)
7625
7626#define FMC_BTR2_BUSTURN_Pos (16U)
7627#define FMC_BTR2_BUSTURN_Msk (0xFUL << FMC_BTR2_BUSTURN_Pos)
7628#define FMC_BTR2_BUSTURN FMC_BTR2_BUSTURN_Msk
7629#define FMC_BTR2_BUSTURN_0 (0x1UL << FMC_BTR2_BUSTURN_Pos)
7630#define FMC_BTR2_BUSTURN_1 (0x2UL << FMC_BTR2_BUSTURN_Pos)
7631#define FMC_BTR2_BUSTURN_2 (0x4UL << FMC_BTR2_BUSTURN_Pos)
7632#define FMC_BTR2_BUSTURN_3 (0x8UL << FMC_BTR2_BUSTURN_Pos)
7633
7634#define FMC_BTR2_CLKDIV_Pos (20U)
7635#define FMC_BTR2_CLKDIV_Msk (0xFUL << FMC_BTR2_CLKDIV_Pos)
7636#define FMC_BTR2_CLKDIV FMC_BTR2_CLKDIV_Msk
7637#define FMC_BTR2_CLKDIV_0 (0x1UL << FMC_BTR2_CLKDIV_Pos)
7638#define FMC_BTR2_CLKDIV_1 (0x2UL << FMC_BTR2_CLKDIV_Pos)
7639#define FMC_BTR2_CLKDIV_2 (0x4UL << FMC_BTR2_CLKDIV_Pos)
7640#define FMC_BTR2_CLKDIV_3 (0x8UL << FMC_BTR2_CLKDIV_Pos)
7641
7642#define FMC_BTR2_DATLAT_Pos (24U)
7643#define FMC_BTR2_DATLAT_Msk (0xFUL << FMC_BTR2_DATLAT_Pos)
7644#define FMC_BTR2_DATLAT FMC_BTR2_DATLAT_Msk
7645#define FMC_BTR2_DATLAT_0 (0x1UL << FMC_BTR2_DATLAT_Pos)
7646#define FMC_BTR2_DATLAT_1 (0x2UL << FMC_BTR2_DATLAT_Pos)
7647#define FMC_BTR2_DATLAT_2 (0x4UL << FMC_BTR2_DATLAT_Pos)
7648#define FMC_BTR2_DATLAT_3 (0x8UL << FMC_BTR2_DATLAT_Pos)
7649
7650#define FMC_BTR2_ACCMOD_Pos (28U)
7651#define FMC_BTR2_ACCMOD_Msk (0x3UL << FMC_BTR2_ACCMOD_Pos)
7652#define FMC_BTR2_ACCMOD FMC_BTR2_ACCMOD_Msk
7653#define FMC_BTR2_ACCMOD_0 (0x1UL << FMC_BTR2_ACCMOD_Pos)
7654#define FMC_BTR2_ACCMOD_1 (0x2UL << FMC_BTR2_ACCMOD_Pos)
7655
7656/******************* Bit definition for FMC_BTR3 register *******************/
7657#define FMC_BTR3_ADDSET_Pos (0U)
7658#define FMC_BTR3_ADDSET_Msk (0xFUL << FMC_BTR3_ADDSET_Pos)
7659#define FMC_BTR3_ADDSET FMC_BTR3_ADDSET_Msk
7660#define FMC_BTR3_ADDSET_0 (0x1UL << FMC_BTR3_ADDSET_Pos)
7661#define FMC_BTR3_ADDSET_1 (0x2UL << FMC_BTR3_ADDSET_Pos)
7662#define FMC_BTR3_ADDSET_2 (0x4UL << FMC_BTR3_ADDSET_Pos)
7663#define FMC_BTR3_ADDSET_3 (0x8UL << FMC_BTR3_ADDSET_Pos)
7664
7665#define FMC_BTR3_ADDHLD_Pos (4U)
7666#define FMC_BTR3_ADDHLD_Msk (0xFUL << FMC_BTR3_ADDHLD_Pos)
7667#define FMC_BTR3_ADDHLD FMC_BTR3_ADDHLD_Msk
7668#define FMC_BTR3_ADDHLD_0 (0x1UL << FMC_BTR3_ADDHLD_Pos)
7669#define FMC_BTR3_ADDHLD_1 (0x2UL << FMC_BTR3_ADDHLD_Pos)
7670#define FMC_BTR3_ADDHLD_2 (0x4UL << FMC_BTR3_ADDHLD_Pos)
7671#define FMC_BTR3_ADDHLD_3 (0x8UL << FMC_BTR3_ADDHLD_Pos)
7672
7673#define FMC_BTR3_DATAST_Pos (8U)
7674#define FMC_BTR3_DATAST_Msk (0xFFUL << FMC_BTR3_DATAST_Pos)
7675#define FMC_BTR3_DATAST FMC_BTR3_DATAST_Msk
7676#define FMC_BTR3_DATAST_0 (0x01UL << FMC_BTR3_DATAST_Pos)
7677#define FMC_BTR3_DATAST_1 (0x02UL << FMC_BTR3_DATAST_Pos)
7678#define FMC_BTR3_DATAST_2 (0x04UL << FMC_BTR3_DATAST_Pos)
7679#define FMC_BTR3_DATAST_3 (0x08UL << FMC_BTR3_DATAST_Pos)
7680#define FMC_BTR3_DATAST_4 (0x10UL << FMC_BTR3_DATAST_Pos)
7681#define FMC_BTR3_DATAST_5 (0x20UL << FMC_BTR3_DATAST_Pos)
7682#define FMC_BTR3_DATAST_6 (0x40UL << FMC_BTR3_DATAST_Pos)
7683#define FMC_BTR3_DATAST_7 (0x80UL << FMC_BTR3_DATAST_Pos)
7684
7685#define FMC_BTR3_BUSTURN_Pos (16U)
7686#define FMC_BTR3_BUSTURN_Msk (0xFUL << FMC_BTR3_BUSTURN_Pos)
7687#define FMC_BTR3_BUSTURN FMC_BTR3_BUSTURN_Msk
7688#define FMC_BTR3_BUSTURN_0 (0x1UL << FMC_BTR3_BUSTURN_Pos)
7689#define FMC_BTR3_BUSTURN_1 (0x2UL << FMC_BTR3_BUSTURN_Pos)
7690#define FMC_BTR3_BUSTURN_2 (0x4UL << FMC_BTR3_BUSTURN_Pos)
7691#define FMC_BTR3_BUSTURN_3 (0x8UL << FMC_BTR3_BUSTURN_Pos)
7692
7693#define FMC_BTR3_CLKDIV_Pos (20U)
7694#define FMC_BTR3_CLKDIV_Msk (0xFUL << FMC_BTR3_CLKDIV_Pos)
7695#define FMC_BTR3_CLKDIV FMC_BTR3_CLKDIV_Msk
7696#define FMC_BTR3_CLKDIV_0 (0x1UL << FMC_BTR3_CLKDIV_Pos)
7697#define FMC_BTR3_CLKDIV_1 (0x2UL << FMC_BTR3_CLKDIV_Pos)
7698#define FMC_BTR3_CLKDIV_2 (0x4UL << FMC_BTR3_CLKDIV_Pos)
7699#define FMC_BTR3_CLKDIV_3 (0x8UL << FMC_BTR3_CLKDIV_Pos)
7700
7701#define FMC_BTR3_DATLAT_Pos (24U)
7702#define FMC_BTR3_DATLAT_Msk (0xFUL << FMC_BTR3_DATLAT_Pos)
7703#define FMC_BTR3_DATLAT FMC_BTR3_DATLAT_Msk
7704#define FMC_BTR3_DATLAT_0 (0x1UL << FMC_BTR3_DATLAT_Pos)
7705#define FMC_BTR3_DATLAT_1 (0x2UL << FMC_BTR3_DATLAT_Pos)
7706#define FMC_BTR3_DATLAT_2 (0x4UL << FMC_BTR3_DATLAT_Pos)
7707#define FMC_BTR3_DATLAT_3 (0x8UL << FMC_BTR3_DATLAT_Pos)
7708
7709#define FMC_BTR3_ACCMOD_Pos (28U)
7710#define FMC_BTR3_ACCMOD_Msk (0x3UL << FMC_BTR3_ACCMOD_Pos)
7711#define FMC_BTR3_ACCMOD FMC_BTR3_ACCMOD_Msk
7712#define FMC_BTR3_ACCMOD_0 (0x1UL << FMC_BTR3_ACCMOD_Pos)
7713#define FMC_BTR3_ACCMOD_1 (0x2UL << FMC_BTR3_ACCMOD_Pos)
7714
7715/****************** Bit definition for FMC_BTR4 register *******************/
7716#define FMC_BTR4_ADDSET_Pos (0U)
7717#define FMC_BTR4_ADDSET_Msk (0xFUL << FMC_BTR4_ADDSET_Pos)
7718#define FMC_BTR4_ADDSET FMC_BTR4_ADDSET_Msk
7719#define FMC_BTR4_ADDSET_0 (0x1UL << FMC_BTR4_ADDSET_Pos)
7720#define FMC_BTR4_ADDSET_1 (0x2UL << FMC_BTR4_ADDSET_Pos)
7721#define FMC_BTR4_ADDSET_2 (0x4UL << FMC_BTR4_ADDSET_Pos)
7722#define FMC_BTR4_ADDSET_3 (0x8UL << FMC_BTR4_ADDSET_Pos)
7723
7724#define FMC_BTR4_ADDHLD_Pos (4U)
7725#define FMC_BTR4_ADDHLD_Msk (0xFUL << FMC_BTR4_ADDHLD_Pos)
7726#define FMC_BTR4_ADDHLD FMC_BTR4_ADDHLD_Msk
7727#define FMC_BTR4_ADDHLD_0 (0x1UL << FMC_BTR4_ADDHLD_Pos)
7728#define FMC_BTR4_ADDHLD_1 (0x2UL << FMC_BTR4_ADDHLD_Pos)
7729#define FMC_BTR4_ADDHLD_2 (0x4UL << FMC_BTR4_ADDHLD_Pos)
7730#define FMC_BTR4_ADDHLD_3 (0x8UL << FMC_BTR4_ADDHLD_Pos)
7731
7732#define FMC_BTR4_DATAST_Pos (8U)
7733#define FMC_BTR4_DATAST_Msk (0xFFUL << FMC_BTR4_DATAST_Pos)
7734#define FMC_BTR4_DATAST FMC_BTR4_DATAST_Msk
7735#define FMC_BTR4_DATAST_0 (0x01UL << FMC_BTR4_DATAST_Pos)
7736#define FMC_BTR4_DATAST_1 (0x02UL << FMC_BTR4_DATAST_Pos)
7737#define FMC_BTR4_DATAST_2 (0x04UL << FMC_BTR4_DATAST_Pos)
7738#define FMC_BTR4_DATAST_3 (0x08UL << FMC_BTR4_DATAST_Pos)
7739#define FMC_BTR4_DATAST_4 (0x10UL << FMC_BTR4_DATAST_Pos)
7740#define FMC_BTR4_DATAST_5 (0x20UL << FMC_BTR4_DATAST_Pos)
7741#define FMC_BTR4_DATAST_6 (0x40UL << FMC_BTR4_DATAST_Pos)
7742#define FMC_BTR4_DATAST_7 (0x80UL << FMC_BTR4_DATAST_Pos)
7743
7744#define FMC_BTR4_BUSTURN_Pos (16U)
7745#define FMC_BTR4_BUSTURN_Msk (0xFUL << FMC_BTR4_BUSTURN_Pos)
7746#define FMC_BTR4_BUSTURN FMC_BTR4_BUSTURN_Msk
7747#define FMC_BTR4_BUSTURN_0 (0x1UL << FMC_BTR4_BUSTURN_Pos)
7748#define FMC_BTR4_BUSTURN_1 (0x2UL << FMC_BTR4_BUSTURN_Pos)
7749#define FMC_BTR4_BUSTURN_2 (0x4UL << FMC_BTR4_BUSTURN_Pos)
7750#define FMC_BTR4_BUSTURN_3 (0x8UL << FMC_BTR4_BUSTURN_Pos)
7751
7752#define FMC_BTR4_CLKDIV_Pos (20U)
7753#define FMC_BTR4_CLKDIV_Msk (0xFUL << FMC_BTR4_CLKDIV_Pos)
7754#define FMC_BTR4_CLKDIV FMC_BTR4_CLKDIV_Msk
7755#define FMC_BTR4_CLKDIV_0 (0x1UL << FMC_BTR4_CLKDIV_Pos)
7756#define FMC_BTR4_CLKDIV_1 (0x2UL << FMC_BTR4_CLKDIV_Pos)
7757#define FMC_BTR4_CLKDIV_2 (0x4UL << FMC_BTR4_CLKDIV_Pos)
7758#define FMC_BTR4_CLKDIV_3 (0x8UL << FMC_BTR4_CLKDIV_Pos)
7759
7760#define FMC_BTR4_DATLAT_Pos (24U)
7761#define FMC_BTR4_DATLAT_Msk (0xFUL << FMC_BTR4_DATLAT_Pos)
7762#define FMC_BTR4_DATLAT FMC_BTR4_DATLAT_Msk
7763#define FMC_BTR4_DATLAT_0 (0x1UL << FMC_BTR4_DATLAT_Pos)
7764#define FMC_BTR4_DATLAT_1 (0x2UL << FMC_BTR4_DATLAT_Pos)
7765#define FMC_BTR4_DATLAT_2 (0x4UL << FMC_BTR4_DATLAT_Pos)
7766#define FMC_BTR4_DATLAT_3 (0x8UL << FMC_BTR4_DATLAT_Pos)
7767
7768#define FMC_BTR4_ACCMOD_Pos (28U)
7769#define FMC_BTR4_ACCMOD_Msk (0x3UL << FMC_BTR4_ACCMOD_Pos)
7770#define FMC_BTR4_ACCMOD FMC_BTR4_ACCMOD_Msk
7771#define FMC_BTR4_ACCMOD_0 (0x1UL << FMC_BTR4_ACCMOD_Pos)
7772#define FMC_BTR4_ACCMOD_1 (0x2UL << FMC_BTR4_ACCMOD_Pos)
7773
7774/****************** Bit definition for FMC_BWTR1 register ******************/
7775#define FMC_BWTR1_ADDSET_Pos (0U)
7776#define FMC_BWTR1_ADDSET_Msk (0xFUL << FMC_BWTR1_ADDSET_Pos)
7777#define FMC_BWTR1_ADDSET FMC_BWTR1_ADDSET_Msk
7778#define FMC_BWTR1_ADDSET_0 (0x1UL << FMC_BWTR1_ADDSET_Pos)
7779#define FMC_BWTR1_ADDSET_1 (0x2UL << FMC_BWTR1_ADDSET_Pos)
7780#define FMC_BWTR1_ADDSET_2 (0x4UL << FMC_BWTR1_ADDSET_Pos)
7781#define FMC_BWTR1_ADDSET_3 (0x8UL << FMC_BWTR1_ADDSET_Pos)
7782
7783#define FMC_BWTR1_ADDHLD_Pos (4U)
7784#define FMC_BWTR1_ADDHLD_Msk (0xFUL << FMC_BWTR1_ADDHLD_Pos)
7785#define FMC_BWTR1_ADDHLD FMC_BWTR1_ADDHLD_Msk
7786#define FMC_BWTR1_ADDHLD_0 (0x1UL << FMC_BWTR1_ADDHLD_Pos)
7787#define FMC_BWTR1_ADDHLD_1 (0x2UL << FMC_BWTR1_ADDHLD_Pos)
7788#define FMC_BWTR1_ADDHLD_2 (0x4UL << FMC_BWTR1_ADDHLD_Pos)
7789#define FMC_BWTR1_ADDHLD_3 (0x8UL << FMC_BWTR1_ADDHLD_Pos)
7790
7791#define FMC_BWTR1_DATAST_Pos (8U)
7792#define FMC_BWTR1_DATAST_Msk (0xFFUL << FMC_BWTR1_DATAST_Pos)
7793#define FMC_BWTR1_DATAST FMC_BWTR1_DATAST_Msk
7794#define FMC_BWTR1_DATAST_0 (0x01UL << FMC_BWTR1_DATAST_Pos)
7795#define FMC_BWTR1_DATAST_1 (0x02UL << FMC_BWTR1_DATAST_Pos)
7796#define FMC_BWTR1_DATAST_2 (0x04UL << FMC_BWTR1_DATAST_Pos)
7797#define FMC_BWTR1_DATAST_3 (0x08UL << FMC_BWTR1_DATAST_Pos)
7798#define FMC_BWTR1_DATAST_4 (0x10UL << FMC_BWTR1_DATAST_Pos)
7799#define FMC_BWTR1_DATAST_5 (0x20UL << FMC_BWTR1_DATAST_Pos)
7800#define FMC_BWTR1_DATAST_6 (0x40UL << FMC_BWTR1_DATAST_Pos)
7801#define FMC_BWTR1_DATAST_7 (0x80UL << FMC_BWTR1_DATAST_Pos)
7802
7803#define FMC_BWTR1_BUSTURN_Pos (16U)
7804#define FMC_BWTR1_BUSTURN_Msk (0xFUL << FMC_BWTR1_BUSTURN_Pos)
7805#define FMC_BWTR1_BUSTURN FMC_BWTR1_BUSTURN_Msk
7806#define FMC_BWTR1_BUSTURN_0 (0x1UL << FMC_BWTR1_BUSTURN_Pos)
7807#define FMC_BWTR1_BUSTURN_1 (0x2UL << FMC_BWTR1_BUSTURN_Pos)
7808#define FMC_BWTR1_BUSTURN_2 (0x4UL << FMC_BWTR1_BUSTURN_Pos)
7809#define FMC_BWTR1_BUSTURN_3 (0x8UL << FMC_BWTR1_BUSTURN_Pos)
7810
7811#define FMC_BWTR1_ACCMOD_Pos (28U)
7812#define FMC_BWTR1_ACCMOD_Msk (0x3UL << FMC_BWTR1_ACCMOD_Pos)
7813#define FMC_BWTR1_ACCMOD FMC_BWTR1_ACCMOD_Msk
7814#define FMC_BWTR1_ACCMOD_0 (0x1UL << FMC_BWTR1_ACCMOD_Pos)
7815#define FMC_BWTR1_ACCMOD_1 (0x2UL << FMC_BWTR1_ACCMOD_Pos)
7816
7817/****************** Bit definition for FMC_BWTR2 register ******************/
7818#define FMC_BWTR2_ADDSET_Pos (0U)
7819#define FMC_BWTR2_ADDSET_Msk (0xFUL << FMC_BWTR2_ADDSET_Pos)
7820#define FMC_BWTR2_ADDSET FMC_BWTR2_ADDSET_Msk
7821#define FMC_BWTR2_ADDSET_0 (0x1UL << FMC_BWTR2_ADDSET_Pos)
7822#define FMC_BWTR2_ADDSET_1 (0x2UL << FMC_BWTR2_ADDSET_Pos)
7823#define FMC_BWTR2_ADDSET_2 (0x4UL << FMC_BWTR2_ADDSET_Pos)
7824#define FMC_BWTR2_ADDSET_3 (0x8UL << FMC_BWTR2_ADDSET_Pos)
7825
7826#define FMC_BWTR2_ADDHLD_Pos (4U)
7827#define FMC_BWTR2_ADDHLD_Msk (0xFUL << FMC_BWTR2_ADDHLD_Pos)
7828#define FMC_BWTR2_ADDHLD FMC_BWTR2_ADDHLD_Msk
7829#define FMC_BWTR2_ADDHLD_0 (0x1UL << FMC_BWTR2_ADDHLD_Pos)
7830#define FMC_BWTR2_ADDHLD_1 (0x2UL << FMC_BWTR2_ADDHLD_Pos)
7831#define FMC_BWTR2_ADDHLD_2 (0x4UL << FMC_BWTR2_ADDHLD_Pos)
7832#define FMC_BWTR2_ADDHLD_3 (0x8UL << FMC_BWTR2_ADDHLD_Pos)
7833
7834#define FMC_BWTR2_DATAST_Pos (8U)
7835#define FMC_BWTR2_DATAST_Msk (0xFFUL << FMC_BWTR2_DATAST_Pos)
7836#define FMC_BWTR2_DATAST FMC_BWTR2_DATAST_Msk
7837#define FMC_BWTR2_DATAST_0 (0x01UL << FMC_BWTR2_DATAST_Pos)
7838#define FMC_BWTR2_DATAST_1 (0x02UL << FMC_BWTR2_DATAST_Pos)
7839#define FMC_BWTR2_DATAST_2 (0x04UL << FMC_BWTR2_DATAST_Pos)
7840#define FMC_BWTR2_DATAST_3 (0x08UL << FMC_BWTR2_DATAST_Pos)
7841#define FMC_BWTR2_DATAST_4 (0x10UL << FMC_BWTR2_DATAST_Pos)
7842#define FMC_BWTR2_DATAST_5 (0x20UL << FMC_BWTR2_DATAST_Pos)
7843#define FMC_BWTR2_DATAST_6 (0x40UL << FMC_BWTR2_DATAST_Pos)
7844#define FMC_BWTR2_DATAST_7 (0x80UL << FMC_BWTR2_DATAST_Pos)
7845
7846#define FMC_BWTR2_BUSTURN_Pos (16U)
7847#define FMC_BWTR2_BUSTURN_Msk (0xFUL << FMC_BWTR2_BUSTURN_Pos)
7848#define FMC_BWTR2_BUSTURN FMC_BWTR2_BUSTURN_Msk
7849#define FMC_BWTR2_BUSTURN_0 (0x1UL << FMC_BWTR2_BUSTURN_Pos)
7850#define FMC_BWTR2_BUSTURN_1 (0x2UL << FMC_BWTR2_BUSTURN_Pos)
7851#define FMC_BWTR2_BUSTURN_2 (0x4UL << FMC_BWTR2_BUSTURN_Pos)
7852#define FMC_BWTR2_BUSTURN_3 (0x8UL << FMC_BWTR2_BUSTURN_Pos)
7853
7854#define FMC_BWTR2_ACCMOD_Pos (28U)
7855#define FMC_BWTR2_ACCMOD_Msk (0x3UL << FMC_BWTR2_ACCMOD_Pos)
7856#define FMC_BWTR2_ACCMOD FMC_BWTR2_ACCMOD_Msk
7857#define FMC_BWTR2_ACCMOD_0 (0x1UL << FMC_BWTR2_ACCMOD_Pos)
7858#define FMC_BWTR2_ACCMOD_1 (0x2UL << FMC_BWTR2_ACCMOD_Pos)
7859
7860/****************** Bit definition for FMC_BWTR3 register ******************/
7861#define FMC_BWTR3_ADDSET_Pos (0U)
7862#define FMC_BWTR3_ADDSET_Msk (0xFUL << FMC_BWTR3_ADDSET_Pos)
7863#define FMC_BWTR3_ADDSET FMC_BWTR3_ADDSET_Msk
7864#define FMC_BWTR3_ADDSET_0 (0x1UL << FMC_BWTR3_ADDSET_Pos)
7865#define FMC_BWTR3_ADDSET_1 (0x2UL << FMC_BWTR3_ADDSET_Pos)
7866#define FMC_BWTR3_ADDSET_2 (0x4UL << FMC_BWTR3_ADDSET_Pos)
7867#define FMC_BWTR3_ADDSET_3 (0x8UL << FMC_BWTR3_ADDSET_Pos)
7868
7869#define FMC_BWTR3_ADDHLD_Pos (4U)
7870#define FMC_BWTR3_ADDHLD_Msk (0xFUL << FMC_BWTR3_ADDHLD_Pos)
7871#define FMC_BWTR3_ADDHLD FMC_BWTR3_ADDHLD_Msk
7872#define FMC_BWTR3_ADDHLD_0 (0x1UL << FMC_BWTR3_ADDHLD_Pos)
7873#define FMC_BWTR3_ADDHLD_1 (0x2UL << FMC_BWTR3_ADDHLD_Pos)
7874#define FMC_BWTR3_ADDHLD_2 (0x4UL << FMC_BWTR3_ADDHLD_Pos)
7875#define FMC_BWTR3_ADDHLD_3 (0x8UL << FMC_BWTR3_ADDHLD_Pos)
7876
7877#define FMC_BWTR3_DATAST_Pos (8U)
7878#define FMC_BWTR3_DATAST_Msk (0xFFUL << FMC_BWTR3_DATAST_Pos)
7879#define FMC_BWTR3_DATAST FMC_BWTR3_DATAST_Msk
7880#define FMC_BWTR3_DATAST_0 (0x01UL << FMC_BWTR3_DATAST_Pos)
7881#define FMC_BWTR3_DATAST_1 (0x02UL << FMC_BWTR3_DATAST_Pos)
7882#define FMC_BWTR3_DATAST_2 (0x04UL << FMC_BWTR3_DATAST_Pos)
7883#define FMC_BWTR3_DATAST_3 (0x08UL << FMC_BWTR3_DATAST_Pos)
7884#define FMC_BWTR3_DATAST_4 (0x10UL << FMC_BWTR3_DATAST_Pos)
7885#define FMC_BWTR3_DATAST_5 (0x20UL << FMC_BWTR3_DATAST_Pos)
7886#define FMC_BWTR3_DATAST_6 (0x40UL << FMC_BWTR3_DATAST_Pos)
7887#define FMC_BWTR3_DATAST_7 (0x80UL << FMC_BWTR3_DATAST_Pos)
7888
7889#define FMC_BWTR3_BUSTURN_Pos (16U)
7890#define FMC_BWTR3_BUSTURN_Msk (0xFUL << FMC_BWTR3_BUSTURN_Pos)
7891#define FMC_BWTR3_BUSTURN FMC_BWTR3_BUSTURN_Msk
7892#define FMC_BWTR3_BUSTURN_0 (0x1UL << FMC_BWTR3_BUSTURN_Pos)
7893#define FMC_BWTR3_BUSTURN_1 (0x2UL << FMC_BWTR3_BUSTURN_Pos)
7894#define FMC_BWTR3_BUSTURN_2 (0x4UL << FMC_BWTR3_BUSTURN_Pos)
7895#define FMC_BWTR3_BUSTURN_3 (0x8UL << FMC_BWTR3_BUSTURN_Pos)
7896
7897#define FMC_BWTR3_ACCMOD_Pos (28U)
7898#define FMC_BWTR3_ACCMOD_Msk (0x3UL << FMC_BWTR3_ACCMOD_Pos)
7899#define FMC_BWTR3_ACCMOD FMC_BWTR3_ACCMOD_Msk
7900#define FMC_BWTR3_ACCMOD_0 (0x1UL << FMC_BWTR3_ACCMOD_Pos)
7901#define FMC_BWTR3_ACCMOD_1 (0x2UL << FMC_BWTR3_ACCMOD_Pos)
7902
7903/****************** Bit definition for FMC_BWTR4 register ******************/
7904#define FMC_BWTR4_ADDSET_Pos (0U)
7905#define FMC_BWTR4_ADDSET_Msk (0xFUL << FMC_BWTR4_ADDSET_Pos)
7906#define FMC_BWTR4_ADDSET FMC_BWTR4_ADDSET_Msk
7907#define FMC_BWTR4_ADDSET_0 (0x1UL << FMC_BWTR4_ADDSET_Pos)
7908#define FMC_BWTR4_ADDSET_1 (0x2UL << FMC_BWTR4_ADDSET_Pos)
7909#define FMC_BWTR4_ADDSET_2 (0x4UL << FMC_BWTR4_ADDSET_Pos)
7910#define FMC_BWTR4_ADDSET_3 (0x8UL << FMC_BWTR4_ADDSET_Pos)
7911
7912#define FMC_BWTR4_ADDHLD_Pos (4U)
7913#define FMC_BWTR4_ADDHLD_Msk (0xFUL << FMC_BWTR4_ADDHLD_Pos)
7914#define FMC_BWTR4_ADDHLD FMC_BWTR4_ADDHLD_Msk
7915#define FMC_BWTR4_ADDHLD_0 (0x1UL << FMC_BWTR4_ADDHLD_Pos)
7916#define FMC_BWTR4_ADDHLD_1 (0x2UL << FMC_BWTR4_ADDHLD_Pos)
7917#define FMC_BWTR4_ADDHLD_2 (0x4UL << FMC_BWTR4_ADDHLD_Pos)
7918#define FMC_BWTR4_ADDHLD_3 (0x8UL << FMC_BWTR4_ADDHLD_Pos)
7919
7920#define FMC_BWTR4_DATAST_Pos (8U)
7921#define FMC_BWTR4_DATAST_Msk (0xFFUL << FMC_BWTR4_DATAST_Pos)
7922#define FMC_BWTR4_DATAST FMC_BWTR4_DATAST_Msk
7923#define FMC_BWTR4_DATAST_0 (0x01UL << FMC_BWTR4_DATAST_Pos)
7924#define FMC_BWTR4_DATAST_1 (0x02UL << FMC_BWTR4_DATAST_Pos)
7925#define FMC_BWTR4_DATAST_2 (0x04UL << FMC_BWTR4_DATAST_Pos)
7926#define FMC_BWTR4_DATAST_3 (0x08UL << FMC_BWTR4_DATAST_Pos)
7927#define FMC_BWTR4_DATAST_4 (0x10UL << FMC_BWTR4_DATAST_Pos)
7928#define FMC_BWTR4_DATAST_5 (0x20UL << FMC_BWTR4_DATAST_Pos)
7929#define FMC_BWTR4_DATAST_6 (0x40UL << FMC_BWTR4_DATAST_Pos)
7930#define FMC_BWTR4_DATAST_7 (0x80UL << FMC_BWTR4_DATAST_Pos)
7931
7932#define FMC_BWTR4_BUSTURN_Pos (16U)
7933#define FMC_BWTR4_BUSTURN_Msk (0xFUL << FMC_BWTR4_BUSTURN_Pos)
7934#define FMC_BWTR4_BUSTURN FMC_BWTR4_BUSTURN_Msk
7935#define FMC_BWTR4_BUSTURN_0 (0x1UL << FMC_BWTR4_BUSTURN_Pos)
7936#define FMC_BWTR4_BUSTURN_1 (0x2UL << FMC_BWTR4_BUSTURN_Pos)
7937#define FMC_BWTR4_BUSTURN_2 (0x4UL << FMC_BWTR4_BUSTURN_Pos)
7938#define FMC_BWTR4_BUSTURN_3 (0x8UL << FMC_BWTR4_BUSTURN_Pos)
7939
7940#define FMC_BWTR4_ACCMOD_Pos (28U)
7941#define FMC_BWTR4_ACCMOD_Msk (0x3UL << FMC_BWTR4_ACCMOD_Pos)
7942#define FMC_BWTR4_ACCMOD FMC_BWTR4_ACCMOD_Msk
7943#define FMC_BWTR4_ACCMOD_0 (0x1UL << FMC_BWTR4_ACCMOD_Pos)
7944#define FMC_BWTR4_ACCMOD_1 (0x2UL << FMC_BWTR4_ACCMOD_Pos)
7945
7946/****************** Bit definition for FMC_PCR2 register *******************/
7947
7948#define FMC_PCR2_PWAITEN_Pos (1U)
7949#define FMC_PCR2_PWAITEN_Msk (0x1UL << FMC_PCR2_PWAITEN_Pos)
7950#define FMC_PCR2_PWAITEN FMC_PCR2_PWAITEN_Msk
7951#define FMC_PCR2_PBKEN_Pos (2U)
7952#define FMC_PCR2_PBKEN_Msk (0x1UL << FMC_PCR2_PBKEN_Pos)
7953#define FMC_PCR2_PBKEN FMC_PCR2_PBKEN_Msk
7954#define FMC_PCR2_PTYP_Pos (3U)
7955#define FMC_PCR2_PTYP_Msk (0x1UL << FMC_PCR2_PTYP_Pos)
7956#define FMC_PCR2_PTYP FMC_PCR2_PTYP_Msk
7957
7958#define FMC_PCR2_PWID_Pos (4U)
7959#define FMC_PCR2_PWID_Msk (0x3UL << FMC_PCR2_PWID_Pos)
7960#define FMC_PCR2_PWID FMC_PCR2_PWID_Msk
7961#define FMC_PCR2_PWID_0 (0x1UL << FMC_PCR2_PWID_Pos)
7962#define FMC_PCR2_PWID_1 (0x2UL << FMC_PCR2_PWID_Pos)
7963
7964#define FMC_PCR2_ECCEN_Pos (6U)
7965#define FMC_PCR2_ECCEN_Msk (0x1UL << FMC_PCR2_ECCEN_Pos)
7966#define FMC_PCR2_ECCEN FMC_PCR2_ECCEN_Msk
7967
7968#define FMC_PCR2_TCLR_Pos (9U)
7969#define FMC_PCR2_TCLR_Msk (0xFUL << FMC_PCR2_TCLR_Pos)
7970#define FMC_PCR2_TCLR FMC_PCR2_TCLR_Msk
7971#define FMC_PCR2_TCLR_0 (0x1UL << FMC_PCR2_TCLR_Pos)
7972#define FMC_PCR2_TCLR_1 (0x2UL << FMC_PCR2_TCLR_Pos)
7973#define FMC_PCR2_TCLR_2 (0x4UL << FMC_PCR2_TCLR_Pos)
7974#define FMC_PCR2_TCLR_3 (0x8UL << FMC_PCR2_TCLR_Pos)
7975
7976#define FMC_PCR2_TAR_Pos (13U)
7977#define FMC_PCR2_TAR_Msk (0xFUL << FMC_PCR2_TAR_Pos)
7978#define FMC_PCR2_TAR FMC_PCR2_TAR_Msk
7979#define FMC_PCR2_TAR_0 (0x1UL << FMC_PCR2_TAR_Pos)
7980#define FMC_PCR2_TAR_1 (0x2UL << FMC_PCR2_TAR_Pos)
7981#define FMC_PCR2_TAR_2 (0x4UL << FMC_PCR2_TAR_Pos)
7982#define FMC_PCR2_TAR_3 (0x8UL << FMC_PCR2_TAR_Pos)
7983
7984#define FMC_PCR2_ECCPS_Pos (17U)
7985#define FMC_PCR2_ECCPS_Msk (0x7UL << FMC_PCR2_ECCPS_Pos)
7986#define FMC_PCR2_ECCPS FMC_PCR2_ECCPS_Msk
7987#define FMC_PCR2_ECCPS_0 (0x1UL << FMC_PCR2_ECCPS_Pos)
7988#define FMC_PCR2_ECCPS_1 (0x2UL << FMC_PCR2_ECCPS_Pos)
7989#define FMC_PCR2_ECCPS_2 (0x4UL << FMC_PCR2_ECCPS_Pos)
7990
7991/****************** Bit definition for FMC_PCR3 register *******************/
7992#define FMC_PCR3_PWAITEN_Pos (1U)
7993#define FMC_PCR3_PWAITEN_Msk (0x1UL << FMC_PCR3_PWAITEN_Pos)
7994#define FMC_PCR3_PWAITEN FMC_PCR3_PWAITEN_Msk
7995#define FMC_PCR3_PBKEN_Pos (2U)
7996#define FMC_PCR3_PBKEN_Msk (0x1UL << FMC_PCR3_PBKEN_Pos)
7997#define FMC_PCR3_PBKEN FMC_PCR3_PBKEN_Msk
7998#define FMC_PCR3_PTYP_Pos (3U)
7999#define FMC_PCR3_PTYP_Msk (0x1UL << FMC_PCR3_PTYP_Pos)
8000#define FMC_PCR3_PTYP FMC_PCR3_PTYP_Msk
8001
8002#define FMC_PCR3_PWID_Pos (4U)
8003#define FMC_PCR3_PWID_Msk (0x3UL << FMC_PCR3_PWID_Pos)
8004#define FMC_PCR3_PWID FMC_PCR3_PWID_Msk
8005#define FMC_PCR3_PWID_0 (0x1UL << FMC_PCR3_PWID_Pos)
8006#define FMC_PCR3_PWID_1 (0x2UL << FMC_PCR3_PWID_Pos)
8007
8008#define FMC_PCR3_ECCEN_Pos (6U)
8009#define FMC_PCR3_ECCEN_Msk (0x1UL << FMC_PCR3_ECCEN_Pos)
8010#define FMC_PCR3_ECCEN FMC_PCR3_ECCEN_Msk
8011
8012#define FMC_PCR3_TCLR_Pos (9U)
8013#define FMC_PCR3_TCLR_Msk (0xFUL << FMC_PCR3_TCLR_Pos)
8014#define FMC_PCR3_TCLR FMC_PCR3_TCLR_Msk
8015#define FMC_PCR3_TCLR_0 (0x1UL << FMC_PCR3_TCLR_Pos)
8016#define FMC_PCR3_TCLR_1 (0x2UL << FMC_PCR3_TCLR_Pos)
8017#define FMC_PCR3_TCLR_2 (0x4UL << FMC_PCR3_TCLR_Pos)
8018#define FMC_PCR3_TCLR_3 (0x8UL << FMC_PCR3_TCLR_Pos)
8019
8020#define FMC_PCR3_TAR_Pos (13U)
8021#define FMC_PCR3_TAR_Msk (0xFUL << FMC_PCR3_TAR_Pos)
8022#define FMC_PCR3_TAR FMC_PCR3_TAR_Msk
8023#define FMC_PCR3_TAR_0 (0x1UL << FMC_PCR3_TAR_Pos)
8024#define FMC_PCR3_TAR_1 (0x2UL << FMC_PCR3_TAR_Pos)
8025#define FMC_PCR3_TAR_2 (0x4UL << FMC_PCR3_TAR_Pos)
8026#define FMC_PCR3_TAR_3 (0x8UL << FMC_PCR3_TAR_Pos)
8027
8028#define FMC_PCR3_ECCPS_Pos (17U)
8029#define FMC_PCR3_ECCPS_Msk (0x7UL << FMC_PCR3_ECCPS_Pos)
8030#define FMC_PCR3_ECCPS FMC_PCR3_ECCPS_Msk
8031#define FMC_PCR3_ECCPS_0 (0x1UL << FMC_PCR3_ECCPS_Pos)
8032#define FMC_PCR3_ECCPS_1 (0x2UL << FMC_PCR3_ECCPS_Pos)
8033#define FMC_PCR3_ECCPS_2 (0x4UL << FMC_PCR3_ECCPS_Pos)
8034
8035/****************** Bit definition for FMC_PCR4 register *******************/
8036#define FMC_PCR4_PWAITEN_Pos (1U)
8037#define FMC_PCR4_PWAITEN_Msk (0x1UL << FMC_PCR4_PWAITEN_Pos)
8038#define FMC_PCR4_PWAITEN FMC_PCR4_PWAITEN_Msk
8039#define FMC_PCR4_PBKEN_Pos (2U)
8040#define FMC_PCR4_PBKEN_Msk (0x1UL << FMC_PCR4_PBKEN_Pos)
8041#define FMC_PCR4_PBKEN FMC_PCR4_PBKEN_Msk
8042#define FMC_PCR4_PTYP_Pos (3U)
8043#define FMC_PCR4_PTYP_Msk (0x1UL << FMC_PCR4_PTYP_Pos)
8044#define FMC_PCR4_PTYP FMC_PCR4_PTYP_Msk
8045
8046#define FMC_PCR4_PWID_Pos (4U)
8047#define FMC_PCR4_PWID_Msk (0x3UL << FMC_PCR4_PWID_Pos)
8048#define FMC_PCR4_PWID FMC_PCR4_PWID_Msk
8049#define FMC_PCR4_PWID_0 (0x1UL << FMC_PCR4_PWID_Pos)
8050#define FMC_PCR4_PWID_1 (0x2UL << FMC_PCR4_PWID_Pos)
8051
8052#define FMC_PCR4_ECCEN_Pos (6U)
8053#define FMC_PCR4_ECCEN_Msk (0x1UL << FMC_PCR4_ECCEN_Pos)
8054#define FMC_PCR4_ECCEN FMC_PCR4_ECCEN_Msk
8055
8056#define FMC_PCR4_TCLR_Pos (9U)
8057#define FMC_PCR4_TCLR_Msk (0xFUL << FMC_PCR4_TCLR_Pos)
8058#define FMC_PCR4_TCLR FMC_PCR4_TCLR_Msk
8059#define FMC_PCR4_TCLR_0 (0x1UL << FMC_PCR4_TCLR_Pos)
8060#define FMC_PCR4_TCLR_1 (0x2UL << FMC_PCR4_TCLR_Pos)
8061#define FMC_PCR4_TCLR_2 (0x4UL << FMC_PCR4_TCLR_Pos)
8062#define FMC_PCR4_TCLR_3 (0x8UL << FMC_PCR4_TCLR_Pos)
8063
8064#define FMC_PCR4_TAR_Pos (13U)
8065#define FMC_PCR4_TAR_Msk (0xFUL << FMC_PCR4_TAR_Pos)
8066#define FMC_PCR4_TAR FMC_PCR4_TAR_Msk
8067#define FMC_PCR4_TAR_0 (0x1UL << FMC_PCR4_TAR_Pos)
8068#define FMC_PCR4_TAR_1 (0x2UL << FMC_PCR4_TAR_Pos)
8069#define FMC_PCR4_TAR_2 (0x4UL << FMC_PCR4_TAR_Pos)
8070#define FMC_PCR4_TAR_3 (0x8UL << FMC_PCR4_TAR_Pos)
8071
8072#define FMC_PCR4_ECCPS_Pos (17U)
8073#define FMC_PCR4_ECCPS_Msk (0x7UL << FMC_PCR4_ECCPS_Pos)
8074#define FMC_PCR4_ECCPS FMC_PCR4_ECCPS_Msk
8075#define FMC_PCR4_ECCPS_0 (0x1UL << FMC_PCR4_ECCPS_Pos)
8076#define FMC_PCR4_ECCPS_1 (0x2UL << FMC_PCR4_ECCPS_Pos)
8077#define FMC_PCR4_ECCPS_2 (0x4UL << FMC_PCR4_ECCPS_Pos)
8078
8079/******************* Bit definition for FMC_SR2 register *******************/
8080#define FMC_SR2_IRS_Pos (0U)
8081#define FMC_SR2_IRS_Msk (0x1UL << FMC_SR2_IRS_Pos)
8082#define FMC_SR2_IRS FMC_SR2_IRS_Msk
8083#define FMC_SR2_ILS_Pos (1U)
8084#define FMC_SR2_ILS_Msk (0x1UL << FMC_SR2_ILS_Pos)
8085#define FMC_SR2_ILS FMC_SR2_ILS_Msk
8086#define FMC_SR2_IFS_Pos (2U)
8087#define FMC_SR2_IFS_Msk (0x1UL << FMC_SR2_IFS_Pos)
8088#define FMC_SR2_IFS FMC_SR2_IFS_Msk
8089#define FMC_SR2_IREN_Pos (3U)
8090#define FMC_SR2_IREN_Msk (0x1UL << FMC_SR2_IREN_Pos)
8091#define FMC_SR2_IREN FMC_SR2_IREN_Msk
8092#define FMC_SR2_ILEN_Pos (4U)
8093#define FMC_SR2_ILEN_Msk (0x1UL << FMC_SR2_ILEN_Pos)
8094#define FMC_SR2_ILEN FMC_SR2_ILEN_Msk
8095#define FMC_SR2_IFEN_Pos (5U)
8096#define FMC_SR2_IFEN_Msk (0x1UL << FMC_SR2_IFEN_Pos)
8097#define FMC_SR2_IFEN FMC_SR2_IFEN_Msk
8098#define FMC_SR2_FEMPT_Pos (6U)
8099#define FMC_SR2_FEMPT_Msk (0x1UL << FMC_SR2_FEMPT_Pos)
8100#define FMC_SR2_FEMPT FMC_SR2_FEMPT_Msk
8101
8102/******************* Bit definition for FMC_SR3 register *******************/
8103#define FMC_SR3_IRS_Pos (0U)
8104#define FMC_SR3_IRS_Msk (0x1UL << FMC_SR3_IRS_Pos)
8105#define FMC_SR3_IRS FMC_SR3_IRS_Msk
8106#define FMC_SR3_ILS_Pos (1U)
8107#define FMC_SR3_ILS_Msk (0x1UL << FMC_SR3_ILS_Pos)
8108#define FMC_SR3_ILS FMC_SR3_ILS_Msk
8109#define FMC_SR3_IFS_Pos (2U)
8110#define FMC_SR3_IFS_Msk (0x1UL << FMC_SR3_IFS_Pos)
8111#define FMC_SR3_IFS FMC_SR3_IFS_Msk
8112#define FMC_SR3_IREN_Pos (3U)
8113#define FMC_SR3_IREN_Msk (0x1UL << FMC_SR3_IREN_Pos)
8114#define FMC_SR3_IREN FMC_SR3_IREN_Msk
8115#define FMC_SR3_ILEN_Pos (4U)
8116#define FMC_SR3_ILEN_Msk (0x1UL << FMC_SR3_ILEN_Pos)
8117#define FMC_SR3_ILEN FMC_SR3_ILEN_Msk
8118#define FMC_SR3_IFEN_Pos (5U)
8119#define FMC_SR3_IFEN_Msk (0x1UL << FMC_SR3_IFEN_Pos)
8120#define FMC_SR3_IFEN FMC_SR3_IFEN_Msk
8121#define FMC_SR3_FEMPT_Pos (6U)
8122#define FMC_SR3_FEMPT_Msk (0x1UL << FMC_SR3_FEMPT_Pos)
8123#define FMC_SR3_FEMPT FMC_SR3_FEMPT_Msk
8124
8125/******************* Bit definition for FMC_SR4 register *******************/
8126#define FMC_SR4_IRS_Pos (0U)
8127#define FMC_SR4_IRS_Msk (0x1UL << FMC_SR4_IRS_Pos)
8128#define FMC_SR4_IRS FMC_SR4_IRS_Msk
8129#define FMC_SR4_ILS_Pos (1U)
8130#define FMC_SR4_ILS_Msk (0x1UL << FMC_SR4_ILS_Pos)
8131#define FMC_SR4_ILS FMC_SR4_ILS_Msk
8132#define FMC_SR4_IFS_Pos (2U)
8133#define FMC_SR4_IFS_Msk (0x1UL << FMC_SR4_IFS_Pos)
8134#define FMC_SR4_IFS FMC_SR4_IFS_Msk
8135#define FMC_SR4_IREN_Pos (3U)
8136#define FMC_SR4_IREN_Msk (0x1UL << FMC_SR4_IREN_Pos)
8137#define FMC_SR4_IREN FMC_SR4_IREN_Msk
8138#define FMC_SR4_ILEN_Pos (4U)
8139#define FMC_SR4_ILEN_Msk (0x1UL << FMC_SR4_ILEN_Pos)
8140#define FMC_SR4_ILEN FMC_SR4_ILEN_Msk
8141#define FMC_SR4_IFEN_Pos (5U)
8142#define FMC_SR4_IFEN_Msk (0x1UL << FMC_SR4_IFEN_Pos)
8143#define FMC_SR4_IFEN FMC_SR4_IFEN_Msk
8144#define FMC_SR4_FEMPT_Pos (6U)
8145#define FMC_SR4_FEMPT_Msk (0x1UL << FMC_SR4_FEMPT_Pos)
8146#define FMC_SR4_FEMPT FMC_SR4_FEMPT_Msk
8147
8148/****************** Bit definition for FMC_PMEM2 register ******************/
8149#define FMC_PMEM2_MEMSET2_Pos (0U)
8150#define FMC_PMEM2_MEMSET2_Msk (0xFFUL << FMC_PMEM2_MEMSET2_Pos)
8151#define FMC_PMEM2_MEMSET2 FMC_PMEM2_MEMSET2_Msk
8152#define FMC_PMEM2_MEMSET2_0 (0x01UL << FMC_PMEM2_MEMSET2_Pos)
8153#define FMC_PMEM2_MEMSET2_1 (0x02UL << FMC_PMEM2_MEMSET2_Pos)
8154#define FMC_PMEM2_MEMSET2_2 (0x04UL << FMC_PMEM2_MEMSET2_Pos)
8155#define FMC_PMEM2_MEMSET2_3 (0x08UL << FMC_PMEM2_MEMSET2_Pos)
8156#define FMC_PMEM2_MEMSET2_4 (0x10UL << FMC_PMEM2_MEMSET2_Pos)
8157#define FMC_PMEM2_MEMSET2_5 (0x20UL << FMC_PMEM2_MEMSET2_Pos)
8158#define FMC_PMEM2_MEMSET2_6 (0x40UL << FMC_PMEM2_MEMSET2_Pos)
8159#define FMC_PMEM2_MEMSET2_7 (0x80UL << FMC_PMEM2_MEMSET2_Pos)
8160
8161#define FMC_PMEM2_MEMWAIT2_Pos (8U)
8162#define FMC_PMEM2_MEMWAIT2_Msk (0xFFUL << FMC_PMEM2_MEMWAIT2_Pos)
8163#define FMC_PMEM2_MEMWAIT2 FMC_PMEM2_MEMWAIT2_Msk
8164#define FMC_PMEM2_MEMWAIT2_0 (0x01UL << FMC_PMEM2_MEMWAIT2_Pos)
8165#define FMC_PMEM2_MEMWAIT2_1 (0x02UL << FMC_PMEM2_MEMWAIT2_Pos)
8166#define FMC_PMEM2_MEMWAIT2_2 (0x04UL << FMC_PMEM2_MEMWAIT2_Pos)
8167#define FMC_PMEM2_MEMWAIT2_3 (0x08UL << FMC_PMEM2_MEMWAIT2_Pos)
8168#define FMC_PMEM2_MEMWAIT2_4 (0x10UL << FMC_PMEM2_MEMWAIT2_Pos)
8169#define FMC_PMEM2_MEMWAIT2_5 (0x20UL << FMC_PMEM2_MEMWAIT2_Pos)
8170#define FMC_PMEM2_MEMWAIT2_6 (0x40UL << FMC_PMEM2_MEMWAIT2_Pos)
8171#define FMC_PMEM2_MEMWAIT2_7 (0x80UL << FMC_PMEM2_MEMWAIT2_Pos)
8172
8173#define FMC_PMEM2_MEMHOLD2_Pos (16U)
8174#define FMC_PMEM2_MEMHOLD2_Msk (0xFFUL << FMC_PMEM2_MEMHOLD2_Pos)
8175#define FMC_PMEM2_MEMHOLD2 FMC_PMEM2_MEMHOLD2_Msk
8176#define FMC_PMEM2_MEMHOLD2_0 (0x01UL << FMC_PMEM2_MEMHOLD2_Pos)
8177#define FMC_PMEM2_MEMHOLD2_1 (0x02UL << FMC_PMEM2_MEMHOLD2_Pos)
8178#define FMC_PMEM2_MEMHOLD2_2 (0x04UL << FMC_PMEM2_MEMHOLD2_Pos)
8179#define FMC_PMEM2_MEMHOLD2_3 (0x08UL << FMC_PMEM2_MEMHOLD2_Pos)
8180#define FMC_PMEM2_MEMHOLD2_4 (0x10UL << FMC_PMEM2_MEMHOLD2_Pos)
8181#define FMC_PMEM2_MEMHOLD2_5 (0x20UL << FMC_PMEM2_MEMHOLD2_Pos)
8182#define FMC_PMEM2_MEMHOLD2_6 (0x40UL << FMC_PMEM2_MEMHOLD2_Pos)
8183#define FMC_PMEM2_MEMHOLD2_7 (0x80UL << FMC_PMEM2_MEMHOLD2_Pos)
8184
8185#define FMC_PMEM2_MEMHIZ2_Pos (24U)
8186#define FMC_PMEM2_MEMHIZ2_Msk (0xFFUL << FMC_PMEM2_MEMHIZ2_Pos)
8187#define FMC_PMEM2_MEMHIZ2 FMC_PMEM2_MEMHIZ2_Msk
8188#define FMC_PMEM2_MEMHIZ2_0 (0x01UL << FMC_PMEM2_MEMHIZ2_Pos)
8189#define FMC_PMEM2_MEMHIZ2_1 (0x02UL << FMC_PMEM2_MEMHIZ2_Pos)
8190#define FMC_PMEM2_MEMHIZ2_2 (0x04UL << FMC_PMEM2_MEMHIZ2_Pos)
8191#define FMC_PMEM2_MEMHIZ2_3 (0x08UL << FMC_PMEM2_MEMHIZ2_Pos)
8192#define FMC_PMEM2_MEMHIZ2_4 (0x10UL << FMC_PMEM2_MEMHIZ2_Pos)
8193#define FMC_PMEM2_MEMHIZ2_5 (0x20UL << FMC_PMEM2_MEMHIZ2_Pos)
8194#define FMC_PMEM2_MEMHIZ2_6 (0x40UL << FMC_PMEM2_MEMHIZ2_Pos)
8195#define FMC_PMEM2_MEMHIZ2_7 (0x80UL << FMC_PMEM2_MEMHIZ2_Pos)
8196
8197/****************** Bit definition for FMC_PMEM3 register ******************/
8198#define FMC_PMEM3_MEMSET3_Pos (0U)
8199#define FMC_PMEM3_MEMSET3_Msk (0xFFUL << FMC_PMEM3_MEMSET3_Pos)
8200#define FMC_PMEM3_MEMSET3 FMC_PMEM3_MEMSET3_Msk
8201#define FMC_PMEM3_MEMSET3_0 (0x01UL << FMC_PMEM3_MEMSET3_Pos)
8202#define FMC_PMEM3_MEMSET3_1 (0x02UL << FMC_PMEM3_MEMSET3_Pos)
8203#define FMC_PMEM3_MEMSET3_2 (0x04UL << FMC_PMEM3_MEMSET3_Pos)
8204#define FMC_PMEM3_MEMSET3_3 (0x08UL << FMC_PMEM3_MEMSET3_Pos)
8205#define FMC_PMEM3_MEMSET3_4 (0x10UL << FMC_PMEM3_MEMSET3_Pos)
8206#define FMC_PMEM3_MEMSET3_5 (0x20UL << FMC_PMEM3_MEMSET3_Pos)
8207#define FMC_PMEM3_MEMSET3_6 (0x40UL << FMC_PMEM3_MEMSET3_Pos)
8208#define FMC_PMEM3_MEMSET3_7 (0x80UL << FMC_PMEM3_MEMSET3_Pos)
8209
8210#define FMC_PMEM3_MEMWAIT3_Pos (8U)
8211#define FMC_PMEM3_MEMWAIT3_Msk (0xFFUL << FMC_PMEM3_MEMWAIT3_Pos)
8212#define FMC_PMEM3_MEMWAIT3 FMC_PMEM3_MEMWAIT3_Msk
8213#define FMC_PMEM3_MEMWAIT3_0 (0x01UL << FMC_PMEM3_MEMWAIT3_Pos)
8214#define FMC_PMEM3_MEMWAIT3_1 (0x02UL << FMC_PMEM3_MEMWAIT3_Pos)
8215#define FMC_PMEM3_MEMWAIT3_2 (0x04UL << FMC_PMEM3_MEMWAIT3_Pos)
8216#define FMC_PMEM3_MEMWAIT3_3 (0x08UL << FMC_PMEM3_MEMWAIT3_Pos)
8217#define FMC_PMEM3_MEMWAIT3_4 (0x10UL << FMC_PMEM3_MEMWAIT3_Pos)
8218#define FMC_PMEM3_MEMWAIT3_5 (0x20UL << FMC_PMEM3_MEMWAIT3_Pos)
8219#define FMC_PMEM3_MEMWAIT3_6 (0x40UL << FMC_PMEM3_MEMWAIT3_Pos)
8220#define FMC_PMEM3_MEMWAIT3_7 (0x80UL << FMC_PMEM3_MEMWAIT3_Pos)
8221
8222#define FMC_PMEM3_MEMHOLD3_Pos (16U)
8223#define FMC_PMEM3_MEMHOLD3_Msk (0xFFUL << FMC_PMEM3_MEMHOLD3_Pos)
8224#define FMC_PMEM3_MEMHOLD3 FMC_PMEM3_MEMHOLD3_Msk
8225#define FMC_PMEM3_MEMHOLD3_0 (0x01UL << FMC_PMEM3_MEMHOLD3_Pos)
8226#define FMC_PMEM3_MEMHOLD3_1 (0x02UL << FMC_PMEM3_MEMHOLD3_Pos)
8227#define FMC_PMEM3_MEMHOLD3_2 (0x04UL << FMC_PMEM3_MEMHOLD3_Pos)
8228#define FMC_PMEM3_MEMHOLD3_3 (0x08UL << FMC_PMEM3_MEMHOLD3_Pos)
8229#define FMC_PMEM3_MEMHOLD3_4 (0x10UL << FMC_PMEM3_MEMHOLD3_Pos)
8230#define FMC_PMEM3_MEMHOLD3_5 (0x20UL << FMC_PMEM3_MEMHOLD3_Pos)
8231#define FMC_PMEM3_MEMHOLD3_6 (0x40UL << FMC_PMEM3_MEMHOLD3_Pos)
8232#define FMC_PMEM3_MEMHOLD3_7 (0x80UL << FMC_PMEM3_MEMHOLD3_Pos)
8233
8234#define FMC_PMEM3_MEMHIZ3_Pos (24U)
8235#define FMC_PMEM3_MEMHIZ3_Msk (0xFFUL << FMC_PMEM3_MEMHIZ3_Pos)
8236#define FMC_PMEM3_MEMHIZ3 FMC_PMEM3_MEMHIZ3_Msk
8237#define FMC_PMEM3_MEMHIZ3_0 (0x01UL << FMC_PMEM3_MEMHIZ3_Pos)
8238#define FMC_PMEM3_MEMHIZ3_1 (0x02UL << FMC_PMEM3_MEMHIZ3_Pos)
8239#define FMC_PMEM3_MEMHIZ3_2 (0x04UL << FMC_PMEM3_MEMHIZ3_Pos)
8240#define FMC_PMEM3_MEMHIZ3_3 (0x08UL << FMC_PMEM3_MEMHIZ3_Pos)
8241#define FMC_PMEM3_MEMHIZ3_4 (0x10UL << FMC_PMEM3_MEMHIZ3_Pos)
8242#define FMC_PMEM3_MEMHIZ3_5 (0x20UL << FMC_PMEM3_MEMHIZ3_Pos)
8243#define FMC_PMEM3_MEMHIZ3_6 (0x40UL << FMC_PMEM3_MEMHIZ3_Pos)
8244#define FMC_PMEM3_MEMHIZ3_7 (0x80UL << FMC_PMEM3_MEMHIZ3_Pos)
8245
8246/****************** Bit definition for FMC_PMEM4 register ******************/
8247#define FMC_PMEM4_MEMSET4_Pos (0U)
8248#define FMC_PMEM4_MEMSET4_Msk (0xFFUL << FMC_PMEM4_MEMSET4_Pos)
8249#define FMC_PMEM4_MEMSET4 FMC_PMEM4_MEMSET4_Msk
8250#define FMC_PMEM4_MEMSET4_0 (0x01UL << FMC_PMEM4_MEMSET4_Pos)
8251#define FMC_PMEM4_MEMSET4_1 (0x02UL << FMC_PMEM4_MEMSET4_Pos)
8252#define FMC_PMEM4_MEMSET4_2 (0x04UL << FMC_PMEM4_MEMSET4_Pos)
8253#define FMC_PMEM4_MEMSET4_3 (0x08UL << FMC_PMEM4_MEMSET4_Pos)
8254#define FMC_PMEM4_MEMSET4_4 (0x10UL << FMC_PMEM4_MEMSET4_Pos)
8255#define FMC_PMEM4_MEMSET4_5 (0x20UL << FMC_PMEM4_MEMSET4_Pos)
8256#define FMC_PMEM4_MEMSET4_6 (0x40UL << FMC_PMEM4_MEMSET4_Pos)
8257#define FMC_PMEM4_MEMSET4_7 (0x80UL << FMC_PMEM4_MEMSET4_Pos)
8258
8259#define FMC_PMEM4_MEMWAIT4_Pos (8U)
8260#define FMC_PMEM4_MEMWAIT4_Msk (0xFFUL << FMC_PMEM4_MEMWAIT4_Pos)
8261#define FMC_PMEM4_MEMWAIT4 FMC_PMEM4_MEMWAIT4_Msk
8262#define FMC_PMEM4_MEMWAIT4_0 (0x01UL << FMC_PMEM4_MEMWAIT4_Pos)
8263#define FMC_PMEM4_MEMWAIT4_1 (0x02UL << FMC_PMEM4_MEMWAIT4_Pos)
8264#define FMC_PMEM4_MEMWAIT4_2 (0x04UL << FMC_PMEM4_MEMWAIT4_Pos)
8265#define FMC_PMEM4_MEMWAIT4_3 (0x08UL << FMC_PMEM4_MEMWAIT4_Pos)
8266#define FMC_PMEM4_MEMWAIT4_4 (0x10UL << FMC_PMEM4_MEMWAIT4_Pos)
8267#define FMC_PMEM4_MEMWAIT4_5 (0x20UL << FMC_PMEM4_MEMWAIT4_Pos)
8268#define FMC_PMEM4_MEMWAIT4_6 (0x40UL << FMC_PMEM4_MEMWAIT4_Pos)
8269#define FMC_PMEM4_MEMWAIT4_7 (0x80UL << FMC_PMEM4_MEMWAIT4_Pos)
8270
8271#define FMC_PMEM4_MEMHOLD4_Pos (16U)
8272#define FMC_PMEM4_MEMHOLD4_Msk (0xFFUL << FMC_PMEM4_MEMHOLD4_Pos)
8273#define FMC_PMEM4_MEMHOLD4 FMC_PMEM4_MEMHOLD4_Msk
8274#define FMC_PMEM4_MEMHOLD4_0 (0x01UL << FMC_PMEM4_MEMHOLD4_Pos)
8275#define FMC_PMEM4_MEMHOLD4_1 (0x02UL << FMC_PMEM4_MEMHOLD4_Pos)
8276#define FMC_PMEM4_MEMHOLD4_2 (0x04UL << FMC_PMEM4_MEMHOLD4_Pos)
8277#define FMC_PMEM4_MEMHOLD4_3 (0x08UL << FMC_PMEM4_MEMHOLD4_Pos)
8278#define FMC_PMEM4_MEMHOLD4_4 (0x10UL << FMC_PMEM4_MEMHOLD4_Pos)
8279#define FMC_PMEM4_MEMHOLD4_5 (0x20UL << FMC_PMEM4_MEMHOLD4_Pos)
8280#define FMC_PMEM4_MEMHOLD4_6 (0x40UL << FMC_PMEM4_MEMHOLD4_Pos)
8281#define FMC_PMEM4_MEMHOLD4_7 (0x80UL << FMC_PMEM4_MEMHOLD4_Pos)
8282
8283#define FMC_PMEM4_MEMHIZ4_Pos (24U)
8284#define FMC_PMEM4_MEMHIZ4_Msk (0xFFUL << FMC_PMEM4_MEMHIZ4_Pos)
8285#define FMC_PMEM4_MEMHIZ4 FMC_PMEM4_MEMHIZ4_Msk
8286#define FMC_PMEM4_MEMHIZ4_0 (0x01UL << FMC_PMEM4_MEMHIZ4_Pos)
8287#define FMC_PMEM4_MEMHIZ4_1 (0x02UL << FMC_PMEM4_MEMHIZ4_Pos)
8288#define FMC_PMEM4_MEMHIZ4_2 (0x04UL << FMC_PMEM4_MEMHIZ4_Pos)
8289#define FMC_PMEM4_MEMHIZ4_3 (0x08UL << FMC_PMEM4_MEMHIZ4_Pos)
8290#define FMC_PMEM4_MEMHIZ4_4 (0x10UL << FMC_PMEM4_MEMHIZ4_Pos)
8291#define FMC_PMEM4_MEMHIZ4_5 (0x20UL << FMC_PMEM4_MEMHIZ4_Pos)
8292#define FMC_PMEM4_MEMHIZ4_6 (0x40UL << FMC_PMEM4_MEMHIZ4_Pos)
8293#define FMC_PMEM4_MEMHIZ4_7 (0x80UL << FMC_PMEM4_MEMHIZ4_Pos)
8294
8295/****************** Bit definition for FMC_PATT2 register ******************/
8296#define FMC_PATT2_ATTSET2_Pos (0U)
8297#define FMC_PATT2_ATTSET2_Msk (0xFFUL << FMC_PATT2_ATTSET2_Pos)
8298#define FMC_PATT2_ATTSET2 FMC_PATT2_ATTSET2_Msk
8299#define FMC_PATT2_ATTSET2_0 (0x01UL << FMC_PATT2_ATTSET2_Pos)
8300#define FMC_PATT2_ATTSET2_1 (0x02UL << FMC_PATT2_ATTSET2_Pos)
8301#define FMC_PATT2_ATTSET2_2 (0x04UL << FMC_PATT2_ATTSET2_Pos)
8302#define FMC_PATT2_ATTSET2_3 (0x08UL << FMC_PATT2_ATTSET2_Pos)
8303#define FMC_PATT2_ATTSET2_4 (0x10UL << FMC_PATT2_ATTSET2_Pos)
8304#define FMC_PATT2_ATTSET2_5 (0x20UL << FMC_PATT2_ATTSET2_Pos)
8305#define FMC_PATT2_ATTSET2_6 (0x40UL << FMC_PATT2_ATTSET2_Pos)
8306#define FMC_PATT2_ATTSET2_7 (0x80UL << FMC_PATT2_ATTSET2_Pos)
8307
8308#define FMC_PATT2_ATTWAIT2_Pos (8U)
8309#define FMC_PATT2_ATTWAIT2_Msk (0xFFUL << FMC_PATT2_ATTWAIT2_Pos)
8310#define FMC_PATT2_ATTWAIT2 FMC_PATT2_ATTWAIT2_Msk
8311#define FMC_PATT2_ATTWAIT2_0 (0x01UL << FMC_PATT2_ATTWAIT2_Pos)
8312#define FMC_PATT2_ATTWAIT2_1 (0x02UL << FMC_PATT2_ATTWAIT2_Pos)
8313#define FMC_PATT2_ATTWAIT2_2 (0x04UL << FMC_PATT2_ATTWAIT2_Pos)
8314#define FMC_PATT2_ATTWAIT2_3 (0x08UL << FMC_PATT2_ATTWAIT2_Pos)
8315#define FMC_PATT2_ATTWAIT2_4 (0x10UL << FMC_PATT2_ATTWAIT2_Pos)
8316#define FMC_PATT2_ATTWAIT2_5 (0x20UL << FMC_PATT2_ATTWAIT2_Pos)
8317#define FMC_PATT2_ATTWAIT2_6 (0x40UL << FMC_PATT2_ATTWAIT2_Pos)
8318#define FMC_PATT2_ATTWAIT2_7 (0x80UL << FMC_PATT2_ATTWAIT2_Pos)
8319
8320#define FMC_PATT2_ATTHOLD2_Pos (16U)
8321#define FMC_PATT2_ATTHOLD2_Msk (0xFFUL << FMC_PATT2_ATTHOLD2_Pos)
8322#define FMC_PATT2_ATTHOLD2 FMC_PATT2_ATTHOLD2_Msk
8323#define FMC_PATT2_ATTHOLD2_0 (0x01UL << FMC_PATT2_ATTHOLD2_Pos)
8324#define FMC_PATT2_ATTHOLD2_1 (0x02UL << FMC_PATT2_ATTHOLD2_Pos)
8325#define FMC_PATT2_ATTHOLD2_2 (0x04UL << FMC_PATT2_ATTHOLD2_Pos)
8326#define FMC_PATT2_ATTHOLD2_3 (0x08UL << FMC_PATT2_ATTHOLD2_Pos)
8327#define FMC_PATT2_ATTHOLD2_4 (0x10UL << FMC_PATT2_ATTHOLD2_Pos)
8328#define FMC_PATT2_ATTHOLD2_5 (0x20UL << FMC_PATT2_ATTHOLD2_Pos)
8329#define FMC_PATT2_ATTHOLD2_6 (0x40UL << FMC_PATT2_ATTHOLD2_Pos)
8330#define FMC_PATT2_ATTHOLD2_7 (0x80UL << FMC_PATT2_ATTHOLD2_Pos)
8331
8332#define FMC_PATT2_ATTHIZ2_Pos (24U)
8333#define FMC_PATT2_ATTHIZ2_Msk (0xFFUL << FMC_PATT2_ATTHIZ2_Pos)
8334#define FMC_PATT2_ATTHIZ2 FMC_PATT2_ATTHIZ2_Msk
8335#define FMC_PATT2_ATTHIZ2_0 (0x01UL << FMC_PATT2_ATTHIZ2_Pos)
8336#define FMC_PATT2_ATTHIZ2_1 (0x02UL << FMC_PATT2_ATTHIZ2_Pos)
8337#define FMC_PATT2_ATTHIZ2_2 (0x04UL << FMC_PATT2_ATTHIZ2_Pos)
8338#define FMC_PATT2_ATTHIZ2_3 (0x08UL << FMC_PATT2_ATTHIZ2_Pos)
8339#define FMC_PATT2_ATTHIZ2_4 (0x10UL << FMC_PATT2_ATTHIZ2_Pos)
8340#define FMC_PATT2_ATTHIZ2_5 (0x20UL << FMC_PATT2_ATTHIZ2_Pos)
8341#define FMC_PATT2_ATTHIZ2_6 (0x40UL << FMC_PATT2_ATTHIZ2_Pos)
8342#define FMC_PATT2_ATTHIZ2_7 (0x80UL << FMC_PATT2_ATTHIZ2_Pos)
8343
8344/****************** Bit definition for FMC_PATT3 register ******************/
8345#define FMC_PATT3_ATTSET3_Pos (0U)
8346#define FMC_PATT3_ATTSET3_Msk (0xFFUL << FMC_PATT3_ATTSET3_Pos)
8347#define FMC_PATT3_ATTSET3 FMC_PATT3_ATTSET3_Msk
8348#define FMC_PATT3_ATTSET3_0 (0x01UL << FMC_PATT3_ATTSET3_Pos)
8349#define FMC_PATT3_ATTSET3_1 (0x02UL << FMC_PATT3_ATTSET3_Pos)
8350#define FMC_PATT3_ATTSET3_2 (0x04UL << FMC_PATT3_ATTSET3_Pos)
8351#define FMC_PATT3_ATTSET3_3 (0x08UL << FMC_PATT3_ATTSET3_Pos)
8352#define FMC_PATT3_ATTSET3_4 (0x10UL << FMC_PATT3_ATTSET3_Pos)
8353#define FMC_PATT3_ATTSET3_5 (0x20UL << FMC_PATT3_ATTSET3_Pos)
8354#define FMC_PATT3_ATTSET3_6 (0x40UL << FMC_PATT3_ATTSET3_Pos)
8355#define FMC_PATT3_ATTSET3_7 (0x80UL << FMC_PATT3_ATTSET3_Pos)
8356
8357#define FMC_PATT3_ATTWAIT3_Pos (8U)
8358#define FMC_PATT3_ATTWAIT3_Msk (0xFFUL << FMC_PATT3_ATTWAIT3_Pos)
8359#define FMC_PATT3_ATTWAIT3 FMC_PATT3_ATTWAIT3_Msk
8360#define FMC_PATT3_ATTWAIT3_0 (0x01UL << FMC_PATT3_ATTWAIT3_Pos)
8361#define FMC_PATT3_ATTWAIT3_1 (0x02UL << FMC_PATT3_ATTWAIT3_Pos)
8362#define FMC_PATT3_ATTWAIT3_2 (0x04UL << FMC_PATT3_ATTWAIT3_Pos)
8363#define FMC_PATT3_ATTWAIT3_3 (0x08UL << FMC_PATT3_ATTWAIT3_Pos)
8364#define FMC_PATT3_ATTWAIT3_4 (0x10UL << FMC_PATT3_ATTWAIT3_Pos)
8365#define FMC_PATT3_ATTWAIT3_5 (0x20UL << FMC_PATT3_ATTWAIT3_Pos)
8366#define FMC_PATT3_ATTWAIT3_6 (0x40UL << FMC_PATT3_ATTWAIT3_Pos)
8367#define FMC_PATT3_ATTWAIT3_7 (0x80UL << FMC_PATT3_ATTWAIT3_Pos)
8368
8369#define FMC_PATT3_ATTHOLD3_Pos (16U)
8370#define FMC_PATT3_ATTHOLD3_Msk (0xFFUL << FMC_PATT3_ATTHOLD3_Pos)
8371#define FMC_PATT3_ATTHOLD3 FMC_PATT3_ATTHOLD3_Msk
8372#define FMC_PATT3_ATTHOLD3_0 (0x01UL << FMC_PATT3_ATTHOLD3_Pos)
8373#define FMC_PATT3_ATTHOLD3_1 (0x02UL << FMC_PATT3_ATTHOLD3_Pos)
8374#define FMC_PATT3_ATTHOLD3_2 (0x04UL << FMC_PATT3_ATTHOLD3_Pos)
8375#define FMC_PATT3_ATTHOLD3_3 (0x08UL << FMC_PATT3_ATTHOLD3_Pos)
8376#define FMC_PATT3_ATTHOLD3_4 (0x10UL << FMC_PATT3_ATTHOLD3_Pos)
8377#define FMC_PATT3_ATTHOLD3_5 (0x20UL << FMC_PATT3_ATTHOLD3_Pos)
8378#define FMC_PATT3_ATTHOLD3_6 (0x40UL << FMC_PATT3_ATTHOLD3_Pos)
8379#define FMC_PATT3_ATTHOLD3_7 (0x80UL << FMC_PATT3_ATTHOLD3_Pos)
8380
8381#define FMC_PATT3_ATTHIZ3_Pos (24U)
8382#define FMC_PATT3_ATTHIZ3_Msk (0xFFUL << FMC_PATT3_ATTHIZ3_Pos)
8383#define FMC_PATT3_ATTHIZ3 FMC_PATT3_ATTHIZ3_Msk
8384#define FMC_PATT3_ATTHIZ3_0 (0x01UL << FMC_PATT3_ATTHIZ3_Pos)
8385#define FMC_PATT3_ATTHIZ3_1 (0x02UL << FMC_PATT3_ATTHIZ3_Pos)
8386#define FMC_PATT3_ATTHIZ3_2 (0x04UL << FMC_PATT3_ATTHIZ3_Pos)
8387#define FMC_PATT3_ATTHIZ3_3 (0x08UL << FMC_PATT3_ATTHIZ3_Pos)
8388#define FMC_PATT3_ATTHIZ3_4 (0x10UL << FMC_PATT3_ATTHIZ3_Pos)
8389#define FMC_PATT3_ATTHIZ3_5 (0x20UL << FMC_PATT3_ATTHIZ3_Pos)
8390#define FMC_PATT3_ATTHIZ3_6 (0x40UL << FMC_PATT3_ATTHIZ3_Pos)
8391#define FMC_PATT3_ATTHIZ3_7 (0x80UL << FMC_PATT3_ATTHIZ3_Pos)
8392
8393/****************** Bit definition for FMC_PATT4 register ******************/
8394#define FMC_PATT4_ATTSET4_Pos (0U)
8395#define FMC_PATT4_ATTSET4_Msk (0xFFUL << FMC_PATT4_ATTSET4_Pos)
8396#define FMC_PATT4_ATTSET4 FMC_PATT4_ATTSET4_Msk
8397#define FMC_PATT4_ATTSET4_0 (0x01UL << FMC_PATT4_ATTSET4_Pos)
8398#define FMC_PATT4_ATTSET4_1 (0x02UL << FMC_PATT4_ATTSET4_Pos)
8399#define FMC_PATT4_ATTSET4_2 (0x04UL << FMC_PATT4_ATTSET4_Pos)
8400#define FMC_PATT4_ATTSET4_3 (0x08UL << FMC_PATT4_ATTSET4_Pos)
8401#define FMC_PATT4_ATTSET4_4 (0x10UL << FMC_PATT4_ATTSET4_Pos)
8402#define FMC_PATT4_ATTSET4_5 (0x20UL << FMC_PATT4_ATTSET4_Pos)
8403#define FMC_PATT4_ATTSET4_6 (0x40UL << FMC_PATT4_ATTSET4_Pos)
8404#define FMC_PATT4_ATTSET4_7 (0x80UL << FMC_PATT4_ATTSET4_Pos)
8405
8406#define FMC_PATT4_ATTWAIT4_Pos (8U)
8407#define FMC_PATT4_ATTWAIT4_Msk (0xFFUL << FMC_PATT4_ATTWAIT4_Pos)
8408#define FMC_PATT4_ATTWAIT4 FMC_PATT4_ATTWAIT4_Msk
8409#define FMC_PATT4_ATTWAIT4_0 (0x01UL << FMC_PATT4_ATTWAIT4_Pos)
8410#define FMC_PATT4_ATTWAIT4_1 (0x02UL << FMC_PATT4_ATTWAIT4_Pos)
8411#define FMC_PATT4_ATTWAIT4_2 (0x04UL << FMC_PATT4_ATTWAIT4_Pos)
8412#define FMC_PATT4_ATTWAIT4_3 (0x08UL << FMC_PATT4_ATTWAIT4_Pos)
8413#define FMC_PATT4_ATTWAIT4_4 (0x10UL << FMC_PATT4_ATTWAIT4_Pos)
8414#define FMC_PATT4_ATTWAIT4_5 (0x20UL << FMC_PATT4_ATTWAIT4_Pos)
8415#define FMC_PATT4_ATTWAIT4_6 (0x40UL << FMC_PATT4_ATTWAIT4_Pos)
8416#define FMC_PATT4_ATTWAIT4_7 (0x80UL << FMC_PATT4_ATTWAIT4_Pos)
8417
8418#define FMC_PATT4_ATTHOLD4_Pos (16U)
8419#define FMC_PATT4_ATTHOLD4_Msk (0xFFUL << FMC_PATT4_ATTHOLD4_Pos)
8420#define FMC_PATT4_ATTHOLD4 FMC_PATT4_ATTHOLD4_Msk
8421#define FMC_PATT4_ATTHOLD4_0 (0x01UL << FMC_PATT4_ATTHOLD4_Pos)
8422#define FMC_PATT4_ATTHOLD4_1 (0x02UL << FMC_PATT4_ATTHOLD4_Pos)
8423#define FMC_PATT4_ATTHOLD4_2 (0x04UL << FMC_PATT4_ATTHOLD4_Pos)
8424#define FMC_PATT4_ATTHOLD4_3 (0x08UL << FMC_PATT4_ATTHOLD4_Pos)
8425#define FMC_PATT4_ATTHOLD4_4 (0x10UL << FMC_PATT4_ATTHOLD4_Pos)
8426#define FMC_PATT4_ATTHOLD4_5 (0x20UL << FMC_PATT4_ATTHOLD4_Pos)
8427#define FMC_PATT4_ATTHOLD4_6 (0x40UL << FMC_PATT4_ATTHOLD4_Pos)
8428#define FMC_PATT4_ATTHOLD4_7 (0x80UL << FMC_PATT4_ATTHOLD4_Pos)
8429
8430#define FMC_PATT4_ATTHIZ4_Pos (24U)
8431#define FMC_PATT4_ATTHIZ4_Msk (0xFFUL << FMC_PATT4_ATTHIZ4_Pos)
8432#define FMC_PATT4_ATTHIZ4 FMC_PATT4_ATTHIZ4_Msk
8433#define FMC_PATT4_ATTHIZ4_0 (0x01UL << FMC_PATT4_ATTHIZ4_Pos)
8434#define FMC_PATT4_ATTHIZ4_1 (0x02UL << FMC_PATT4_ATTHIZ4_Pos)
8435#define FMC_PATT4_ATTHIZ4_2 (0x04UL << FMC_PATT4_ATTHIZ4_Pos)
8436#define FMC_PATT4_ATTHIZ4_3 (0x08UL << FMC_PATT4_ATTHIZ4_Pos)
8437#define FMC_PATT4_ATTHIZ4_4 (0x10UL << FMC_PATT4_ATTHIZ4_Pos)
8438#define FMC_PATT4_ATTHIZ4_5 (0x20UL << FMC_PATT4_ATTHIZ4_Pos)
8439#define FMC_PATT4_ATTHIZ4_6 (0x40UL << FMC_PATT4_ATTHIZ4_Pos)
8440#define FMC_PATT4_ATTHIZ4_7 (0x80UL << FMC_PATT4_ATTHIZ4_Pos)
8441
8442/****************** Bit definition for FMC_PIO4 register *******************/
8443#define FMC_PIO4_IOSET4_Pos (0U)
8444#define FMC_PIO4_IOSET4_Msk (0xFFUL << FMC_PIO4_IOSET4_Pos)
8445#define FMC_PIO4_IOSET4 FMC_PIO4_IOSET4_Msk
8446#define FMC_PIO4_IOSET4_0 (0x01UL << FMC_PIO4_IOSET4_Pos)
8447#define FMC_PIO4_IOSET4_1 (0x02UL << FMC_PIO4_IOSET4_Pos)
8448#define FMC_PIO4_IOSET4_2 (0x04UL << FMC_PIO4_IOSET4_Pos)
8449#define FMC_PIO4_IOSET4_3 (0x08UL << FMC_PIO4_IOSET4_Pos)
8450#define FMC_PIO4_IOSET4_4 (0x10UL << FMC_PIO4_IOSET4_Pos)
8451#define FMC_PIO4_IOSET4_5 (0x20UL << FMC_PIO4_IOSET4_Pos)
8452#define FMC_PIO4_IOSET4_6 (0x40UL << FMC_PIO4_IOSET4_Pos)
8453#define FMC_PIO4_IOSET4_7 (0x80UL << FMC_PIO4_IOSET4_Pos)
8454
8455#define FMC_PIO4_IOWAIT4_Pos (8U)
8456#define FMC_PIO4_IOWAIT4_Msk (0xFFUL << FMC_PIO4_IOWAIT4_Pos)
8457#define FMC_PIO4_IOWAIT4 FMC_PIO4_IOWAIT4_Msk
8458#define FMC_PIO4_IOWAIT4_0 (0x01UL << FMC_PIO4_IOWAIT4_Pos)
8459#define FMC_PIO4_IOWAIT4_1 (0x02UL << FMC_PIO4_IOWAIT4_Pos)
8460#define FMC_PIO4_IOWAIT4_2 (0x04UL << FMC_PIO4_IOWAIT4_Pos)
8461#define FMC_PIO4_IOWAIT4_3 (0x08UL << FMC_PIO4_IOWAIT4_Pos)
8462#define FMC_PIO4_IOWAIT4_4 (0x10UL << FMC_PIO4_IOWAIT4_Pos)
8463#define FMC_PIO4_IOWAIT4_5 (0x20UL << FMC_PIO4_IOWAIT4_Pos)
8464#define FMC_PIO4_IOWAIT4_6 (0x40UL << FMC_PIO4_IOWAIT4_Pos)
8465#define FMC_PIO4_IOWAIT4_7 (0x80UL << FMC_PIO4_IOWAIT4_Pos)
8466
8467#define FMC_PIO4_IOHOLD4_Pos (16U)
8468#define FMC_PIO4_IOHOLD4_Msk (0xFFUL << FMC_PIO4_IOHOLD4_Pos)
8469#define FMC_PIO4_IOHOLD4 FMC_PIO4_IOHOLD4_Msk
8470#define FMC_PIO4_IOHOLD4_0 (0x01UL << FMC_PIO4_IOHOLD4_Pos)
8471#define FMC_PIO4_IOHOLD4_1 (0x02UL << FMC_PIO4_IOHOLD4_Pos)
8472#define FMC_PIO4_IOHOLD4_2 (0x04UL << FMC_PIO4_IOHOLD4_Pos)
8473#define FMC_PIO4_IOHOLD4_3 (0x08UL << FMC_PIO4_IOHOLD4_Pos)
8474#define FMC_PIO4_IOHOLD4_4 (0x10UL << FMC_PIO4_IOHOLD4_Pos)
8475#define FMC_PIO4_IOHOLD4_5 (0x20UL << FMC_PIO4_IOHOLD4_Pos)
8476#define FMC_PIO4_IOHOLD4_6 (0x40UL << FMC_PIO4_IOHOLD4_Pos)
8477#define FMC_PIO4_IOHOLD4_7 (0x80UL << FMC_PIO4_IOHOLD4_Pos)
8478
8479#define FMC_PIO4_IOHIZ4_Pos (24U)
8480#define FMC_PIO4_IOHIZ4_Msk (0xFFUL << FMC_PIO4_IOHIZ4_Pos)
8481#define FMC_PIO4_IOHIZ4 FMC_PIO4_IOHIZ4_Msk
8482#define FMC_PIO4_IOHIZ4_0 (0x01UL << FMC_PIO4_IOHIZ4_Pos)
8483#define FMC_PIO4_IOHIZ4_1 (0x02UL << FMC_PIO4_IOHIZ4_Pos)
8484#define FMC_PIO4_IOHIZ4_2 (0x04UL << FMC_PIO4_IOHIZ4_Pos)
8485#define FMC_PIO4_IOHIZ4_3 (0x08UL << FMC_PIO4_IOHIZ4_Pos)
8486#define FMC_PIO4_IOHIZ4_4 (0x10UL << FMC_PIO4_IOHIZ4_Pos)
8487#define FMC_PIO4_IOHIZ4_5 (0x20UL << FMC_PIO4_IOHIZ4_Pos)
8488#define FMC_PIO4_IOHIZ4_6 (0x40UL << FMC_PIO4_IOHIZ4_Pos)
8489#define FMC_PIO4_IOHIZ4_7 (0x80UL << FMC_PIO4_IOHIZ4_Pos)
8490
8491
8492/****************** Bit definition for FMC_ECCR2 register ******************/
8493#define FMC_ECCR2_ECC2_Pos (0U)
8494#define FMC_ECCR2_ECC2_Msk (0xFFFFFFFFUL << FMC_ECCR2_ECC2_Pos)
8495#define FMC_ECCR2_ECC2 FMC_ECCR2_ECC2_Msk
8496
8497/****************** Bit definition for FMC_ECCR3 register ******************/
8498#define FMC_ECCR3_ECC3_Pos (0U)
8499#define FMC_ECCR3_ECC3_Msk (0xFFFFFFFFUL << FMC_ECCR3_ECC3_Pos)
8500#define FMC_ECCR3_ECC3 FMC_ECCR3_ECC3_Msk
8501
8502/****************** Bit definition for FMC_SDCR1 register ******************/
8503#define FMC_SDCR1_NC_Pos (0U)
8504#define FMC_SDCR1_NC_Msk (0x3UL << FMC_SDCR1_NC_Pos)
8505#define FMC_SDCR1_NC FMC_SDCR1_NC_Msk
8506#define FMC_SDCR1_NC_0 (0x1UL << FMC_SDCR1_NC_Pos)
8507#define FMC_SDCR1_NC_1 (0x2UL << FMC_SDCR1_NC_Pos)
8508
8509#define FMC_SDCR1_NR_Pos (2U)
8510#define FMC_SDCR1_NR_Msk (0x3UL << FMC_SDCR1_NR_Pos)
8511#define FMC_SDCR1_NR FMC_SDCR1_NR_Msk
8512#define FMC_SDCR1_NR_0 (0x1UL << FMC_SDCR1_NR_Pos)
8513#define FMC_SDCR1_NR_1 (0x2UL << FMC_SDCR1_NR_Pos)
8514
8515#define FMC_SDCR1_MWID_Pos (4U)
8516#define FMC_SDCR1_MWID_Msk (0x3UL << FMC_SDCR1_MWID_Pos)
8517#define FMC_SDCR1_MWID FMC_SDCR1_MWID_Msk
8518#define FMC_SDCR1_MWID_0 (0x1UL << FMC_SDCR1_MWID_Pos)
8519#define FMC_SDCR1_MWID_1 (0x2UL << FMC_SDCR1_MWID_Pos)
8520
8521#define FMC_SDCR1_NB_Pos (6U)
8522#define FMC_SDCR1_NB_Msk (0x1UL << FMC_SDCR1_NB_Pos)
8523#define FMC_SDCR1_NB FMC_SDCR1_NB_Msk
8524
8525#define FMC_SDCR1_CAS_Pos (7U)
8526#define FMC_SDCR1_CAS_Msk (0x3UL << FMC_SDCR1_CAS_Pos)
8527#define FMC_SDCR1_CAS FMC_SDCR1_CAS_Msk
8528#define FMC_SDCR1_CAS_0 (0x1UL << FMC_SDCR1_CAS_Pos)
8529#define FMC_SDCR1_CAS_1 (0x2UL << FMC_SDCR1_CAS_Pos)
8530
8531#define FMC_SDCR1_WP_Pos (9U)
8532#define FMC_SDCR1_WP_Msk (0x1UL << FMC_SDCR1_WP_Pos)
8533#define FMC_SDCR1_WP FMC_SDCR1_WP_Msk
8534
8535#define FMC_SDCR1_SDCLK_Pos (10U)
8536#define FMC_SDCR1_SDCLK_Msk (0x3UL << FMC_SDCR1_SDCLK_Pos)
8537#define FMC_SDCR1_SDCLK FMC_SDCR1_SDCLK_Msk
8538#define FMC_SDCR1_SDCLK_0 (0x1UL << FMC_SDCR1_SDCLK_Pos)
8539#define FMC_SDCR1_SDCLK_1 (0x2UL << FMC_SDCR1_SDCLK_Pos)
8540
8541#define FMC_SDCR1_RBURST_Pos (12U)
8542#define FMC_SDCR1_RBURST_Msk (0x1UL << FMC_SDCR1_RBURST_Pos)
8543#define FMC_SDCR1_RBURST FMC_SDCR1_RBURST_Msk
8544
8545#define FMC_SDCR1_RPIPE_Pos (13U)
8546#define FMC_SDCR1_RPIPE_Msk (0x3UL << FMC_SDCR1_RPIPE_Pos)
8547#define FMC_SDCR1_RPIPE FMC_SDCR1_RPIPE_Msk
8548#define FMC_SDCR1_RPIPE_0 (0x1UL << FMC_SDCR1_RPIPE_Pos)
8549#define FMC_SDCR1_RPIPE_1 (0x2UL << FMC_SDCR1_RPIPE_Pos)
8550
8551/****************** Bit definition for FMC_SDCR2 register ******************/
8552#define FMC_SDCR2_NC_Pos (0U)
8553#define FMC_SDCR2_NC_Msk (0x3UL << FMC_SDCR2_NC_Pos)
8554#define FMC_SDCR2_NC FMC_SDCR2_NC_Msk
8555#define FMC_SDCR2_NC_0 (0x1UL << FMC_SDCR2_NC_Pos)
8556#define FMC_SDCR2_NC_1 (0x2UL << FMC_SDCR2_NC_Pos)
8557
8558#define FMC_SDCR2_NR_Pos (2U)
8559#define FMC_SDCR2_NR_Msk (0x3UL << FMC_SDCR2_NR_Pos)
8560#define FMC_SDCR2_NR FMC_SDCR2_NR_Msk
8561#define FMC_SDCR2_NR_0 (0x1UL << FMC_SDCR2_NR_Pos)
8562#define FMC_SDCR2_NR_1 (0x2UL << FMC_SDCR2_NR_Pos)
8563
8564#define FMC_SDCR2_MWID_Pos (4U)
8565#define FMC_SDCR2_MWID_Msk (0x3UL << FMC_SDCR2_MWID_Pos)
8566#define FMC_SDCR2_MWID FMC_SDCR2_MWID_Msk
8567#define FMC_SDCR2_MWID_0 (0x1UL << FMC_SDCR2_MWID_Pos)
8568#define FMC_SDCR2_MWID_1 (0x2UL << FMC_SDCR2_MWID_Pos)
8569
8570#define FMC_SDCR2_NB_Pos (6U)
8571#define FMC_SDCR2_NB_Msk (0x1UL << FMC_SDCR2_NB_Pos)
8572#define FMC_SDCR2_NB FMC_SDCR2_NB_Msk
8573
8574#define FMC_SDCR2_CAS_Pos (7U)
8575#define FMC_SDCR2_CAS_Msk (0x3UL << FMC_SDCR2_CAS_Pos)
8576#define FMC_SDCR2_CAS FMC_SDCR2_CAS_Msk
8577#define FMC_SDCR2_CAS_0 (0x1UL << FMC_SDCR2_CAS_Pos)
8578#define FMC_SDCR2_CAS_1 (0x2UL << FMC_SDCR2_CAS_Pos)
8579
8580#define FMC_SDCR2_WP_Pos (9U)
8581#define FMC_SDCR2_WP_Msk (0x1UL << FMC_SDCR2_WP_Pos)
8582#define FMC_SDCR2_WP FMC_SDCR2_WP_Msk
8583
8584#define FMC_SDCR2_SDCLK_Pos (10U)
8585#define FMC_SDCR2_SDCLK_Msk (0x3UL << FMC_SDCR2_SDCLK_Pos)
8586#define FMC_SDCR2_SDCLK FMC_SDCR2_SDCLK_Msk
8587#define FMC_SDCR2_SDCLK_0 (0x1UL << FMC_SDCR2_SDCLK_Pos)
8588#define FMC_SDCR2_SDCLK_1 (0x2UL << FMC_SDCR2_SDCLK_Pos)
8589
8590#define FMC_SDCR2_RBURST_Pos (12U)
8591#define FMC_SDCR2_RBURST_Msk (0x1UL << FMC_SDCR2_RBURST_Pos)
8592#define FMC_SDCR2_RBURST FMC_SDCR2_RBURST_Msk
8593
8594#define FMC_SDCR2_RPIPE_Pos (13U)
8595#define FMC_SDCR2_RPIPE_Msk (0x3UL << FMC_SDCR2_RPIPE_Pos)
8596#define FMC_SDCR2_RPIPE FMC_SDCR2_RPIPE_Msk
8597#define FMC_SDCR2_RPIPE_0 (0x1UL << FMC_SDCR2_RPIPE_Pos)
8598#define FMC_SDCR2_RPIPE_1 (0x2UL << FMC_SDCR2_RPIPE_Pos)
8599
8600/****************** Bit definition for FMC_SDTR1 register ******************/
8601#define FMC_SDTR1_TMRD_Pos (0U)
8602#define FMC_SDTR1_TMRD_Msk (0xFUL << FMC_SDTR1_TMRD_Pos)
8603#define FMC_SDTR1_TMRD FMC_SDTR1_TMRD_Msk
8604#define FMC_SDTR1_TMRD_0 (0x1UL << FMC_SDTR1_TMRD_Pos)
8605#define FMC_SDTR1_TMRD_1 (0x2UL << FMC_SDTR1_TMRD_Pos)
8606#define FMC_SDTR1_TMRD_2 (0x4UL << FMC_SDTR1_TMRD_Pos)
8607#define FMC_SDTR1_TMRD_3 (0x8UL << FMC_SDTR1_TMRD_Pos)
8608
8609#define FMC_SDTR1_TXSR_Pos (4U)
8610#define FMC_SDTR1_TXSR_Msk (0xFUL << FMC_SDTR1_TXSR_Pos)
8611#define FMC_SDTR1_TXSR FMC_SDTR1_TXSR_Msk
8612#define FMC_SDTR1_TXSR_0 (0x1UL << FMC_SDTR1_TXSR_Pos)
8613#define FMC_SDTR1_TXSR_1 (0x2UL << FMC_SDTR1_TXSR_Pos)
8614#define FMC_SDTR1_TXSR_2 (0x4UL << FMC_SDTR1_TXSR_Pos)
8615#define FMC_SDTR1_TXSR_3 (0x8UL << FMC_SDTR1_TXSR_Pos)
8616
8617#define FMC_SDTR1_TRAS_Pos (8U)
8618#define FMC_SDTR1_TRAS_Msk (0xFUL << FMC_SDTR1_TRAS_Pos)
8619#define FMC_SDTR1_TRAS FMC_SDTR1_TRAS_Msk
8620#define FMC_SDTR1_TRAS_0 (0x1UL << FMC_SDTR1_TRAS_Pos)
8621#define FMC_SDTR1_TRAS_1 (0x2UL << FMC_SDTR1_TRAS_Pos)
8622#define FMC_SDTR1_TRAS_2 (0x4UL << FMC_SDTR1_TRAS_Pos)
8623#define FMC_SDTR1_TRAS_3 (0x8UL << FMC_SDTR1_TRAS_Pos)
8624
8625#define FMC_SDTR1_TRC_Pos (12U)
8626#define FMC_SDTR1_TRC_Msk (0xFUL << FMC_SDTR1_TRC_Pos)
8627#define FMC_SDTR1_TRC FMC_SDTR1_TRC_Msk
8628#define FMC_SDTR1_TRC_0 (0x1UL << FMC_SDTR1_TRC_Pos)
8629#define FMC_SDTR1_TRC_1 (0x2UL << FMC_SDTR1_TRC_Pos)
8630#define FMC_SDTR1_TRC_2 (0x4UL << FMC_SDTR1_TRC_Pos)
8631
8632#define FMC_SDTR1_TWR_Pos (16U)
8633#define FMC_SDTR1_TWR_Msk (0xFUL << FMC_SDTR1_TWR_Pos)
8634#define FMC_SDTR1_TWR FMC_SDTR1_TWR_Msk
8635#define FMC_SDTR1_TWR_0 (0x1UL << FMC_SDTR1_TWR_Pos)
8636#define FMC_SDTR1_TWR_1 (0x2UL << FMC_SDTR1_TWR_Pos)
8637#define FMC_SDTR1_TWR_2 (0x4UL << FMC_SDTR1_TWR_Pos)
8638
8639#define FMC_SDTR1_TRP_Pos (20U)
8640#define FMC_SDTR1_TRP_Msk (0xFUL << FMC_SDTR1_TRP_Pos)
8641#define FMC_SDTR1_TRP FMC_SDTR1_TRP_Msk
8642#define FMC_SDTR1_TRP_0 (0x1UL << FMC_SDTR1_TRP_Pos)
8643#define FMC_SDTR1_TRP_1 (0x2UL << FMC_SDTR1_TRP_Pos)
8644#define FMC_SDTR1_TRP_2 (0x4UL << FMC_SDTR1_TRP_Pos)
8645
8646#define FMC_SDTR1_TRCD_Pos (24U)
8647#define FMC_SDTR1_TRCD_Msk (0xFUL << FMC_SDTR1_TRCD_Pos)
8648#define FMC_SDTR1_TRCD FMC_SDTR1_TRCD_Msk
8649#define FMC_SDTR1_TRCD_0 (0x1UL << FMC_SDTR1_TRCD_Pos)
8650#define FMC_SDTR1_TRCD_1 (0x2UL << FMC_SDTR1_TRCD_Pos)
8651#define FMC_SDTR1_TRCD_2 (0x4UL << FMC_SDTR1_TRCD_Pos)
8652
8653/****************** Bit definition for FMC_SDTR2 register ******************/
8654#define FMC_SDTR2_TMRD_Pos (0U)
8655#define FMC_SDTR2_TMRD_Msk (0xFUL << FMC_SDTR2_TMRD_Pos)
8656#define FMC_SDTR2_TMRD FMC_SDTR2_TMRD_Msk
8657#define FMC_SDTR2_TMRD_0 (0x1UL << FMC_SDTR2_TMRD_Pos)
8658#define FMC_SDTR2_TMRD_1 (0x2UL << FMC_SDTR2_TMRD_Pos)
8659#define FMC_SDTR2_TMRD_2 (0x4UL << FMC_SDTR2_TMRD_Pos)
8660#define FMC_SDTR2_TMRD_3 (0x8UL << FMC_SDTR2_TMRD_Pos)
8661
8662#define FMC_SDTR2_TXSR_Pos (4U)
8663#define FMC_SDTR2_TXSR_Msk (0xFUL << FMC_SDTR2_TXSR_Pos)
8664#define FMC_SDTR2_TXSR FMC_SDTR2_TXSR_Msk
8665#define FMC_SDTR2_TXSR_0 (0x1UL << FMC_SDTR2_TXSR_Pos)
8666#define FMC_SDTR2_TXSR_1 (0x2UL << FMC_SDTR2_TXSR_Pos)
8667#define FMC_SDTR2_TXSR_2 (0x4UL << FMC_SDTR2_TXSR_Pos)
8668#define FMC_SDTR2_TXSR_3 (0x8UL << FMC_SDTR2_TXSR_Pos)
8669
8670#define FMC_SDTR2_TRAS_Pos (8U)
8671#define FMC_SDTR2_TRAS_Msk (0xFUL << FMC_SDTR2_TRAS_Pos)
8672#define FMC_SDTR2_TRAS FMC_SDTR2_TRAS_Msk
8673#define FMC_SDTR2_TRAS_0 (0x1UL << FMC_SDTR2_TRAS_Pos)
8674#define FMC_SDTR2_TRAS_1 (0x2UL << FMC_SDTR2_TRAS_Pos)
8675#define FMC_SDTR2_TRAS_2 (0x4UL << FMC_SDTR2_TRAS_Pos)
8676#define FMC_SDTR2_TRAS_3 (0x8UL << FMC_SDTR2_TRAS_Pos)
8677
8678#define FMC_SDTR2_TRC_Pos (12U)
8679#define FMC_SDTR2_TRC_Msk (0xFUL << FMC_SDTR2_TRC_Pos)
8680#define FMC_SDTR2_TRC FMC_SDTR2_TRC_Msk
8681#define FMC_SDTR2_TRC_0 (0x1UL << FMC_SDTR2_TRC_Pos)
8682#define FMC_SDTR2_TRC_1 (0x2UL << FMC_SDTR2_TRC_Pos)
8683#define FMC_SDTR2_TRC_2 (0x4UL << FMC_SDTR2_TRC_Pos)
8684
8685#define FMC_SDTR2_TWR_Pos (16U)
8686#define FMC_SDTR2_TWR_Msk (0xFUL << FMC_SDTR2_TWR_Pos)
8687#define FMC_SDTR2_TWR FMC_SDTR2_TWR_Msk
8688#define FMC_SDTR2_TWR_0 (0x1UL << FMC_SDTR2_TWR_Pos)
8689#define FMC_SDTR2_TWR_1 (0x2UL << FMC_SDTR2_TWR_Pos)
8690#define FMC_SDTR2_TWR_2 (0x4UL << FMC_SDTR2_TWR_Pos)
8691
8692#define FMC_SDTR2_TRP_Pos (20U)
8693#define FMC_SDTR2_TRP_Msk (0xFUL << FMC_SDTR2_TRP_Pos)
8694#define FMC_SDTR2_TRP FMC_SDTR2_TRP_Msk
8695#define FMC_SDTR2_TRP_0 (0x1UL << FMC_SDTR2_TRP_Pos)
8696#define FMC_SDTR2_TRP_1 (0x2UL << FMC_SDTR2_TRP_Pos)
8697#define FMC_SDTR2_TRP_2 (0x4UL << FMC_SDTR2_TRP_Pos)
8698
8699#define FMC_SDTR2_TRCD_Pos (24U)
8700#define FMC_SDTR2_TRCD_Msk (0xFUL << FMC_SDTR2_TRCD_Pos)
8701#define FMC_SDTR2_TRCD FMC_SDTR2_TRCD_Msk
8702#define FMC_SDTR2_TRCD_0 (0x1UL << FMC_SDTR2_TRCD_Pos)
8703#define FMC_SDTR2_TRCD_1 (0x2UL << FMC_SDTR2_TRCD_Pos)
8704#define FMC_SDTR2_TRCD_2 (0x4UL << FMC_SDTR2_TRCD_Pos)
8705
8706/****************** Bit definition for FMC_SDCMR register ******************/
8707#define FMC_SDCMR_MODE_Pos (0U)
8708#define FMC_SDCMR_MODE_Msk (0x7UL << FMC_SDCMR_MODE_Pos)
8709#define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk
8710#define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos)
8711#define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos)
8712#define FMC_SDCMR_MODE_2 (0x4UL << FMC_SDCMR_MODE_Pos)
8713
8714#define FMC_SDCMR_CTB2_Pos (3U)
8715#define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos)
8716#define FMC_SDCMR_CTB2 FMC_SDCMR_CTB2_Msk
8717
8718#define FMC_SDCMR_CTB1_Pos (4U)
8719#define FMC_SDCMR_CTB1_Msk (0x1UL << FMC_SDCMR_CTB1_Pos)
8720#define FMC_SDCMR_CTB1 FMC_SDCMR_CTB1_Msk
8721
8722#define FMC_SDCMR_NRFS_Pos (5U)
8723#define FMC_SDCMR_NRFS_Msk (0xFUL << FMC_SDCMR_NRFS_Pos)
8724#define FMC_SDCMR_NRFS FMC_SDCMR_NRFS_Msk
8725#define FMC_SDCMR_NRFS_0 (0x1UL << FMC_SDCMR_NRFS_Pos)
8726#define FMC_SDCMR_NRFS_1 (0x2UL << FMC_SDCMR_NRFS_Pos)
8727#define FMC_SDCMR_NRFS_2 (0x4UL << FMC_SDCMR_NRFS_Pos)
8728#define FMC_SDCMR_NRFS_3 (0x8UL << FMC_SDCMR_NRFS_Pos)
8729
8730#define FMC_SDCMR_MRD_Pos (9U)
8731#define FMC_SDCMR_MRD_Msk (0x1FFFUL << FMC_SDCMR_MRD_Pos)
8732#define FMC_SDCMR_MRD FMC_SDCMR_MRD_Msk
8733
8734/****************** Bit definition for FMC_SDRTR register ******************/
8735#define FMC_SDRTR_CRE_Pos (0U)
8736#define FMC_SDRTR_CRE_Msk (0x1UL << FMC_SDRTR_CRE_Pos)
8737#define FMC_SDRTR_CRE FMC_SDRTR_CRE_Msk
8738
8739#define FMC_SDRTR_COUNT_Pos (1U)
8740#define FMC_SDRTR_COUNT_Msk (0x1FFFUL << FMC_SDRTR_COUNT_Pos)
8741#define FMC_SDRTR_COUNT FMC_SDRTR_COUNT_Msk
8742
8743#define FMC_SDRTR_REIE_Pos (14U)
8744#define FMC_SDRTR_REIE_Msk (0x1UL << FMC_SDRTR_REIE_Pos)
8745#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk
8746
8747/****************** Bit definition for FMC_SDSR register ******************/
8748#define FMC_SDSR_RE_Pos (0U)
8749#define FMC_SDSR_RE_Msk (0x1UL << FMC_SDSR_RE_Pos)
8750#define FMC_SDSR_RE FMC_SDSR_RE_Msk
8751
8752#define FMC_SDSR_MODES1_Pos (1U)
8753#define FMC_SDSR_MODES1_Msk (0x3UL << FMC_SDSR_MODES1_Pos)
8754#define FMC_SDSR_MODES1 FMC_SDSR_MODES1_Msk
8755#define FMC_SDSR_MODES1_0 (0x1UL << FMC_SDSR_MODES1_Pos)
8756#define FMC_SDSR_MODES1_1 (0x2UL << FMC_SDSR_MODES1_Pos)
8757
8758#define FMC_SDSR_MODES2_Pos (3U)
8759#define FMC_SDSR_MODES2_Msk (0x3UL << FMC_SDSR_MODES2_Pos)
8760#define FMC_SDSR_MODES2 FMC_SDSR_MODES2_Msk
8761#define FMC_SDSR_MODES2_0 (0x1UL << FMC_SDSR_MODES2_Pos)
8762#define FMC_SDSR_MODES2_1 (0x2UL << FMC_SDSR_MODES2_Pos)
8763#define FMC_SDSR_BUSY_Pos (5U)
8764#define FMC_SDSR_BUSY_Msk (0x1UL << FMC_SDSR_BUSY_Pos)
8765#define FMC_SDSR_BUSY FMC_SDSR_BUSY_Msk
8766
8767/******************************************************************************/
8768/* */
8769/* General Purpose I/O */
8770/* */
8771/******************************************************************************/
8772/****************** Bits definition for GPIO_MODER register *****************/
8773#define GPIO_MODER_MODER0_Pos (0U)
8774#define GPIO_MODER_MODER0_Msk (0x3UL << GPIO_MODER_MODER0_Pos)
8775#define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
8776#define GPIO_MODER_MODER0_0 (0x1UL << GPIO_MODER_MODER0_Pos)
8777#define GPIO_MODER_MODER0_1 (0x2UL << GPIO_MODER_MODER0_Pos)
8778#define GPIO_MODER_MODER1_Pos (2U)
8779#define GPIO_MODER_MODER1_Msk (0x3UL << GPIO_MODER_MODER1_Pos)
8780#define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
8781#define GPIO_MODER_MODER1_0 (0x1UL << GPIO_MODER_MODER1_Pos)
8782#define GPIO_MODER_MODER1_1 (0x2UL << GPIO_MODER_MODER1_Pos)
8783#define GPIO_MODER_MODER2_Pos (4U)
8784#define GPIO_MODER_MODER2_Msk (0x3UL << GPIO_MODER_MODER2_Pos)
8785#define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
8786#define GPIO_MODER_MODER2_0 (0x1UL << GPIO_MODER_MODER2_Pos)
8787#define GPIO_MODER_MODER2_1 (0x2UL << GPIO_MODER_MODER2_Pos)
8788#define GPIO_MODER_MODER3_Pos (6U)
8789#define GPIO_MODER_MODER3_Msk (0x3UL << GPIO_MODER_MODER3_Pos)
8790#define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
8791#define GPIO_MODER_MODER3_0 (0x1UL << GPIO_MODER_MODER3_Pos)
8792#define GPIO_MODER_MODER3_1 (0x2UL << GPIO_MODER_MODER3_Pos)
8793#define GPIO_MODER_MODER4_Pos (8U)
8794#define GPIO_MODER_MODER4_Msk (0x3UL << GPIO_MODER_MODER4_Pos)
8795#define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
8796#define GPIO_MODER_MODER4_0 (0x1UL << GPIO_MODER_MODER4_Pos)
8797#define GPIO_MODER_MODER4_1 (0x2UL << GPIO_MODER_MODER4_Pos)
8798#define GPIO_MODER_MODER5_Pos (10U)
8799#define GPIO_MODER_MODER5_Msk (0x3UL << GPIO_MODER_MODER5_Pos)
8800#define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
8801#define GPIO_MODER_MODER5_0 (0x1UL << GPIO_MODER_MODER5_Pos)
8802#define GPIO_MODER_MODER5_1 (0x2UL << GPIO_MODER_MODER5_Pos)
8803#define GPIO_MODER_MODER6_Pos (12U)
8804#define GPIO_MODER_MODER6_Msk (0x3UL << GPIO_MODER_MODER6_Pos)
8805#define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
8806#define GPIO_MODER_MODER6_0 (0x1UL << GPIO_MODER_MODER6_Pos)
8807#define GPIO_MODER_MODER6_1 (0x2UL << GPIO_MODER_MODER6_Pos)
8808#define GPIO_MODER_MODER7_Pos (14U)
8809#define GPIO_MODER_MODER7_Msk (0x3UL << GPIO_MODER_MODER7_Pos)
8810#define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
8811#define GPIO_MODER_MODER7_0 (0x1UL << GPIO_MODER_MODER7_Pos)
8812#define GPIO_MODER_MODER7_1 (0x2UL << GPIO_MODER_MODER7_Pos)
8813#define GPIO_MODER_MODER8_Pos (16U)
8814#define GPIO_MODER_MODER8_Msk (0x3UL << GPIO_MODER_MODER8_Pos)
8815#define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
8816#define GPIO_MODER_MODER8_0 (0x1UL << GPIO_MODER_MODER8_Pos)
8817#define GPIO_MODER_MODER8_1 (0x2UL << GPIO_MODER_MODER8_Pos)
8818#define GPIO_MODER_MODER9_Pos (18U)
8819#define GPIO_MODER_MODER9_Msk (0x3UL << GPIO_MODER_MODER9_Pos)
8820#define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
8821#define GPIO_MODER_MODER9_0 (0x1UL << GPIO_MODER_MODER9_Pos)
8822#define GPIO_MODER_MODER9_1 (0x2UL << GPIO_MODER_MODER9_Pos)
8823#define GPIO_MODER_MODER10_Pos (20U)
8824#define GPIO_MODER_MODER10_Msk (0x3UL << GPIO_MODER_MODER10_Pos)
8825#define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
8826#define GPIO_MODER_MODER10_0 (0x1UL << GPIO_MODER_MODER10_Pos)
8827#define GPIO_MODER_MODER10_1 (0x2UL << GPIO_MODER_MODER10_Pos)
8828#define GPIO_MODER_MODER11_Pos (22U)
8829#define GPIO_MODER_MODER11_Msk (0x3UL << GPIO_MODER_MODER11_Pos)
8830#define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
8831#define GPIO_MODER_MODER11_0 (0x1UL << GPIO_MODER_MODER11_Pos)
8832#define GPIO_MODER_MODER11_1 (0x2UL << GPIO_MODER_MODER11_Pos)
8833#define GPIO_MODER_MODER12_Pos (24U)
8834#define GPIO_MODER_MODER12_Msk (0x3UL << GPIO_MODER_MODER12_Pos)
8835#define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
8836#define GPIO_MODER_MODER12_0 (0x1UL << GPIO_MODER_MODER12_Pos)
8837#define GPIO_MODER_MODER12_1 (0x2UL << GPIO_MODER_MODER12_Pos)
8838#define GPIO_MODER_MODER13_Pos (26U)
8839#define GPIO_MODER_MODER13_Msk (0x3UL << GPIO_MODER_MODER13_Pos)
8840#define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
8841#define GPIO_MODER_MODER13_0 (0x1UL << GPIO_MODER_MODER13_Pos)
8842#define GPIO_MODER_MODER13_1 (0x2UL << GPIO_MODER_MODER13_Pos)
8843#define GPIO_MODER_MODER14_Pos (28U)
8844#define GPIO_MODER_MODER14_Msk (0x3UL << GPIO_MODER_MODER14_Pos)
8845#define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
8846#define GPIO_MODER_MODER14_0 (0x1UL << GPIO_MODER_MODER14_Pos)
8847#define GPIO_MODER_MODER14_1 (0x2UL << GPIO_MODER_MODER14_Pos)
8848#define GPIO_MODER_MODER15_Pos (30U)
8849#define GPIO_MODER_MODER15_Msk (0x3UL << GPIO_MODER_MODER15_Pos)
8850#define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
8851#define GPIO_MODER_MODER15_0 (0x1UL << GPIO_MODER_MODER15_Pos)
8852#define GPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos)
8853
8854/* Legacy defines */
8855#define GPIO_MODER_MODE0_Pos GPIO_MODER_MODER0_Pos
8856#define GPIO_MODER_MODE0_Msk GPIO_MODER_MODER0_Msk
8857#define GPIO_MODER_MODE0 GPIO_MODER_MODER0
8858#define GPIO_MODER_MODE0_0 GPIO_MODER_MODER0_0
8859#define GPIO_MODER_MODE0_1 GPIO_MODER_MODER0_1
8860#define GPIO_MODER_MODE1_Pos GPIO_MODER_MODER1_Pos
8861#define GPIO_MODER_MODE1_Msk GPIO_MODER_MODER1_Msk
8862#define GPIO_MODER_MODE1 GPIO_MODER_MODER1
8863#define GPIO_MODER_MODE1_0 GPIO_MODER_MODER1_0
8864#define GPIO_MODER_MODE1_1 GPIO_MODER_MODER1_1
8865#define GPIO_MODER_MODE2_Pos GPIO_MODER_MODER2_Pos
8866#define GPIO_MODER_MODE2_Msk GPIO_MODER_MODER2_Msk
8867#define GPIO_MODER_MODE2 GPIO_MODER_MODER2
8868#define GPIO_MODER_MODE2_0 GPIO_MODER_MODER2_0
8869#define GPIO_MODER_MODE2_1 GPIO_MODER_MODER2_1
8870#define GPIO_MODER_MODE3_Pos GPIO_MODER_MODER3_Pos
8871#define GPIO_MODER_MODE3_Msk GPIO_MODER_MODER3_Msk
8872#define GPIO_MODER_MODE3 GPIO_MODER_MODER3
8873#define GPIO_MODER_MODE3_0 GPIO_MODER_MODER3_0
8874#define GPIO_MODER_MODE3_1 GPIO_MODER_MODER3_1
8875#define GPIO_MODER_MODE4_Pos GPIO_MODER_MODER4_Pos
8876#define GPIO_MODER_MODE4_Msk GPIO_MODER_MODER4_Msk
8877#define GPIO_MODER_MODE4 GPIO_MODER_MODER4
8878#define GPIO_MODER_MODE4_0 GPIO_MODER_MODER4_0
8879#define GPIO_MODER_MODE4_1 GPIO_MODER_MODER4_1
8880#define GPIO_MODER_MODE5_Pos GPIO_MODER_MODER5_Pos
8881#define GPIO_MODER_MODE5_Msk GPIO_MODER_MODER5_Msk
8882#define GPIO_MODER_MODE5 GPIO_MODER_MODER5
8883#define GPIO_MODER_MODE5_0 GPIO_MODER_MODER5_0
8884#define GPIO_MODER_MODE5_1 GPIO_MODER_MODER5_1
8885#define GPIO_MODER_MODE6_Pos GPIO_MODER_MODER6_Pos
8886#define GPIO_MODER_MODE6_Msk GPIO_MODER_MODER6_Msk
8887#define GPIO_MODER_MODE6 GPIO_MODER_MODER6
8888#define GPIO_MODER_MODE6_0 GPIO_MODER_MODER6_0
8889#define GPIO_MODER_MODE6_1 GPIO_MODER_MODER6_1
8890#define GPIO_MODER_MODE7_Pos GPIO_MODER_MODER7_Pos
8891#define GPIO_MODER_MODE7_Msk GPIO_MODER_MODER7_Msk
8892#define GPIO_MODER_MODE7 GPIO_MODER_MODER7
8893#define GPIO_MODER_MODE7_0 GPIO_MODER_MODER7_0
8894#define GPIO_MODER_MODE7_1 GPIO_MODER_MODER7_1
8895#define GPIO_MODER_MODE8_Pos GPIO_MODER_MODER8_Pos
8896#define GPIO_MODER_MODE8_Msk GPIO_MODER_MODER8_Msk
8897#define GPIO_MODER_MODE8 GPIO_MODER_MODER8
8898#define GPIO_MODER_MODE8_0 GPIO_MODER_MODER8_0
8899#define GPIO_MODER_MODE8_1 GPIO_MODER_MODER8_1
8900#define GPIO_MODER_MODE9_Pos GPIO_MODER_MODER9_Pos
8901#define GPIO_MODER_MODE9_Msk GPIO_MODER_MODER9_Msk
8902#define GPIO_MODER_MODE9 GPIO_MODER_MODER9
8903#define GPIO_MODER_MODE9_0 GPIO_MODER_MODER9_0
8904#define GPIO_MODER_MODE9_1 GPIO_MODER_MODER9_1
8905#define GPIO_MODER_MODE10_Pos GPIO_MODER_MODER10_Pos
8906#define GPIO_MODER_MODE10_Msk GPIO_MODER_MODER10_Msk
8907#define GPIO_MODER_MODE10 GPIO_MODER_MODER10
8908#define GPIO_MODER_MODE10_0 GPIO_MODER_MODER10_0
8909#define GPIO_MODER_MODE10_1 GPIO_MODER_MODER10_1
8910#define GPIO_MODER_MODE11_Pos GPIO_MODER_MODER11_Pos
8911#define GPIO_MODER_MODE11_Msk GPIO_MODER_MODER11_Msk
8912#define GPIO_MODER_MODE11 GPIO_MODER_MODER11
8913#define GPIO_MODER_MODE11_0 GPIO_MODER_MODER11_0
8914#define GPIO_MODER_MODE11_1 GPIO_MODER_MODER11_1
8915#define GPIO_MODER_MODE12_Pos GPIO_MODER_MODER12_Pos
8916#define GPIO_MODER_MODE12_Msk GPIO_MODER_MODER12_Msk
8917#define GPIO_MODER_MODE12 GPIO_MODER_MODER12
8918#define GPIO_MODER_MODE12_0 GPIO_MODER_MODER12_0
8919#define GPIO_MODER_MODE12_1 GPIO_MODER_MODER12_1
8920#define GPIO_MODER_MODE13_Pos GPIO_MODER_MODER13_Pos
8921#define GPIO_MODER_MODE13_Msk GPIO_MODER_MODER13_Msk
8922#define GPIO_MODER_MODE13 GPIO_MODER_MODER13
8923#define GPIO_MODER_MODE13_0 GPIO_MODER_MODER13_0
8924#define GPIO_MODER_MODE13_1 GPIO_MODER_MODER13_1
8925#define GPIO_MODER_MODE14_Pos GPIO_MODER_MODER14_Pos
8926#define GPIO_MODER_MODE14_Msk GPIO_MODER_MODER14_Msk
8927#define GPIO_MODER_MODE14 GPIO_MODER_MODER14
8928#define GPIO_MODER_MODE14_0 GPIO_MODER_MODER14_0
8929#define GPIO_MODER_MODE14_1 GPIO_MODER_MODER14_1
8930#define GPIO_MODER_MODE15_Pos GPIO_MODER_MODER15_Pos
8931#define GPIO_MODER_MODE15_Msk GPIO_MODER_MODER15_Msk
8932#define GPIO_MODER_MODE15 GPIO_MODER_MODER15
8933#define GPIO_MODER_MODE15_0 GPIO_MODER_MODER15_0
8934#define GPIO_MODER_MODE15_1 GPIO_MODER_MODER15_1
8935
8936/****************** Bits definition for GPIO_OTYPER register ****************/
8937#define GPIO_OTYPER_OT0_Pos (0U)
8938#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos)
8939#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
8940#define GPIO_OTYPER_OT1_Pos (1U)
8941#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos)
8942#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
8943#define GPIO_OTYPER_OT2_Pos (2U)
8944#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos)
8945#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
8946#define GPIO_OTYPER_OT3_Pos (3U)
8947#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos)
8948#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
8949#define GPIO_OTYPER_OT4_Pos (4U)
8950#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos)
8951#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
8952#define GPIO_OTYPER_OT5_Pos (5U)
8953#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos)
8954#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
8955#define GPIO_OTYPER_OT6_Pos (6U)
8956#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos)
8957#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
8958#define GPIO_OTYPER_OT7_Pos (7U)
8959#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos)
8960#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
8961#define GPIO_OTYPER_OT8_Pos (8U)
8962#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos)
8963#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
8964#define GPIO_OTYPER_OT9_Pos (9U)
8965#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos)
8966#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
8967#define GPIO_OTYPER_OT10_Pos (10U)
8968#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos)
8969#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
8970#define GPIO_OTYPER_OT11_Pos (11U)
8971#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos)
8972#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
8973#define GPIO_OTYPER_OT12_Pos (12U)
8974#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos)
8975#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
8976#define GPIO_OTYPER_OT13_Pos (13U)
8977#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos)
8978#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
8979#define GPIO_OTYPER_OT14_Pos (14U)
8980#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos)
8981#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
8982#define GPIO_OTYPER_OT15_Pos (15U)
8983#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos)
8984#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
8985
8986/* Legacy defines */
8987#define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
8988#define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
8989#define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
8990#define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
8991#define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
8992#define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
8993#define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
8994#define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
8995#define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
8996#define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
8997#define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
8998#define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
8999#define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
9000#define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
9001#define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
9002#define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
9003
9004/****************** Bits definition for GPIO_OSPEEDR register ***************/
9005#define GPIO_OSPEEDR_OSPEED0_Pos (0U)
9006#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)
9007#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
9008#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)
9009#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)
9010#define GPIO_OSPEEDR_OSPEED1_Pos (2U)
9011#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)
9012#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
9013#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)
9014#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)
9015#define GPIO_OSPEEDR_OSPEED2_Pos (4U)
9016#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)
9017#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
9018#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)
9019#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)
9020#define GPIO_OSPEEDR_OSPEED3_Pos (6U)
9021#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)
9022#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
9023#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)
9024#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)
9025#define GPIO_OSPEEDR_OSPEED4_Pos (8U)
9026#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)
9027#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
9028#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)
9029#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)
9030#define GPIO_OSPEEDR_OSPEED5_Pos (10U)
9031#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)
9032#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
9033#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)
9034#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)
9035#define GPIO_OSPEEDR_OSPEED6_Pos (12U)
9036#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)
9037#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
9038#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)
9039#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)
9040#define GPIO_OSPEEDR_OSPEED7_Pos (14U)
9041#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)
9042#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
9043#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)
9044#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)
9045#define GPIO_OSPEEDR_OSPEED8_Pos (16U)
9046#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)
9047#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
9048#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)
9049#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)
9050#define GPIO_OSPEEDR_OSPEED9_Pos (18U)
9051#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)
9052#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
9053#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)
9054#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)
9055#define GPIO_OSPEEDR_OSPEED10_Pos (20U)
9056#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)
9057#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
9058#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)
9059#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)
9060#define GPIO_OSPEEDR_OSPEED11_Pos (22U)
9061#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)
9062#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
9063#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)
9064#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)
9065#define GPIO_OSPEEDR_OSPEED12_Pos (24U)
9066#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)
9067#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
9068#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)
9069#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)
9070#define GPIO_OSPEEDR_OSPEED13_Pos (26U)
9071#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)
9072#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
9073#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)
9074#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)
9075#define GPIO_OSPEEDR_OSPEED14_Pos (28U)
9076#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)
9077#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
9078#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)
9079#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)
9080#define GPIO_OSPEEDR_OSPEED15_Pos (30U)
9081#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)
9082#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
9083#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)
9084#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)
9085
9086/* Legacy defines */
9087#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
9088#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
9089#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
9090#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
9091#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
9092#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
9093#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
9094#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
9095#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
9096#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
9097#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
9098#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
9099#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
9100#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
9101#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
9102#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
9103#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
9104#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
9105#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
9106#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
9107#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
9108#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
9109#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
9110#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
9111#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
9112#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
9113#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
9114#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
9115#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
9116#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
9117#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
9118#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
9119#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
9120#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
9121#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
9122#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
9123#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
9124#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
9125#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
9126#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
9127#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
9128#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
9129#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
9130#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
9131#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
9132#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
9133#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
9134#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
9135
9136/****************** Bits definition for GPIO_PUPDR register *****************/
9137#define GPIO_PUPDR_PUPD0_Pos (0U)
9138#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos)
9139#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
9140#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos)
9141#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos)
9142#define GPIO_PUPDR_PUPD1_Pos (2U)
9143#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos)
9144#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
9145#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos)
9146#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos)
9147#define GPIO_PUPDR_PUPD2_Pos (4U)
9148#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos)
9149#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
9150#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos)
9151#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos)
9152#define GPIO_PUPDR_PUPD3_Pos (6U)
9153#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos)
9154#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
9155#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos)
9156#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos)
9157#define GPIO_PUPDR_PUPD4_Pos (8U)
9158#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos)
9159#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
9160#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos)
9161#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos)
9162#define GPIO_PUPDR_PUPD5_Pos (10U)
9163#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos)
9164#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
9165#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos)
9166#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos)
9167#define GPIO_PUPDR_PUPD6_Pos (12U)
9168#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos)
9169#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
9170#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos)
9171#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos)
9172#define GPIO_PUPDR_PUPD7_Pos (14U)
9173#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos)
9174#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
9175#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos)
9176#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos)
9177#define GPIO_PUPDR_PUPD8_Pos (16U)
9178#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos)
9179#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
9180#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos)
9181#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos)
9182#define GPIO_PUPDR_PUPD9_Pos (18U)
9183#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos)
9184#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
9185#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos)
9186#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos)
9187#define GPIO_PUPDR_PUPD10_Pos (20U)
9188#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos)
9189#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
9190#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos)
9191#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos)
9192#define GPIO_PUPDR_PUPD11_Pos (22U)
9193#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos)
9194#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
9195#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos)
9196#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos)
9197#define GPIO_PUPDR_PUPD12_Pos (24U)
9198#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos)
9199#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
9200#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos)
9201#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos)
9202#define GPIO_PUPDR_PUPD13_Pos (26U)
9203#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos)
9204#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
9205#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos)
9206#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos)
9207#define GPIO_PUPDR_PUPD14_Pos (28U)
9208#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos)
9209#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
9210#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos)
9211#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos)
9212#define GPIO_PUPDR_PUPD15_Pos (30U)
9213#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos)
9214#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
9215#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos)
9216#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos)
9217
9218/* Legacy defines */
9219#define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
9220#define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
9221#define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
9222#define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
9223#define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
9224#define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
9225#define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
9226#define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
9227#define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
9228#define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
9229#define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
9230#define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
9231#define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
9232#define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
9233#define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
9234#define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
9235#define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
9236#define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
9237#define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
9238#define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
9239#define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
9240#define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
9241#define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
9242#define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
9243#define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
9244#define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
9245#define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
9246#define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
9247#define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
9248#define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
9249#define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
9250#define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
9251#define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
9252#define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
9253#define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
9254#define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
9255#define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
9256#define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
9257#define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
9258#define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
9259#define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
9260#define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
9261#define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
9262#define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
9263#define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
9264#define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
9265#define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
9266#define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
9267
9268/****************** Bits definition for GPIO_IDR register *******************/
9269#define GPIO_IDR_ID0_Pos (0U)
9270#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos)
9271#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
9272#define GPIO_IDR_ID1_Pos (1U)
9273#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos)
9274#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
9275#define GPIO_IDR_ID2_Pos (2U)
9276#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos)
9277#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
9278#define GPIO_IDR_ID3_Pos (3U)
9279#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos)
9280#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
9281#define GPIO_IDR_ID4_Pos (4U)
9282#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos)
9283#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
9284#define GPIO_IDR_ID5_Pos (5U)
9285#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos)
9286#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
9287#define GPIO_IDR_ID6_Pos (6U)
9288#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos)
9289#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
9290#define GPIO_IDR_ID7_Pos (7U)
9291#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos)
9292#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
9293#define GPIO_IDR_ID8_Pos (8U)
9294#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos)
9295#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
9296#define GPIO_IDR_ID9_Pos (9U)
9297#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos)
9298#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
9299#define GPIO_IDR_ID10_Pos (10U)
9300#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos)
9301#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
9302#define GPIO_IDR_ID11_Pos (11U)
9303#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos)
9304#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
9305#define GPIO_IDR_ID12_Pos (12U)
9306#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos)
9307#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
9308#define GPIO_IDR_ID13_Pos (13U)
9309#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos)
9310#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
9311#define GPIO_IDR_ID14_Pos (14U)
9312#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos)
9313#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
9314#define GPIO_IDR_ID15_Pos (15U)
9315#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos)
9316#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
9317
9318/* Legacy defines */
9319#define GPIO_IDR_IDR_0 GPIO_IDR_ID0
9320#define GPIO_IDR_IDR_1 GPIO_IDR_ID1
9321#define GPIO_IDR_IDR_2 GPIO_IDR_ID2
9322#define GPIO_IDR_IDR_3 GPIO_IDR_ID3
9323#define GPIO_IDR_IDR_4 GPIO_IDR_ID4
9324#define GPIO_IDR_IDR_5 GPIO_IDR_ID5
9325#define GPIO_IDR_IDR_6 GPIO_IDR_ID6
9326#define GPIO_IDR_IDR_7 GPIO_IDR_ID7
9327#define GPIO_IDR_IDR_8 GPIO_IDR_ID8
9328#define GPIO_IDR_IDR_9 GPIO_IDR_ID9
9329#define GPIO_IDR_IDR_10 GPIO_IDR_ID10
9330#define GPIO_IDR_IDR_11 GPIO_IDR_ID11
9331#define GPIO_IDR_IDR_12 GPIO_IDR_ID12
9332#define GPIO_IDR_IDR_13 GPIO_IDR_ID13
9333#define GPIO_IDR_IDR_14 GPIO_IDR_ID14
9334#define GPIO_IDR_IDR_15 GPIO_IDR_ID15
9335
9336/****************** Bits definition for GPIO_ODR register *******************/
9337#define GPIO_ODR_OD0_Pos (0U)
9338#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos)
9339#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
9340#define GPIO_ODR_OD1_Pos (1U)
9341#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos)
9342#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
9343#define GPIO_ODR_OD2_Pos (2U)
9344#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos)
9345#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
9346#define GPIO_ODR_OD3_Pos (3U)
9347#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos)
9348#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
9349#define GPIO_ODR_OD4_Pos (4U)
9350#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos)
9351#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
9352#define GPIO_ODR_OD5_Pos (5U)
9353#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos)
9354#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
9355#define GPIO_ODR_OD6_Pos (6U)
9356#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos)
9357#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
9358#define GPIO_ODR_OD7_Pos (7U)
9359#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos)
9360#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
9361#define GPIO_ODR_OD8_Pos (8U)
9362#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos)
9363#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
9364#define GPIO_ODR_OD9_Pos (9U)
9365#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos)
9366#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
9367#define GPIO_ODR_OD10_Pos (10U)
9368#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos)
9369#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
9370#define GPIO_ODR_OD11_Pos (11U)
9371#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos)
9372#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
9373#define GPIO_ODR_OD12_Pos (12U)
9374#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos)
9375#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
9376#define GPIO_ODR_OD13_Pos (13U)
9377#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos)
9378#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
9379#define GPIO_ODR_OD14_Pos (14U)
9380#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos)
9381#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
9382#define GPIO_ODR_OD15_Pos (15U)
9383#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos)
9384#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
9385/* Legacy defines */
9386#define GPIO_ODR_ODR_0 GPIO_ODR_OD0
9387#define GPIO_ODR_ODR_1 GPIO_ODR_OD1
9388#define GPIO_ODR_ODR_2 GPIO_ODR_OD2
9389#define GPIO_ODR_ODR_3 GPIO_ODR_OD3
9390#define GPIO_ODR_ODR_4 GPIO_ODR_OD4
9391#define GPIO_ODR_ODR_5 GPIO_ODR_OD5
9392#define GPIO_ODR_ODR_6 GPIO_ODR_OD6
9393#define GPIO_ODR_ODR_7 GPIO_ODR_OD7
9394#define GPIO_ODR_ODR_8 GPIO_ODR_OD8
9395#define GPIO_ODR_ODR_9 GPIO_ODR_OD9
9396#define GPIO_ODR_ODR_10 GPIO_ODR_OD10
9397#define GPIO_ODR_ODR_11 GPIO_ODR_OD11
9398#define GPIO_ODR_ODR_12 GPIO_ODR_OD12
9399#define GPIO_ODR_ODR_13 GPIO_ODR_OD13
9400#define GPIO_ODR_ODR_14 GPIO_ODR_OD14
9401#define GPIO_ODR_ODR_15 GPIO_ODR_OD15
9402
9403/****************** Bits definition for GPIO_BSRR register ******************/
9404#define GPIO_BSRR_BS0_Pos (0U)
9405#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos)
9406#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
9407#define GPIO_BSRR_BS1_Pos (1U)
9408#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos)
9409#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
9410#define GPIO_BSRR_BS2_Pos (2U)
9411#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos)
9412#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
9413#define GPIO_BSRR_BS3_Pos (3U)
9414#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos)
9415#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
9416#define GPIO_BSRR_BS4_Pos (4U)
9417#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos)
9418#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
9419#define GPIO_BSRR_BS5_Pos (5U)
9420#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos)
9421#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
9422#define GPIO_BSRR_BS6_Pos (6U)
9423#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos)
9424#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
9425#define GPIO_BSRR_BS7_Pos (7U)
9426#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos)
9427#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
9428#define GPIO_BSRR_BS8_Pos (8U)
9429#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos)
9430#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
9431#define GPIO_BSRR_BS9_Pos (9U)
9432#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos)
9433#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
9434#define GPIO_BSRR_BS10_Pos (10U)
9435#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos)
9436#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
9437#define GPIO_BSRR_BS11_Pos (11U)
9438#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos)
9439#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
9440#define GPIO_BSRR_BS12_Pos (12U)
9441#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos)
9442#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
9443#define GPIO_BSRR_BS13_Pos (13U)
9444#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos)
9445#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
9446#define GPIO_BSRR_BS14_Pos (14U)
9447#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos)
9448#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
9449#define GPIO_BSRR_BS15_Pos (15U)
9450#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos)
9451#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
9452#define GPIO_BSRR_BR0_Pos (16U)
9453#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos)
9454#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
9455#define GPIO_BSRR_BR1_Pos (17U)
9456#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos)
9457#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
9458#define GPIO_BSRR_BR2_Pos (18U)
9459#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos)
9460#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
9461#define GPIO_BSRR_BR3_Pos (19U)
9462#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos)
9463#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
9464#define GPIO_BSRR_BR4_Pos (20U)
9465#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos)
9466#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
9467#define GPIO_BSRR_BR5_Pos (21U)
9468#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos)
9469#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
9470#define GPIO_BSRR_BR6_Pos (22U)
9471#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos)
9472#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
9473#define GPIO_BSRR_BR7_Pos (23U)
9474#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos)
9475#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
9476#define GPIO_BSRR_BR8_Pos (24U)
9477#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos)
9478#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
9479#define GPIO_BSRR_BR9_Pos (25U)
9480#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos)
9481#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
9482#define GPIO_BSRR_BR10_Pos (26U)
9483#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos)
9484#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
9485#define GPIO_BSRR_BR11_Pos (27U)
9486#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos)
9487#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
9488#define GPIO_BSRR_BR12_Pos (28U)
9489#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos)
9490#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
9491#define GPIO_BSRR_BR13_Pos (29U)
9492#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos)
9493#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
9494#define GPIO_BSRR_BR14_Pos (30U)
9495#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos)
9496#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
9497#define GPIO_BSRR_BR15_Pos (31U)
9498#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos)
9499#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
9500
9501/* Legacy defines */
9502#define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
9503#define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
9504#define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
9505#define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
9506#define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
9507#define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
9508#define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
9509#define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
9510#define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
9511#define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
9512#define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
9513#define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
9514#define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
9515#define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
9516#define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
9517#define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
9518#define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
9519#define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
9520#define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
9521#define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
9522#define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
9523#define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
9524#define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
9525#define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
9526#define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
9527#define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
9528#define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
9529#define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
9530#define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
9531#define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
9532#define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
9533#define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
9534#define GPIO_BRR_BR0 GPIO_BSRR_BR0
9535#define GPIO_BRR_BR0_Pos GPIO_BSRR_BR0_Pos
9536#define GPIO_BRR_BR0_Msk GPIO_BSRR_BR0_Msk
9537#define GPIO_BRR_BR1 GPIO_BSRR_BR1
9538#define GPIO_BRR_BR1_Pos GPIO_BSRR_BR1_Pos
9539#define GPIO_BRR_BR1_Msk GPIO_BSRR_BR1_Msk
9540#define GPIO_BRR_BR2 GPIO_BSRR_BR2
9541#define GPIO_BRR_BR2_Pos GPIO_BSRR_BR2_Pos
9542#define GPIO_BRR_BR2_Msk GPIO_BSRR_BR2_Msk
9543#define GPIO_BRR_BR3 GPIO_BSRR_BR3
9544#define GPIO_BRR_BR3_Pos GPIO_BSRR_BR3_Pos
9545#define GPIO_BRR_BR3_Msk GPIO_BSRR_BR3_Msk
9546#define GPIO_BRR_BR4 GPIO_BSRR_BR4
9547#define GPIO_BRR_BR4_Pos GPIO_BSRR_BR4_Pos
9548#define GPIO_BRR_BR4_Msk GPIO_BSRR_BR4_Msk
9549#define GPIO_BRR_BR5 GPIO_BSRR_BR5
9550#define GPIO_BRR_BR5_Pos GPIO_BSRR_BR5_Pos
9551#define GPIO_BRR_BR5_Msk GPIO_BSRR_BR5_Msk
9552#define GPIO_BRR_BR6 GPIO_BSRR_BR6
9553#define GPIO_BRR_BR6_Pos GPIO_BSRR_BR6_Pos
9554#define GPIO_BRR_BR6_Msk GPIO_BSRR_BR6_Msk
9555#define GPIO_BRR_BR7 GPIO_BSRR_BR7
9556#define GPIO_BRR_BR7_Pos GPIO_BSRR_BR7_Pos
9557#define GPIO_BRR_BR7_Msk GPIO_BSRR_BR7_Msk
9558#define GPIO_BRR_BR8 GPIO_BSRR_BR8
9559#define GPIO_BRR_BR8_Pos GPIO_BSRR_BR8_Pos
9560#define GPIO_BRR_BR8_Msk GPIO_BSRR_BR8_Msk
9561#define GPIO_BRR_BR9 GPIO_BSRR_BR9
9562#define GPIO_BRR_BR9_Pos GPIO_BSRR_BR9_Pos
9563#define GPIO_BRR_BR9_Msk GPIO_BSRR_BR9_Msk
9564#define GPIO_BRR_BR10 GPIO_BSRR_BR10
9565#define GPIO_BRR_BR10_Pos GPIO_BSRR_BR10_Pos
9566#define GPIO_BRR_BR10_Msk GPIO_BSRR_BR10_Msk
9567#define GPIO_BRR_BR11 GPIO_BSRR_BR11
9568#define GPIO_BRR_BR11_Pos GPIO_BSRR_BR11_Pos
9569#define GPIO_BRR_BR11_Msk GPIO_BSRR_BR11_Msk
9570#define GPIO_BRR_BR12 GPIO_BSRR_BR12
9571#define GPIO_BRR_BR12_Pos GPIO_BSRR_BR12_Pos
9572#define GPIO_BRR_BR12_Msk GPIO_BSRR_BR12_Msk
9573#define GPIO_BRR_BR13 GPIO_BSRR_BR13
9574#define GPIO_BRR_BR13_Pos GPIO_BSRR_BR13_Pos
9575#define GPIO_BRR_BR13_Msk GPIO_BSRR_BR13_Msk
9576#define GPIO_BRR_BR14 GPIO_BSRR_BR14
9577#define GPIO_BRR_BR14_Pos GPIO_BSRR_BR14_Pos
9578#define GPIO_BRR_BR14_Msk GPIO_BSRR_BR14_Msk
9579#define GPIO_BRR_BR15 GPIO_BSRR_BR15
9580#define GPIO_BRR_BR15_Pos GPIO_BSRR_BR15_Pos
9581#define GPIO_BRR_BR15_Msk GPIO_BSRR_BR15_Msk
9582/****************** Bit definition for GPIO_LCKR register *********************/
9583#define GPIO_LCKR_LCK0_Pos (0U)
9584#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos)
9585#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
9586#define GPIO_LCKR_LCK1_Pos (1U)
9587#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos)
9588#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
9589#define GPIO_LCKR_LCK2_Pos (2U)
9590#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos)
9591#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
9592#define GPIO_LCKR_LCK3_Pos (3U)
9593#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos)
9594#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
9595#define GPIO_LCKR_LCK4_Pos (4U)
9596#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos)
9597#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
9598#define GPIO_LCKR_LCK5_Pos (5U)
9599#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos)
9600#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
9601#define GPIO_LCKR_LCK6_Pos (6U)
9602#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos)
9603#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
9604#define GPIO_LCKR_LCK7_Pos (7U)
9605#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos)
9606#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
9607#define GPIO_LCKR_LCK8_Pos (8U)
9608#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos)
9609#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
9610#define GPIO_LCKR_LCK9_Pos (9U)
9611#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos)
9612#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
9613#define GPIO_LCKR_LCK10_Pos (10U)
9614#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos)
9615#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
9616#define GPIO_LCKR_LCK11_Pos (11U)
9617#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos)
9618#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
9619#define GPIO_LCKR_LCK12_Pos (12U)
9620#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos)
9621#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
9622#define GPIO_LCKR_LCK13_Pos (13U)
9623#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos)
9624#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
9625#define GPIO_LCKR_LCK14_Pos (14U)
9626#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos)
9627#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
9628#define GPIO_LCKR_LCK15_Pos (15U)
9629#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos)
9630#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
9631#define GPIO_LCKR_LCKK_Pos (16U)
9632#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos)
9633#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
9634/****************** Bit definition for GPIO_AFRL register *********************/
9635#define GPIO_AFRL_AFSEL0_Pos (0U)
9636#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos)
9637#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
9638#define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos)
9639#define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos)
9640#define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos)
9641#define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos)
9642#define GPIO_AFRL_AFSEL1_Pos (4U)
9643#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos)
9644#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
9645#define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos)
9646#define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos)
9647#define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos)
9648#define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos)
9649#define GPIO_AFRL_AFSEL2_Pos (8U)
9650#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos)
9651#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
9652#define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos)
9653#define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos)
9654#define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos)
9655#define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos)
9656#define GPIO_AFRL_AFSEL3_Pos (12U)
9657#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos)
9658#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
9659#define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos)
9660#define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos)
9661#define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos)
9662#define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos)
9663#define GPIO_AFRL_AFSEL4_Pos (16U)
9664#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos)
9665#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
9666#define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos)
9667#define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos)
9668#define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos)
9669#define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos)
9670#define GPIO_AFRL_AFSEL5_Pos (20U)
9671#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos)
9672#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
9673#define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos)
9674#define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos)
9675#define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos)
9676#define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos)
9677#define GPIO_AFRL_AFSEL6_Pos (24U)
9678#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos)
9679#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
9680#define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos)
9681#define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos)
9682#define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos)
9683#define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos)
9684#define GPIO_AFRL_AFSEL7_Pos (28U)
9685#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos)
9686#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
9687#define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos)
9688#define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos)
9689#define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos)
9690#define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos)
9691
9692/* Legacy defines */
9693#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
9694#define GPIO_AFRL_AFRL0_0 GPIO_AFRL_AFSEL0_0
9695#define GPIO_AFRL_AFRL0_1 GPIO_AFRL_AFSEL0_1
9696#define GPIO_AFRL_AFRL0_2 GPIO_AFRL_AFSEL0_2
9697#define GPIO_AFRL_AFRL0_3 GPIO_AFRL_AFSEL0_3
9698#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
9699#define GPIO_AFRL_AFRL1_0 GPIO_AFRL_AFSEL1_0
9700#define GPIO_AFRL_AFRL1_1 GPIO_AFRL_AFSEL1_1
9701#define GPIO_AFRL_AFRL1_2 GPIO_AFRL_AFSEL1_2
9702#define GPIO_AFRL_AFRL1_3 GPIO_AFRL_AFSEL1_3
9703#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
9704#define GPIO_AFRL_AFRL2_0 GPIO_AFRL_AFSEL2_0
9705#define GPIO_AFRL_AFRL2_1 GPIO_AFRL_AFSEL2_1
9706#define GPIO_AFRL_AFRL2_2 GPIO_AFRL_AFSEL2_2
9707#define GPIO_AFRL_AFRL2_3 GPIO_AFRL_AFSEL2_3
9708#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
9709#define GPIO_AFRL_AFRL3_0 GPIO_AFRL_AFSEL3_0
9710#define GPIO_AFRL_AFRL3_1 GPIO_AFRL_AFSEL3_1
9711#define GPIO_AFRL_AFRL3_2 GPIO_AFRL_AFSEL3_2
9712#define GPIO_AFRL_AFRL3_3 GPIO_AFRL_AFSEL3_3
9713#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
9714#define GPIO_AFRL_AFRL4_0 GPIO_AFRL_AFSEL4_0
9715#define GPIO_AFRL_AFRL4_1 GPIO_AFRL_AFSEL4_1
9716#define GPIO_AFRL_AFRL4_2 GPIO_AFRL_AFSEL4_2
9717#define GPIO_AFRL_AFRL4_3 GPIO_AFRL_AFSEL4_3
9718#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
9719#define GPIO_AFRL_AFRL5_0 GPIO_AFRL_AFSEL5_0
9720#define GPIO_AFRL_AFRL5_1 GPIO_AFRL_AFSEL5_1
9721#define GPIO_AFRL_AFRL5_2 GPIO_AFRL_AFSEL5_2
9722#define GPIO_AFRL_AFRL5_3 GPIO_AFRL_AFSEL5_3
9723#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
9724#define GPIO_AFRL_AFRL6_0 GPIO_AFRL_AFSEL6_0
9725#define GPIO_AFRL_AFRL6_1 GPIO_AFRL_AFSEL6_1
9726#define GPIO_AFRL_AFRL6_2 GPIO_AFRL_AFSEL6_2
9727#define GPIO_AFRL_AFRL6_3 GPIO_AFRL_AFSEL6_3
9728#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
9729#define GPIO_AFRL_AFRL7_0 GPIO_AFRL_AFSEL7_0
9730#define GPIO_AFRL_AFRL7_1 GPIO_AFRL_AFSEL7_1
9731#define GPIO_AFRL_AFRL7_2 GPIO_AFRL_AFSEL7_2
9732#define GPIO_AFRL_AFRL7_3 GPIO_AFRL_AFSEL7_3
9733
9734/****************** Bit definition for GPIO_AFRH register *********************/
9735#define GPIO_AFRH_AFSEL8_Pos (0U)
9736#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos)
9737#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
9738#define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos)
9739#define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos)
9740#define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos)
9741#define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos)
9742#define GPIO_AFRH_AFSEL9_Pos (4U)
9743#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos)
9744#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
9745#define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos)
9746#define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos)
9747#define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos)
9748#define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos)
9749#define GPIO_AFRH_AFSEL10_Pos (8U)
9750#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos)
9751#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
9752#define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos)
9753#define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos)
9754#define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos)
9755#define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos)
9756#define GPIO_AFRH_AFSEL11_Pos (12U)
9757#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos)
9758#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
9759#define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos)
9760#define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos)
9761#define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos)
9762#define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos)
9763#define GPIO_AFRH_AFSEL12_Pos (16U)
9764#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos)
9765#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
9766#define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos)
9767#define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos)
9768#define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos)
9769#define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos)
9770#define GPIO_AFRH_AFSEL13_Pos (20U)
9771#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos)
9772#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
9773#define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos)
9774#define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos)
9775#define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos)
9776#define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos)
9777#define GPIO_AFRH_AFSEL14_Pos (24U)
9778#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos)
9779#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
9780#define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos)
9781#define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos)
9782#define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos)
9783#define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos)
9784#define GPIO_AFRH_AFSEL15_Pos (28U)
9785#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos)
9786#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
9787#define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos)
9788#define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos)
9789#define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos)
9790#define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos)
9791
9792/* Legacy defines */
9793#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
9794#define GPIO_AFRH_AFRH0_0 GPIO_AFRH_AFSEL8_0
9795#define GPIO_AFRH_AFRH0_1 GPIO_AFRH_AFSEL8_1
9796#define GPIO_AFRH_AFRH0_2 GPIO_AFRH_AFSEL8_2
9797#define GPIO_AFRH_AFRH0_3 GPIO_AFRH_AFSEL8_3
9798#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
9799#define GPIO_AFRH_AFRH1_0 GPIO_AFRH_AFSEL9_0
9800#define GPIO_AFRH_AFRH1_1 GPIO_AFRH_AFSEL9_1
9801#define GPIO_AFRH_AFRH1_2 GPIO_AFRH_AFSEL9_2
9802#define GPIO_AFRH_AFRH1_3 GPIO_AFRH_AFSEL9_3
9803#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
9804#define GPIO_AFRH_AFRH2_0 GPIO_AFRH_AFSEL10_0
9805#define GPIO_AFRH_AFRH2_1 GPIO_AFRH_AFSEL10_1
9806#define GPIO_AFRH_AFRH2_2 GPIO_AFRH_AFSEL10_2
9807#define GPIO_AFRH_AFRH2_3 GPIO_AFRH_AFSEL10_3
9808#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
9809#define GPIO_AFRH_AFRH3_0 GPIO_AFRH_AFSEL11_0
9810#define GPIO_AFRH_AFRH3_1 GPIO_AFRH_AFSEL11_1
9811#define GPIO_AFRH_AFRH3_2 GPIO_AFRH_AFSEL11_2
9812#define GPIO_AFRH_AFRH3_3 GPIO_AFRH_AFSEL11_3
9813#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
9814#define GPIO_AFRH_AFRH4_0 GPIO_AFRH_AFSEL12_0
9815#define GPIO_AFRH_AFRH4_1 GPIO_AFRH_AFSEL12_1
9816#define GPIO_AFRH_AFRH4_2 GPIO_AFRH_AFSEL12_2
9817#define GPIO_AFRH_AFRH4_3 GPIO_AFRH_AFSEL12_3
9818#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
9819#define GPIO_AFRH_AFRH5_0 GPIO_AFRH_AFSEL13_0
9820#define GPIO_AFRH_AFRH5_1 GPIO_AFRH_AFSEL13_1
9821#define GPIO_AFRH_AFRH5_2 GPIO_AFRH_AFSEL13_2
9822#define GPIO_AFRH_AFRH5_3 GPIO_AFRH_AFSEL13_3
9823#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
9824#define GPIO_AFRH_AFRH6_0 GPIO_AFRH_AFSEL14_0
9825#define GPIO_AFRH_AFRH6_1 GPIO_AFRH_AFSEL14_1
9826#define GPIO_AFRH_AFRH6_2 GPIO_AFRH_AFSEL14_2
9827#define GPIO_AFRH_AFRH6_3 GPIO_AFRH_AFSEL14_3
9828#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
9829#define GPIO_AFRH_AFRH7_0 GPIO_AFRH_AFSEL15_0
9830#define GPIO_AFRH_AFRH7_1 GPIO_AFRH_AFSEL15_1
9831#define GPIO_AFRH_AFRH7_2 GPIO_AFRH_AFSEL15_2
9832#define GPIO_AFRH_AFRH7_3 GPIO_AFRH_AFSEL15_3
9833
9834
9835/******************************************************************************/
9836/* */
9837/* Inter-integrated Circuit Interface */
9838/* */
9839/******************************************************************************/
9840/******************* Bit definition for I2C_CR1 register ********************/
9841#define I2C_CR1_PE_Pos (0U)
9842#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos)
9843#define I2C_CR1_PE I2C_CR1_PE_Msk
9844#define I2C_CR1_SMBUS_Pos (1U)
9845#define I2C_CR1_SMBUS_Msk (0x1UL << I2C_CR1_SMBUS_Pos)
9846#define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk
9847#define I2C_CR1_SMBTYPE_Pos (3U)
9848#define I2C_CR1_SMBTYPE_Msk (0x1UL << I2C_CR1_SMBTYPE_Pos)
9849#define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk
9850#define I2C_CR1_ENARP_Pos (4U)
9851#define I2C_CR1_ENARP_Msk (0x1UL << I2C_CR1_ENARP_Pos)
9852#define I2C_CR1_ENARP I2C_CR1_ENARP_Msk
9853#define I2C_CR1_ENPEC_Pos (5U)
9854#define I2C_CR1_ENPEC_Msk (0x1UL << I2C_CR1_ENPEC_Pos)
9855#define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk
9856#define I2C_CR1_ENGC_Pos (6U)
9857#define I2C_CR1_ENGC_Msk (0x1UL << I2C_CR1_ENGC_Pos)
9858#define I2C_CR1_ENGC I2C_CR1_ENGC_Msk
9859#define I2C_CR1_NOSTRETCH_Pos (7U)
9860#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos)
9861#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk
9862#define I2C_CR1_START_Pos (8U)
9863#define I2C_CR1_START_Msk (0x1UL << I2C_CR1_START_Pos)
9864#define I2C_CR1_START I2C_CR1_START_Msk
9865#define I2C_CR1_STOP_Pos (9U)
9866#define I2C_CR1_STOP_Msk (0x1UL << I2C_CR1_STOP_Pos)
9867#define I2C_CR1_STOP I2C_CR1_STOP_Msk
9868#define I2C_CR1_ACK_Pos (10U)
9869#define I2C_CR1_ACK_Msk (0x1UL << I2C_CR1_ACK_Pos)
9870#define I2C_CR1_ACK I2C_CR1_ACK_Msk
9871#define I2C_CR1_POS_Pos (11U)
9872#define I2C_CR1_POS_Msk (0x1UL << I2C_CR1_POS_Pos)
9873#define I2C_CR1_POS I2C_CR1_POS_Msk
9874#define I2C_CR1_PEC_Pos (12U)
9875#define I2C_CR1_PEC_Msk (0x1UL << I2C_CR1_PEC_Pos)
9876#define I2C_CR1_PEC I2C_CR1_PEC_Msk
9877#define I2C_CR1_ALERT_Pos (13U)
9878#define I2C_CR1_ALERT_Msk (0x1UL << I2C_CR1_ALERT_Pos)
9879#define I2C_CR1_ALERT I2C_CR1_ALERT_Msk
9880#define I2C_CR1_SWRST_Pos (15U)
9881#define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos)
9882#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk
9883
9884/******************* Bit definition for I2C_CR2 register ********************/
9885#define I2C_CR2_FREQ_Pos (0U)
9886#define I2C_CR2_FREQ_Msk (0x3FUL << I2C_CR2_FREQ_Pos)
9887#define I2C_CR2_FREQ I2C_CR2_FREQ_Msk
9888#define I2C_CR2_FREQ_0 (0x01UL << I2C_CR2_FREQ_Pos)
9889#define I2C_CR2_FREQ_1 (0x02UL << I2C_CR2_FREQ_Pos)
9890#define I2C_CR2_FREQ_2 (0x04UL << I2C_CR2_FREQ_Pos)
9891#define I2C_CR2_FREQ_3 (0x08UL << I2C_CR2_FREQ_Pos)
9892#define I2C_CR2_FREQ_4 (0x10UL << I2C_CR2_FREQ_Pos)
9893#define I2C_CR2_FREQ_5 (0x20UL << I2C_CR2_FREQ_Pos)
9894
9895#define I2C_CR2_ITERREN_Pos (8U)
9896#define I2C_CR2_ITERREN_Msk (0x1UL << I2C_CR2_ITERREN_Pos)
9897#define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk
9898#define I2C_CR2_ITEVTEN_Pos (9U)
9899#define I2C_CR2_ITEVTEN_Msk (0x1UL << I2C_CR2_ITEVTEN_Pos)
9900#define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk
9901#define I2C_CR2_ITBUFEN_Pos (10U)
9902#define I2C_CR2_ITBUFEN_Msk (0x1UL << I2C_CR2_ITBUFEN_Pos)
9903#define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk
9904#define I2C_CR2_DMAEN_Pos (11U)
9905#define I2C_CR2_DMAEN_Msk (0x1UL << I2C_CR2_DMAEN_Pos)
9906#define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk
9907#define I2C_CR2_LAST_Pos (12U)
9908#define I2C_CR2_LAST_Msk (0x1UL << I2C_CR2_LAST_Pos)
9909#define I2C_CR2_LAST I2C_CR2_LAST_Msk
9910
9911/******************* Bit definition for I2C_OAR1 register *******************/
9912#define I2C_OAR1_ADD1_7 0x000000FEU
9913#define I2C_OAR1_ADD8_9 0x00000300U
9914
9915#define I2C_OAR1_ADD0_Pos (0U)
9916#define I2C_OAR1_ADD0_Msk (0x1UL << I2C_OAR1_ADD0_Pos)
9917#define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk
9918#define I2C_OAR1_ADD1_Pos (1U)
9919#define I2C_OAR1_ADD1_Msk (0x1UL << I2C_OAR1_ADD1_Pos)
9920#define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk
9921#define I2C_OAR1_ADD2_Pos (2U)
9922#define I2C_OAR1_ADD2_Msk (0x1UL << I2C_OAR1_ADD2_Pos)
9923#define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk
9924#define I2C_OAR1_ADD3_Pos (3U)
9925#define I2C_OAR1_ADD3_Msk (0x1UL << I2C_OAR1_ADD3_Pos)
9926#define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk
9927#define I2C_OAR1_ADD4_Pos (4U)
9928#define I2C_OAR1_ADD4_Msk (0x1UL << I2C_OAR1_ADD4_Pos)
9929#define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk
9930#define I2C_OAR1_ADD5_Pos (5U)
9931#define I2C_OAR1_ADD5_Msk (0x1UL << I2C_OAR1_ADD5_Pos)
9932#define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk
9933#define I2C_OAR1_ADD6_Pos (6U)
9934#define I2C_OAR1_ADD6_Msk (0x1UL << I2C_OAR1_ADD6_Pos)
9935#define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk
9936#define I2C_OAR1_ADD7_Pos (7U)
9937#define I2C_OAR1_ADD7_Msk (0x1UL << I2C_OAR1_ADD7_Pos)
9938#define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk
9939#define I2C_OAR1_ADD8_Pos (8U)
9940#define I2C_OAR1_ADD8_Msk (0x1UL << I2C_OAR1_ADD8_Pos)
9941#define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk
9942#define I2C_OAR1_ADD9_Pos (9U)
9943#define I2C_OAR1_ADD9_Msk (0x1UL << I2C_OAR1_ADD9_Pos)
9944#define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk
9945
9946#define I2C_OAR1_ADDMODE_Pos (15U)
9947#define I2C_OAR1_ADDMODE_Msk (0x1UL << I2C_OAR1_ADDMODE_Pos)
9948#define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk
9949
9950/******************* Bit definition for I2C_OAR2 register *******************/
9951#define I2C_OAR2_ENDUAL_Pos (0U)
9952#define I2C_OAR2_ENDUAL_Msk (0x1UL << I2C_OAR2_ENDUAL_Pos)
9953#define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk
9954#define I2C_OAR2_ADD2_Pos (1U)
9955#define I2C_OAR2_ADD2_Msk (0x7FUL << I2C_OAR2_ADD2_Pos)
9956#define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk
9957
9958/******************** Bit definition for I2C_DR register ********************/
9959#define I2C_DR_DR_Pos (0U)
9960#define I2C_DR_DR_Msk (0xFFUL << I2C_DR_DR_Pos)
9961#define I2C_DR_DR I2C_DR_DR_Msk
9962
9963/******************* Bit definition for I2C_SR1 register ********************/
9964#define I2C_SR1_SB_Pos (0U)
9965#define I2C_SR1_SB_Msk (0x1UL << I2C_SR1_SB_Pos)
9966#define I2C_SR1_SB I2C_SR1_SB_Msk
9967#define I2C_SR1_ADDR_Pos (1U)
9968#define I2C_SR1_ADDR_Msk (0x1UL << I2C_SR1_ADDR_Pos)
9969#define I2C_SR1_ADDR I2C_SR1_ADDR_Msk
9970#define I2C_SR1_BTF_Pos (2U)
9971#define I2C_SR1_BTF_Msk (0x1UL << I2C_SR1_BTF_Pos)
9972#define I2C_SR1_BTF I2C_SR1_BTF_Msk
9973#define I2C_SR1_ADD10_Pos (3U)
9974#define I2C_SR1_ADD10_Msk (0x1UL << I2C_SR1_ADD10_Pos)
9975#define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk
9976#define I2C_SR1_STOPF_Pos (4U)
9977#define I2C_SR1_STOPF_Msk (0x1UL << I2C_SR1_STOPF_Pos)
9978#define I2C_SR1_STOPF I2C_SR1_STOPF_Msk
9979#define I2C_SR1_RXNE_Pos (6U)
9980#define I2C_SR1_RXNE_Msk (0x1UL << I2C_SR1_RXNE_Pos)
9981#define I2C_SR1_RXNE I2C_SR1_RXNE_Msk
9982#define I2C_SR1_TXE_Pos (7U)
9983#define I2C_SR1_TXE_Msk (0x1UL << I2C_SR1_TXE_Pos)
9984#define I2C_SR1_TXE I2C_SR1_TXE_Msk
9985#define I2C_SR1_BERR_Pos (8U)
9986#define I2C_SR1_BERR_Msk (0x1UL << I2C_SR1_BERR_Pos)
9987#define I2C_SR1_BERR I2C_SR1_BERR_Msk
9988#define I2C_SR1_ARLO_Pos (9U)
9989#define I2C_SR1_ARLO_Msk (0x1UL << I2C_SR1_ARLO_Pos)
9990#define I2C_SR1_ARLO I2C_SR1_ARLO_Msk
9991#define I2C_SR1_AF_Pos (10U)
9992#define I2C_SR1_AF_Msk (0x1UL << I2C_SR1_AF_Pos)
9993#define I2C_SR1_AF I2C_SR1_AF_Msk
9994#define I2C_SR1_OVR_Pos (11U)
9995#define I2C_SR1_OVR_Msk (0x1UL << I2C_SR1_OVR_Pos)
9996#define I2C_SR1_OVR I2C_SR1_OVR_Msk
9997#define I2C_SR1_PECERR_Pos (12U)
9998#define I2C_SR1_PECERR_Msk (0x1UL << I2C_SR1_PECERR_Pos)
9999#define I2C_SR1_PECERR I2C_SR1_PECERR_Msk
10000#define I2C_SR1_TIMEOUT_Pos (14U)
10001#define I2C_SR1_TIMEOUT_Msk (0x1UL << I2C_SR1_TIMEOUT_Pos)
10002#define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk
10003#define I2C_SR1_SMBALERT_Pos (15U)
10004#define I2C_SR1_SMBALERT_Msk (0x1UL << I2C_SR1_SMBALERT_Pos)
10005#define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk
10006
10007/******************* Bit definition for I2C_SR2 register ********************/
10008#define I2C_SR2_MSL_Pos (0U)
10009#define I2C_SR2_MSL_Msk (0x1UL << I2C_SR2_MSL_Pos)
10010#define I2C_SR2_MSL I2C_SR2_MSL_Msk
10011#define I2C_SR2_BUSY_Pos (1U)
10012#define I2C_SR2_BUSY_Msk (0x1UL << I2C_SR2_BUSY_Pos)
10013#define I2C_SR2_BUSY I2C_SR2_BUSY_Msk
10014#define I2C_SR2_TRA_Pos (2U)
10015#define I2C_SR2_TRA_Msk (0x1UL << I2C_SR2_TRA_Pos)
10016#define I2C_SR2_TRA I2C_SR2_TRA_Msk
10017#define I2C_SR2_GENCALL_Pos (4U)
10018#define I2C_SR2_GENCALL_Msk (0x1UL << I2C_SR2_GENCALL_Pos)
10019#define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk
10020#define I2C_SR2_SMBDEFAULT_Pos (5U)
10021#define I2C_SR2_SMBDEFAULT_Msk (0x1UL << I2C_SR2_SMBDEFAULT_Pos)
10022#define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk
10023#define I2C_SR2_SMBHOST_Pos (6U)
10024#define I2C_SR2_SMBHOST_Msk (0x1UL << I2C_SR2_SMBHOST_Pos)
10025#define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk
10026#define I2C_SR2_DUALF_Pos (7U)
10027#define I2C_SR2_DUALF_Msk (0x1UL << I2C_SR2_DUALF_Pos)
10028#define I2C_SR2_DUALF I2C_SR2_DUALF_Msk
10029#define I2C_SR2_PEC_Pos (8U)
10030#define I2C_SR2_PEC_Msk (0xFFUL << I2C_SR2_PEC_Pos)
10031#define I2C_SR2_PEC I2C_SR2_PEC_Msk
10032
10033/******************* Bit definition for I2C_CCR register ********************/
10034#define I2C_CCR_CCR_Pos (0U)
10035#define I2C_CCR_CCR_Msk (0xFFFUL << I2C_CCR_CCR_Pos)
10036#define I2C_CCR_CCR I2C_CCR_CCR_Msk
10037#define I2C_CCR_DUTY_Pos (14U)
10038#define I2C_CCR_DUTY_Msk (0x1UL << I2C_CCR_DUTY_Pos)
10039#define I2C_CCR_DUTY I2C_CCR_DUTY_Msk
10040#define I2C_CCR_FS_Pos (15U)
10041#define I2C_CCR_FS_Msk (0x1UL << I2C_CCR_FS_Pos)
10042#define I2C_CCR_FS I2C_CCR_FS_Msk
10043
10044/****************** Bit definition for I2C_TRISE register *******************/
10045#define I2C_TRISE_TRISE_Pos (0U)
10046#define I2C_TRISE_TRISE_Msk (0x3FUL << I2C_TRISE_TRISE_Pos)
10047#define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk
10048
10049/****************** Bit definition for I2C_FLTR register *******************/
10050#define I2C_FLTR_DNF_Pos (0U)
10051#define I2C_FLTR_DNF_Msk (0xFUL << I2C_FLTR_DNF_Pos)
10052#define I2C_FLTR_DNF I2C_FLTR_DNF_Msk
10053#define I2C_FLTR_ANOFF_Pos (4U)
10054#define I2C_FLTR_ANOFF_Msk (0x1UL << I2C_FLTR_ANOFF_Pos)
10055#define I2C_FLTR_ANOFF I2C_FLTR_ANOFF_Msk
10056
10057/******************************************************************************/
10058/* */
10059/* Independent WATCHDOG */
10060/* */
10061/******************************************************************************/
10062/******************* Bit definition for IWDG_KR register ********************/
10063#define IWDG_KR_KEY_Pos (0U)
10064#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos)
10065#define IWDG_KR_KEY IWDG_KR_KEY_Msk
10066
10067/******************* Bit definition for IWDG_PR register ********************/
10068#define IWDG_PR_PR_Pos (0U)
10069#define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos)
10070#define IWDG_PR_PR IWDG_PR_PR_Msk
10071#define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos)
10072#define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos)
10073#define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos)
10074
10075/******************* Bit definition for IWDG_RLR register *******************/
10076#define IWDG_RLR_RL_Pos (0U)
10077#define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos)
10078#define IWDG_RLR_RL IWDG_RLR_RL_Msk
10079
10080/******************* Bit definition for IWDG_SR register ********************/
10081#define IWDG_SR_PVU_Pos (0U)
10082#define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos)
10083#define IWDG_SR_PVU IWDG_SR_PVU_Msk
10084#define IWDG_SR_RVU_Pos (1U)
10085#define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos)
10086#define IWDG_SR_RVU IWDG_SR_RVU_Msk
10087
10088
10089/******************************************************************************/
10090/* */
10091/* LCD-TFT Display Controller (LTDC) */
10092/* */
10093/******************************************************************************/
10094
10095/******************** Bit definition for LTDC_SSCR register *****************/
10096
10097#define LTDC_SSCR_VSH_Pos (0U)
10098#define LTDC_SSCR_VSH_Msk (0x7FFUL << LTDC_SSCR_VSH_Pos)
10099#define LTDC_SSCR_VSH LTDC_SSCR_VSH_Msk
10100#define LTDC_SSCR_HSW_Pos (16U)
10101#define LTDC_SSCR_HSW_Msk (0xFFFUL << LTDC_SSCR_HSW_Pos)
10102#define LTDC_SSCR_HSW LTDC_SSCR_HSW_Msk
10103
10104/******************** Bit definition for LTDC_BPCR register *****************/
10105
10106#define LTDC_BPCR_AVBP_Pos (0U)
10107#define LTDC_BPCR_AVBP_Msk (0x7FFUL << LTDC_BPCR_AVBP_Pos)
10108#define LTDC_BPCR_AVBP LTDC_BPCR_AVBP_Msk
10109#define LTDC_BPCR_AHBP_Pos (16U)
10110#define LTDC_BPCR_AHBP_Msk (0xFFFUL << LTDC_BPCR_AHBP_Pos)
10111#define LTDC_BPCR_AHBP LTDC_BPCR_AHBP_Msk
10112
10113/******************** Bit definition for LTDC_AWCR register *****************/
10114
10115#define LTDC_AWCR_AAH_Pos (0U)
10116#define LTDC_AWCR_AAH_Msk (0x7FFUL << LTDC_AWCR_AAH_Pos)
10117#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk
10118#define LTDC_AWCR_AAW_Pos (16U)
10119#define LTDC_AWCR_AAW_Msk (0xFFFUL << LTDC_AWCR_AAW_Pos)
10120#define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk
10121
10122/******************** Bit definition for LTDC_TWCR register *****************/
10123
10124#define LTDC_TWCR_TOTALH_Pos (0U)
10125#define LTDC_TWCR_TOTALH_Msk (0x7FFUL << LTDC_TWCR_TOTALH_Pos)
10126#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk
10127#define LTDC_TWCR_TOTALW_Pos (16U)
10128#define LTDC_TWCR_TOTALW_Msk (0xFFFUL << LTDC_TWCR_TOTALW_Pos)
10129#define LTDC_TWCR_TOTALW LTDC_TWCR_TOTALW_Msk
10130
10131/******************** Bit definition for LTDC_GCR register ******************/
10132
10133#define LTDC_GCR_LTDCEN_Pos (0U)
10134#define LTDC_GCR_LTDCEN_Msk (0x1UL << LTDC_GCR_LTDCEN_Pos)
10135#define LTDC_GCR_LTDCEN LTDC_GCR_LTDCEN_Msk
10136#define LTDC_GCR_DBW_Pos (4U)
10137#define LTDC_GCR_DBW_Msk (0x7UL << LTDC_GCR_DBW_Pos)
10138#define LTDC_GCR_DBW LTDC_GCR_DBW_Msk
10139#define LTDC_GCR_DGW_Pos (8U)
10140#define LTDC_GCR_DGW_Msk (0x7UL << LTDC_GCR_DGW_Pos)
10141#define LTDC_GCR_DGW LTDC_GCR_DGW_Msk
10142#define LTDC_GCR_DRW_Pos (12U)
10143#define LTDC_GCR_DRW_Msk (0x7UL << LTDC_GCR_DRW_Pos)
10144#define LTDC_GCR_DRW LTDC_GCR_DRW_Msk
10145#define LTDC_GCR_DEN_Pos (16U)
10146#define LTDC_GCR_DEN_Msk (0x1UL << LTDC_GCR_DEN_Pos)
10147#define LTDC_GCR_DEN LTDC_GCR_DEN_Msk
10148#define LTDC_GCR_PCPOL_Pos (28U)
10149#define LTDC_GCR_PCPOL_Msk (0x1UL << LTDC_GCR_PCPOL_Pos)
10150#define LTDC_GCR_PCPOL LTDC_GCR_PCPOL_Msk
10151#define LTDC_GCR_DEPOL_Pos (29U)
10152#define LTDC_GCR_DEPOL_Msk (0x1UL << LTDC_GCR_DEPOL_Pos)
10153#define LTDC_GCR_DEPOL LTDC_GCR_DEPOL_Msk
10154#define LTDC_GCR_VSPOL_Pos (30U)
10155#define LTDC_GCR_VSPOL_Msk (0x1UL << LTDC_GCR_VSPOL_Pos)
10156#define LTDC_GCR_VSPOL LTDC_GCR_VSPOL_Msk
10157#define LTDC_GCR_HSPOL_Pos (31U)
10158#define LTDC_GCR_HSPOL_Msk (0x1UL << LTDC_GCR_HSPOL_Pos)
10159#define LTDC_GCR_HSPOL LTDC_GCR_HSPOL_Msk
10160
10161/* Legacy defines */
10162#define LTDC_GCR_DTEN LTDC_GCR_DEN
10163
10164/******************** Bit definition for LTDC_SRCR register *****************/
10165
10166#define LTDC_SRCR_IMR_Pos (0U)
10167#define LTDC_SRCR_IMR_Msk (0x1UL << LTDC_SRCR_IMR_Pos)
10168#define LTDC_SRCR_IMR LTDC_SRCR_IMR_Msk
10169#define LTDC_SRCR_VBR_Pos (1U)
10170#define LTDC_SRCR_VBR_Msk (0x1UL << LTDC_SRCR_VBR_Pos)
10171#define LTDC_SRCR_VBR LTDC_SRCR_VBR_Msk
10172
10173/******************** Bit definition for LTDC_BCCR register *****************/
10174
10175#define LTDC_BCCR_BCBLUE_Pos (0U)
10176#define LTDC_BCCR_BCBLUE_Msk (0xFFUL << LTDC_BCCR_BCBLUE_Pos)
10177#define LTDC_BCCR_BCBLUE LTDC_BCCR_BCBLUE_Msk
10178#define LTDC_BCCR_BCGREEN_Pos (8U)
10179#define LTDC_BCCR_BCGREEN_Msk (0xFFUL << LTDC_BCCR_BCGREEN_Pos)
10180#define LTDC_BCCR_BCGREEN LTDC_BCCR_BCGREEN_Msk
10181#define LTDC_BCCR_BCRED_Pos (16U)
10182#define LTDC_BCCR_BCRED_Msk (0xFFUL << LTDC_BCCR_BCRED_Pos)
10183#define LTDC_BCCR_BCRED LTDC_BCCR_BCRED_Msk
10184
10185/******************** Bit definition for LTDC_IER register ******************/
10186
10187#define LTDC_IER_LIE_Pos (0U)
10188#define LTDC_IER_LIE_Msk (0x1UL << LTDC_IER_LIE_Pos)
10189#define LTDC_IER_LIE LTDC_IER_LIE_Msk
10190#define LTDC_IER_FUIE_Pos (1U)
10191#define LTDC_IER_FUIE_Msk (0x1UL << LTDC_IER_FUIE_Pos)
10192#define LTDC_IER_FUIE LTDC_IER_FUIE_Msk
10193#define LTDC_IER_TERRIE_Pos (2U)
10194#define LTDC_IER_TERRIE_Msk (0x1UL << LTDC_IER_TERRIE_Pos)
10195#define LTDC_IER_TERRIE LTDC_IER_TERRIE_Msk
10196#define LTDC_IER_RRIE_Pos (3U)
10197#define LTDC_IER_RRIE_Msk (0x1UL << LTDC_IER_RRIE_Pos)
10198#define LTDC_IER_RRIE LTDC_IER_RRIE_Msk
10199
10200/******************** Bit definition for LTDC_ISR register ******************/
10201
10202#define LTDC_ISR_LIF_Pos (0U)
10203#define LTDC_ISR_LIF_Msk (0x1UL << LTDC_ISR_LIF_Pos)
10204#define LTDC_ISR_LIF LTDC_ISR_LIF_Msk
10205#define LTDC_ISR_FUIF_Pos (1U)
10206#define LTDC_ISR_FUIF_Msk (0x1UL << LTDC_ISR_FUIF_Pos)
10207#define LTDC_ISR_FUIF LTDC_ISR_FUIF_Msk
10208#define LTDC_ISR_TERRIF_Pos (2U)
10209#define LTDC_ISR_TERRIF_Msk (0x1UL << LTDC_ISR_TERRIF_Pos)
10210#define LTDC_ISR_TERRIF LTDC_ISR_TERRIF_Msk
10211#define LTDC_ISR_RRIF_Pos (3U)
10212#define LTDC_ISR_RRIF_Msk (0x1UL << LTDC_ISR_RRIF_Pos)
10213#define LTDC_ISR_RRIF LTDC_ISR_RRIF_Msk
10214
10215/******************** Bit definition for LTDC_ICR register ******************/
10216
10217#define LTDC_ICR_CLIF_Pos (0U)
10218#define LTDC_ICR_CLIF_Msk (0x1UL << LTDC_ICR_CLIF_Pos)
10219#define LTDC_ICR_CLIF LTDC_ICR_CLIF_Msk
10220#define LTDC_ICR_CFUIF_Pos (1U)
10221#define LTDC_ICR_CFUIF_Msk (0x1UL << LTDC_ICR_CFUIF_Pos)
10222#define LTDC_ICR_CFUIF LTDC_ICR_CFUIF_Msk
10223#define LTDC_ICR_CTERRIF_Pos (2U)
10224#define LTDC_ICR_CTERRIF_Msk (0x1UL << LTDC_ICR_CTERRIF_Pos)
10225#define LTDC_ICR_CTERRIF LTDC_ICR_CTERRIF_Msk
10226#define LTDC_ICR_CRRIF_Pos (3U)
10227#define LTDC_ICR_CRRIF_Msk (0x1UL << LTDC_ICR_CRRIF_Pos)
10228#define LTDC_ICR_CRRIF LTDC_ICR_CRRIF_Msk
10229
10230/******************** Bit definition for LTDC_LIPCR register ****************/
10231
10232#define LTDC_LIPCR_LIPOS_Pos (0U)
10233#define LTDC_LIPCR_LIPOS_Msk (0x7FFUL << LTDC_LIPCR_LIPOS_Pos)
10234#define LTDC_LIPCR_LIPOS LTDC_LIPCR_LIPOS_Msk
10235
10236/******************** Bit definition for LTDC_CPSR register *****************/
10237
10238#define LTDC_CPSR_CYPOS_Pos (0U)
10239#define LTDC_CPSR_CYPOS_Msk (0xFFFFUL << LTDC_CPSR_CYPOS_Pos)
10240#define LTDC_CPSR_CYPOS LTDC_CPSR_CYPOS_Msk
10241#define LTDC_CPSR_CXPOS_Pos (16U)
10242#define LTDC_CPSR_CXPOS_Msk (0xFFFFUL << LTDC_CPSR_CXPOS_Pos)
10243#define LTDC_CPSR_CXPOS LTDC_CPSR_CXPOS_Msk
10244
10245/******************** Bit definition for LTDC_CDSR register *****************/
10246
10247#define LTDC_CDSR_VDES_Pos (0U)
10248#define LTDC_CDSR_VDES_Msk (0x1UL << LTDC_CDSR_VDES_Pos)
10249#define LTDC_CDSR_VDES LTDC_CDSR_VDES_Msk
10250#define LTDC_CDSR_HDES_Pos (1U)
10251#define LTDC_CDSR_HDES_Msk (0x1UL << LTDC_CDSR_HDES_Pos)
10252#define LTDC_CDSR_HDES LTDC_CDSR_HDES_Msk
10253#define LTDC_CDSR_VSYNCS_Pos (2U)
10254#define LTDC_CDSR_VSYNCS_Msk (0x1UL << LTDC_CDSR_VSYNCS_Pos)
10255#define LTDC_CDSR_VSYNCS LTDC_CDSR_VSYNCS_Msk
10256#define LTDC_CDSR_HSYNCS_Pos (3U)
10257#define LTDC_CDSR_HSYNCS_Msk (0x1UL << LTDC_CDSR_HSYNCS_Pos)
10258#define LTDC_CDSR_HSYNCS LTDC_CDSR_HSYNCS_Msk
10259
10260/******************** Bit definition for LTDC_LxCR register *****************/
10261
10262#define LTDC_LxCR_LEN_Pos (0U)
10263#define LTDC_LxCR_LEN_Msk (0x1UL << LTDC_LxCR_LEN_Pos)
10264#define LTDC_LxCR_LEN LTDC_LxCR_LEN_Msk
10265#define LTDC_LxCR_COLKEN_Pos (1U)
10266#define LTDC_LxCR_COLKEN_Msk (0x1UL << LTDC_LxCR_COLKEN_Pos)
10267#define LTDC_LxCR_COLKEN LTDC_LxCR_COLKEN_Msk
10268#define LTDC_LxCR_CLUTEN_Pos (4U)
10269#define LTDC_LxCR_CLUTEN_Msk (0x1UL << LTDC_LxCR_CLUTEN_Pos)
10270#define LTDC_LxCR_CLUTEN LTDC_LxCR_CLUTEN_Msk
10271
10272/******************** Bit definition for LTDC_LxWHPCR register **************/
10273
10274#define LTDC_LxWHPCR_WHSTPOS_Pos (0U)
10275#define LTDC_LxWHPCR_WHSTPOS_Msk (0xFFFUL << LTDC_LxWHPCR_WHSTPOS_Pos)
10276#define LTDC_LxWHPCR_WHSTPOS LTDC_LxWHPCR_WHSTPOS_Msk
10277#define LTDC_LxWHPCR_WHSPPOS_Pos (16U)
10278#define LTDC_LxWHPCR_WHSPPOS_Msk (0xFFFFUL << LTDC_LxWHPCR_WHSPPOS_Pos)
10279#define LTDC_LxWHPCR_WHSPPOS LTDC_LxWHPCR_WHSPPOS_Msk
10280
10281/******************** Bit definition for LTDC_LxWVPCR register **************/
10282
10283#define LTDC_LxWVPCR_WVSTPOS_Pos (0U)
10284#define LTDC_LxWVPCR_WVSTPOS_Msk (0xFFFUL << LTDC_LxWVPCR_WVSTPOS_Pos)
10285#define LTDC_LxWVPCR_WVSTPOS LTDC_LxWVPCR_WVSTPOS_Msk
10286#define LTDC_LxWVPCR_WVSPPOS_Pos (16U)
10287#define LTDC_LxWVPCR_WVSPPOS_Msk (0xFFFFUL << LTDC_LxWVPCR_WVSPPOS_Pos)
10288#define LTDC_LxWVPCR_WVSPPOS LTDC_LxWVPCR_WVSPPOS_Msk
10289
10290/******************** Bit definition for LTDC_LxCKCR register ***************/
10291
10292#define LTDC_LxCKCR_CKBLUE_Pos (0U)
10293#define LTDC_LxCKCR_CKBLUE_Msk (0xFFUL << LTDC_LxCKCR_CKBLUE_Pos)
10294#define LTDC_LxCKCR_CKBLUE LTDC_LxCKCR_CKBLUE_Msk
10295#define LTDC_LxCKCR_CKGREEN_Pos (8U)
10296#define LTDC_LxCKCR_CKGREEN_Msk (0xFFUL << LTDC_LxCKCR_CKGREEN_Pos)
10297#define LTDC_LxCKCR_CKGREEN LTDC_LxCKCR_CKGREEN_Msk
10298#define LTDC_LxCKCR_CKRED_Pos (16U)
10299#define LTDC_LxCKCR_CKRED_Msk (0xFFUL << LTDC_LxCKCR_CKRED_Pos)
10300#define LTDC_LxCKCR_CKRED LTDC_LxCKCR_CKRED_Msk
10301
10302/******************** Bit definition for LTDC_LxPFCR register ***************/
10303
10304#define LTDC_LxPFCR_PF_Pos (0U)
10305#define LTDC_LxPFCR_PF_Msk (0x7UL << LTDC_LxPFCR_PF_Pos)
10306#define LTDC_LxPFCR_PF LTDC_LxPFCR_PF_Msk
10307
10308/******************** Bit definition for LTDC_LxCACR register ***************/
10309
10310#define LTDC_LxCACR_CONSTA_Pos (0U)
10311#define LTDC_LxCACR_CONSTA_Msk (0xFFUL << LTDC_LxCACR_CONSTA_Pos)
10312#define LTDC_LxCACR_CONSTA LTDC_LxCACR_CONSTA_Msk
10313
10314/******************** Bit definition for LTDC_LxDCCR register ***************/
10315
10316#define LTDC_LxDCCR_DCBLUE_Pos (0U)
10317#define LTDC_LxDCCR_DCBLUE_Msk (0xFFUL << LTDC_LxDCCR_DCBLUE_Pos)
10318#define LTDC_LxDCCR_DCBLUE LTDC_LxDCCR_DCBLUE_Msk
10319#define LTDC_LxDCCR_DCGREEN_Pos (8U)
10320#define LTDC_LxDCCR_DCGREEN_Msk (0xFFUL << LTDC_LxDCCR_DCGREEN_Pos)
10321#define LTDC_LxDCCR_DCGREEN LTDC_LxDCCR_DCGREEN_Msk
10322#define LTDC_LxDCCR_DCRED_Pos (16U)
10323#define LTDC_LxDCCR_DCRED_Msk (0xFFUL << LTDC_LxDCCR_DCRED_Pos)
10324#define LTDC_LxDCCR_DCRED LTDC_LxDCCR_DCRED_Msk
10325#define LTDC_LxDCCR_DCALPHA_Pos (24U)
10326#define LTDC_LxDCCR_DCALPHA_Msk (0xFFUL << LTDC_LxDCCR_DCALPHA_Pos)
10327#define LTDC_LxDCCR_DCALPHA LTDC_LxDCCR_DCALPHA_Msk
10328
10329/******************** Bit definition for LTDC_LxBFCR register ***************/
10330
10331#define LTDC_LxBFCR_BF2_Pos (0U)
10332#define LTDC_LxBFCR_BF2_Msk (0x7UL << LTDC_LxBFCR_BF2_Pos)
10333#define LTDC_LxBFCR_BF2 LTDC_LxBFCR_BF2_Msk
10334#define LTDC_LxBFCR_BF1_Pos (8U)
10335#define LTDC_LxBFCR_BF1_Msk (0x7UL << LTDC_LxBFCR_BF1_Pos)
10336#define LTDC_LxBFCR_BF1 LTDC_LxBFCR_BF1_Msk
10337
10338/******************** Bit definition for LTDC_LxCFBAR register **************/
10339
10340#define LTDC_LxCFBAR_CFBADD_Pos (0U)
10341#define LTDC_LxCFBAR_CFBADD_Msk (0xFFFFFFFFUL << LTDC_LxCFBAR_CFBADD_Pos)
10342#define LTDC_LxCFBAR_CFBADD LTDC_LxCFBAR_CFBADD_Msk
10343
10344/******************** Bit definition for LTDC_LxCFBLR register **************/
10345
10346#define LTDC_LxCFBLR_CFBLL_Pos (0U)
10347#define LTDC_LxCFBLR_CFBLL_Msk (0x1FFFUL << LTDC_LxCFBLR_CFBLL_Pos)
10348#define LTDC_LxCFBLR_CFBLL LTDC_LxCFBLR_CFBLL_Msk
10349#define LTDC_LxCFBLR_CFBP_Pos (16U)
10350#define LTDC_LxCFBLR_CFBP_Msk (0x1FFFUL << LTDC_LxCFBLR_CFBP_Pos)
10351#define LTDC_LxCFBLR_CFBP LTDC_LxCFBLR_CFBP_Msk
10352
10353/******************** Bit definition for LTDC_LxCFBLNR register *************/
10354
10355#define LTDC_LxCFBLNR_CFBLNBR_Pos (0U)
10356#define LTDC_LxCFBLNR_CFBLNBR_Msk (0x7FFUL << LTDC_LxCFBLNR_CFBLNBR_Pos)
10357#define LTDC_LxCFBLNR_CFBLNBR LTDC_LxCFBLNR_CFBLNBR_Msk
10358
10359/******************** Bit definition for LTDC_LxCLUTWR register *************/
10360
10361#define LTDC_LxCLUTWR_BLUE_Pos (0U)
10362#define LTDC_LxCLUTWR_BLUE_Msk (0xFFUL << LTDC_LxCLUTWR_BLUE_Pos)
10363#define LTDC_LxCLUTWR_BLUE LTDC_LxCLUTWR_BLUE_Msk
10364#define LTDC_LxCLUTWR_GREEN_Pos (8U)
10365#define LTDC_LxCLUTWR_GREEN_Msk (0xFFUL << LTDC_LxCLUTWR_GREEN_Pos)
10366#define LTDC_LxCLUTWR_GREEN LTDC_LxCLUTWR_GREEN_Msk
10367#define LTDC_LxCLUTWR_RED_Pos (16U)
10368#define LTDC_LxCLUTWR_RED_Msk (0xFFUL << LTDC_LxCLUTWR_RED_Pos)
10369#define LTDC_LxCLUTWR_RED LTDC_LxCLUTWR_RED_Msk
10370#define LTDC_LxCLUTWR_CLUTADD_Pos (24U)
10371#define LTDC_LxCLUTWR_CLUTADD_Msk (0xFFUL << LTDC_LxCLUTWR_CLUTADD_Pos)
10372#define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk
10373
10374
10375/******************************************************************************/
10376/* */
10377/* Power Control */
10378/* */
10379/******************************************************************************/
10380/******************** Bit definition for PWR_CR register ********************/
10381#define PWR_CR_LPDS_Pos (0U)
10382#define PWR_CR_LPDS_Msk (0x1UL << PWR_CR_LPDS_Pos)
10383#define PWR_CR_LPDS PWR_CR_LPDS_Msk
10384#define PWR_CR_PDDS_Pos (1U)
10385#define PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos)
10386#define PWR_CR_PDDS PWR_CR_PDDS_Msk
10387#define PWR_CR_CWUF_Pos (2U)
10388#define PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos)
10389#define PWR_CR_CWUF PWR_CR_CWUF_Msk
10390#define PWR_CR_CSBF_Pos (3U)
10391#define PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos)
10392#define PWR_CR_CSBF PWR_CR_CSBF_Msk
10393#define PWR_CR_PVDE_Pos (4U)
10394#define PWR_CR_PVDE_Msk (0x1UL << PWR_CR_PVDE_Pos)
10395#define PWR_CR_PVDE PWR_CR_PVDE_Msk
10396
10397#define PWR_CR_PLS_Pos (5U)
10398#define PWR_CR_PLS_Msk (0x7UL << PWR_CR_PLS_Pos)
10399#define PWR_CR_PLS PWR_CR_PLS_Msk
10400#define PWR_CR_PLS_0 (0x1UL << PWR_CR_PLS_Pos)
10401#define PWR_CR_PLS_1 (0x2UL << PWR_CR_PLS_Pos)
10402#define PWR_CR_PLS_2 (0x4UL << PWR_CR_PLS_Pos)
10403
10405#define PWR_CR_PLS_LEV0 0x00000000U
10406#define PWR_CR_PLS_LEV1 0x00000020U
10407#define PWR_CR_PLS_LEV2 0x00000040U
10408#define PWR_CR_PLS_LEV3 0x00000060U
10409#define PWR_CR_PLS_LEV4 0x00000080U
10410#define PWR_CR_PLS_LEV5 0x000000A0U
10411#define PWR_CR_PLS_LEV6 0x000000C0U
10412#define PWR_CR_PLS_LEV7 0x000000E0U
10413#define PWR_CR_DBP_Pos (8U)
10414#define PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos)
10415#define PWR_CR_DBP PWR_CR_DBP_Msk
10416#define PWR_CR_FPDS_Pos (9U)
10417#define PWR_CR_FPDS_Msk (0x1UL << PWR_CR_FPDS_Pos)
10418#define PWR_CR_FPDS PWR_CR_FPDS_Msk
10419#define PWR_CR_LPLVDS_Pos (10U)
10420#define PWR_CR_LPLVDS_Msk (0x1UL << PWR_CR_LPLVDS_Pos)
10421#define PWR_CR_LPLVDS PWR_CR_LPLVDS_Msk
10422#define PWR_CR_MRLVDS_Pos (11U)
10423#define PWR_CR_MRLVDS_Msk (0x1UL << PWR_CR_MRLVDS_Pos)
10424#define PWR_CR_MRLVDS PWR_CR_MRLVDS_Msk
10425#define PWR_CR_ADCDC1_Pos (13U)
10426#define PWR_CR_ADCDC1_Msk (0x1UL << PWR_CR_ADCDC1_Pos)
10427#define PWR_CR_ADCDC1 PWR_CR_ADCDC1_Msk
10428#define PWR_CR_VOS_Pos (14U)
10429#define PWR_CR_VOS_Msk (0x3UL << PWR_CR_VOS_Pos)
10430#define PWR_CR_VOS PWR_CR_VOS_Msk
10431#define PWR_CR_VOS_0 0x00004000U
10432#define PWR_CR_VOS_1 0x00008000U
10433#define PWR_CR_ODEN_Pos (16U)
10434#define PWR_CR_ODEN_Msk (0x1UL << PWR_CR_ODEN_Pos)
10435#define PWR_CR_ODEN PWR_CR_ODEN_Msk
10436#define PWR_CR_ODSWEN_Pos (17U)
10437#define PWR_CR_ODSWEN_Msk (0x1UL << PWR_CR_ODSWEN_Pos)
10438#define PWR_CR_ODSWEN PWR_CR_ODSWEN_Msk
10439#define PWR_CR_UDEN_Pos (18U)
10440#define PWR_CR_UDEN_Msk (0x3UL << PWR_CR_UDEN_Pos)
10441#define PWR_CR_UDEN PWR_CR_UDEN_Msk
10442#define PWR_CR_UDEN_0 (0x1UL << PWR_CR_UDEN_Pos)
10443#define PWR_CR_UDEN_1 (0x2UL << PWR_CR_UDEN_Pos)
10444
10445/* Legacy define */
10446#define PWR_CR_PMODE PWR_CR_VOS
10447#define PWR_CR_LPUDS PWR_CR_LPLVDS
10448#define PWR_CR_MRUDS PWR_CR_MRLVDS
10449
10450/******************* Bit definition for PWR_CSR register ********************/
10451#define PWR_CSR_WUF_Pos (0U)
10452#define PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos)
10453#define PWR_CSR_WUF PWR_CSR_WUF_Msk
10454#define PWR_CSR_SBF_Pos (1U)
10455#define PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos)
10456#define PWR_CSR_SBF PWR_CSR_SBF_Msk
10457#define PWR_CSR_PVDO_Pos (2U)
10458#define PWR_CSR_PVDO_Msk (0x1UL << PWR_CSR_PVDO_Pos)
10459#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk
10460#define PWR_CSR_BRR_Pos (3U)
10461#define PWR_CSR_BRR_Msk (0x1UL << PWR_CSR_BRR_Pos)
10462#define PWR_CSR_BRR PWR_CSR_BRR_Msk
10463#define PWR_CSR_EWUP_Pos (8U)
10464#define PWR_CSR_EWUP_Msk (0x1UL << PWR_CSR_EWUP_Pos)
10465#define PWR_CSR_EWUP PWR_CSR_EWUP_Msk
10466#define PWR_CSR_BRE_Pos (9U)
10467#define PWR_CSR_BRE_Msk (0x1UL << PWR_CSR_BRE_Pos)
10468#define PWR_CSR_BRE PWR_CSR_BRE_Msk
10469#define PWR_CSR_VOSRDY_Pos (14U)
10470#define PWR_CSR_VOSRDY_Msk (0x1UL << PWR_CSR_VOSRDY_Pos)
10471#define PWR_CSR_VOSRDY PWR_CSR_VOSRDY_Msk
10472#define PWR_CSR_ODRDY_Pos (16U)
10473#define PWR_CSR_ODRDY_Msk (0x1UL << PWR_CSR_ODRDY_Pos)
10474#define PWR_CSR_ODRDY PWR_CSR_ODRDY_Msk
10475#define PWR_CSR_ODSWRDY_Pos (17U)
10476#define PWR_CSR_ODSWRDY_Msk (0x1UL << PWR_CSR_ODSWRDY_Pos)
10477#define PWR_CSR_ODSWRDY PWR_CSR_ODSWRDY_Msk
10478#define PWR_CSR_UDRDY_Pos (18U)
10479#define PWR_CSR_UDRDY_Msk (0x3UL << PWR_CSR_UDRDY_Pos)
10480#define PWR_CSR_UDRDY PWR_CSR_UDRDY_Msk
10481/* Legacy define */
10482#define PWR_CSR_UDSWRDY PWR_CSR_UDRDY
10483
10484/* Legacy define */
10485#define PWR_CSR_REGRDY PWR_CSR_VOSRDY
10486
10487/******************************************************************************/
10488/* */
10489/* Reset and Clock Control */
10490/* */
10491/******************************************************************************/
10492/******************** Bit definition for RCC_CR register ********************/
10493#define RCC_CR_HSION_Pos (0U)
10494#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos)
10495#define RCC_CR_HSION RCC_CR_HSION_Msk
10496#define RCC_CR_HSIRDY_Pos (1U)
10497#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos)
10498#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
10499
10500#define RCC_CR_HSITRIM_Pos (3U)
10501#define RCC_CR_HSITRIM_Msk (0x1FUL << RCC_CR_HSITRIM_Pos)
10502#define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
10503#define RCC_CR_HSITRIM_0 (0x01UL << RCC_CR_HSITRIM_Pos)
10504#define RCC_CR_HSITRIM_1 (0x02UL << RCC_CR_HSITRIM_Pos)
10505#define RCC_CR_HSITRIM_2 (0x04UL << RCC_CR_HSITRIM_Pos)
10506#define RCC_CR_HSITRIM_3 (0x08UL << RCC_CR_HSITRIM_Pos)
10507#define RCC_CR_HSITRIM_4 (0x10UL << RCC_CR_HSITRIM_Pos)
10508
10509#define RCC_CR_HSICAL_Pos (8U)
10510#define RCC_CR_HSICAL_Msk (0xFFUL << RCC_CR_HSICAL_Pos)
10511#define RCC_CR_HSICAL RCC_CR_HSICAL_Msk
10512#define RCC_CR_HSICAL_0 (0x01UL << RCC_CR_HSICAL_Pos)
10513#define RCC_CR_HSICAL_1 (0x02UL << RCC_CR_HSICAL_Pos)
10514#define RCC_CR_HSICAL_2 (0x04UL << RCC_CR_HSICAL_Pos)
10515#define RCC_CR_HSICAL_3 (0x08UL << RCC_CR_HSICAL_Pos)
10516#define RCC_CR_HSICAL_4 (0x10UL << RCC_CR_HSICAL_Pos)
10517#define RCC_CR_HSICAL_5 (0x20UL << RCC_CR_HSICAL_Pos)
10518#define RCC_CR_HSICAL_6 (0x40UL << RCC_CR_HSICAL_Pos)
10519#define RCC_CR_HSICAL_7 (0x80UL << RCC_CR_HSICAL_Pos)
10520
10521#define RCC_CR_HSEON_Pos (16U)
10522#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos)
10523#define RCC_CR_HSEON RCC_CR_HSEON_Msk
10524#define RCC_CR_HSERDY_Pos (17U)
10525#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos)
10526#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
10527#define RCC_CR_HSEBYP_Pos (18U)
10528#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos)
10529#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
10530#define RCC_CR_CSSON_Pos (19U)
10531#define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos)
10532#define RCC_CR_CSSON RCC_CR_CSSON_Msk
10533#define RCC_CR_PLLON_Pos (24U)
10534#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos)
10535#define RCC_CR_PLLON RCC_CR_PLLON_Msk
10536#define RCC_CR_PLLRDY_Pos (25U)
10537#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos)
10538#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
10539/*
10540 * @brief Specific device feature definitions (not present on all devices in the STM32F4 series)
10541 */
10542#define RCC_PLLI2S_SUPPORT
10543
10544#define RCC_CR_PLLI2SON_Pos (26U)
10545#define RCC_CR_PLLI2SON_Msk (0x1UL << RCC_CR_PLLI2SON_Pos)
10546#define RCC_CR_PLLI2SON RCC_CR_PLLI2SON_Msk
10547#define RCC_CR_PLLI2SRDY_Pos (27U)
10548#define RCC_CR_PLLI2SRDY_Msk (0x1UL << RCC_CR_PLLI2SRDY_Pos)
10549#define RCC_CR_PLLI2SRDY RCC_CR_PLLI2SRDY_Msk
10550/*
10551 * @brief Specific device feature definitions (not present on all devices in the STM32F4 series)
10552 */
10553#define RCC_PLLSAI_SUPPORT
10554
10555#define RCC_CR_PLLSAION_Pos (28U)
10556#define RCC_CR_PLLSAION_Msk (0x1UL << RCC_CR_PLLSAION_Pos)
10557#define RCC_CR_PLLSAION RCC_CR_PLLSAION_Msk
10558#define RCC_CR_PLLSAIRDY_Pos (29U)
10559#define RCC_CR_PLLSAIRDY_Msk (0x1UL << RCC_CR_PLLSAIRDY_Pos)
10560#define RCC_CR_PLLSAIRDY RCC_CR_PLLSAIRDY_Msk
10561
10562/******************** Bit definition for RCC_PLLCFGR register ***************/
10563#define RCC_PLLCFGR_PLLM_Pos (0U)
10564#define RCC_PLLCFGR_PLLM_Msk (0x3FUL << RCC_PLLCFGR_PLLM_Pos)
10565#define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
10566#define RCC_PLLCFGR_PLLM_0 (0x01UL << RCC_PLLCFGR_PLLM_Pos)
10567#define RCC_PLLCFGR_PLLM_1 (0x02UL << RCC_PLLCFGR_PLLM_Pos)
10568#define RCC_PLLCFGR_PLLM_2 (0x04UL << RCC_PLLCFGR_PLLM_Pos)
10569#define RCC_PLLCFGR_PLLM_3 (0x08UL << RCC_PLLCFGR_PLLM_Pos)
10570#define RCC_PLLCFGR_PLLM_4 (0x10UL << RCC_PLLCFGR_PLLM_Pos)
10571#define RCC_PLLCFGR_PLLM_5 (0x20UL << RCC_PLLCFGR_PLLM_Pos)
10572
10573#define RCC_PLLCFGR_PLLN_Pos (6U)
10574#define RCC_PLLCFGR_PLLN_Msk (0x1FFUL << RCC_PLLCFGR_PLLN_Pos)
10575#define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
10576#define RCC_PLLCFGR_PLLN_0 (0x001UL << RCC_PLLCFGR_PLLN_Pos)
10577#define RCC_PLLCFGR_PLLN_1 (0x002UL << RCC_PLLCFGR_PLLN_Pos)
10578#define RCC_PLLCFGR_PLLN_2 (0x004UL << RCC_PLLCFGR_PLLN_Pos)
10579#define RCC_PLLCFGR_PLLN_3 (0x008UL << RCC_PLLCFGR_PLLN_Pos)
10580#define RCC_PLLCFGR_PLLN_4 (0x010UL << RCC_PLLCFGR_PLLN_Pos)
10581#define RCC_PLLCFGR_PLLN_5 (0x020UL << RCC_PLLCFGR_PLLN_Pos)
10582#define RCC_PLLCFGR_PLLN_6 (0x040UL << RCC_PLLCFGR_PLLN_Pos)
10583#define RCC_PLLCFGR_PLLN_7 (0x080UL << RCC_PLLCFGR_PLLN_Pos)
10584#define RCC_PLLCFGR_PLLN_8 (0x100UL << RCC_PLLCFGR_PLLN_Pos)
10585
10586#define RCC_PLLCFGR_PLLP_Pos (16U)
10587#define RCC_PLLCFGR_PLLP_Msk (0x3UL << RCC_PLLCFGR_PLLP_Pos)
10588#define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
10589#define RCC_PLLCFGR_PLLP_0 (0x1UL << RCC_PLLCFGR_PLLP_Pos)
10590#define RCC_PLLCFGR_PLLP_1 (0x2UL << RCC_PLLCFGR_PLLP_Pos)
10591
10592#define RCC_PLLCFGR_PLLSRC_Pos (22U)
10593#define RCC_PLLCFGR_PLLSRC_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_Pos)
10594#define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
10595#define RCC_PLLCFGR_PLLSRC_HSE_Pos (22U)
10596#define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_HSE_Pos)
10597#define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk
10598#define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
10599
10600#define RCC_PLLCFGR_PLLQ_Pos (24U)
10601#define RCC_PLLCFGR_PLLQ_Msk (0xFUL << RCC_PLLCFGR_PLLQ_Pos)
10602#define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
10603#define RCC_PLLCFGR_PLLQ_0 (0x1UL << RCC_PLLCFGR_PLLQ_Pos)
10604#define RCC_PLLCFGR_PLLQ_1 (0x2UL << RCC_PLLCFGR_PLLQ_Pos)
10605#define RCC_PLLCFGR_PLLQ_2 (0x4UL << RCC_PLLCFGR_PLLQ_Pos)
10606#define RCC_PLLCFGR_PLLQ_3 (0x8UL << RCC_PLLCFGR_PLLQ_Pos)
10607
10608
10609/******************** Bit definition for RCC_CFGR register ******************/
10611#define RCC_CFGR_SW_Pos (0U)
10612#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos)
10613#define RCC_CFGR_SW RCC_CFGR_SW_Msk
10614#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos)
10615#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos)
10616
10617#define RCC_CFGR_SW_HSI 0x00000000U
10618#define RCC_CFGR_SW_HSE 0x00000001U
10619#define RCC_CFGR_SW_PLL 0x00000002U
10620
10622#define RCC_CFGR_SWS_Pos (2U)
10623#define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos)
10624#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk
10625#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos)
10626#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos)
10627
10628#define RCC_CFGR_SWS_HSI 0x00000000U
10629#define RCC_CFGR_SWS_HSE 0x00000004U
10630#define RCC_CFGR_SWS_PLL 0x00000008U
10631
10633#define RCC_CFGR_HPRE_Pos (4U)
10634#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos)
10635#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk
10636#define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos)
10637#define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos)
10638#define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos)
10639#define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos)
10640
10641#define RCC_CFGR_HPRE_DIV1 0x00000000U
10642#define RCC_CFGR_HPRE_DIV2 0x00000080U
10643#define RCC_CFGR_HPRE_DIV4 0x00000090U
10644#define RCC_CFGR_HPRE_DIV8 0x000000A0U
10645#define RCC_CFGR_HPRE_DIV16 0x000000B0U
10646#define RCC_CFGR_HPRE_DIV64 0x000000C0U
10647#define RCC_CFGR_HPRE_DIV128 0x000000D0U
10648#define RCC_CFGR_HPRE_DIV256 0x000000E0U
10649#define RCC_CFGR_HPRE_DIV512 0x000000F0U
10650
10652#define RCC_CFGR_PPRE1_Pos (10U)
10653#define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos)
10654#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk
10655#define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos)
10656#define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos)
10657#define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos)
10658
10659#define RCC_CFGR_PPRE1_DIV1 0x00000000U
10660#define RCC_CFGR_PPRE1_DIV2 0x00001000U
10661#define RCC_CFGR_PPRE1_DIV4 0x00001400U
10662#define RCC_CFGR_PPRE1_DIV8 0x00001800U
10663#define RCC_CFGR_PPRE1_DIV16 0x00001C00U
10664
10666#define RCC_CFGR_PPRE2_Pos (13U)
10667#define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos)
10668#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk
10669#define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos)
10670#define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos)
10671#define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos)
10672
10673#define RCC_CFGR_PPRE2_DIV1 0x00000000U
10674#define RCC_CFGR_PPRE2_DIV2 0x00008000U
10675#define RCC_CFGR_PPRE2_DIV4 0x0000A000U
10676#define RCC_CFGR_PPRE2_DIV8 0x0000C000U
10677#define RCC_CFGR_PPRE2_DIV16 0x0000E000U
10678
10680#define RCC_CFGR_RTCPRE_Pos (16U)
10681#define RCC_CFGR_RTCPRE_Msk (0x1FUL << RCC_CFGR_RTCPRE_Pos)
10682#define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk
10683#define RCC_CFGR_RTCPRE_0 (0x01UL << RCC_CFGR_RTCPRE_Pos)
10684#define RCC_CFGR_RTCPRE_1 (0x02UL << RCC_CFGR_RTCPRE_Pos)
10685#define RCC_CFGR_RTCPRE_2 (0x04UL << RCC_CFGR_RTCPRE_Pos)
10686#define RCC_CFGR_RTCPRE_3 (0x08UL << RCC_CFGR_RTCPRE_Pos)
10687#define RCC_CFGR_RTCPRE_4 (0x10UL << RCC_CFGR_RTCPRE_Pos)
10688
10690#define RCC_CFGR_MCO1_Pos (21U)
10691#define RCC_CFGR_MCO1_Msk (0x3UL << RCC_CFGR_MCO1_Pos)
10692#define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk
10693#define RCC_CFGR_MCO1_0 (0x1UL << RCC_CFGR_MCO1_Pos)
10694#define RCC_CFGR_MCO1_1 (0x2UL << RCC_CFGR_MCO1_Pos)
10695
10696#define RCC_CFGR_I2SSRC_Pos (23U)
10697#define RCC_CFGR_I2SSRC_Msk (0x1UL << RCC_CFGR_I2SSRC_Pos)
10698#define RCC_CFGR_I2SSRC RCC_CFGR_I2SSRC_Msk
10699
10700#define RCC_CFGR_MCO1PRE_Pos (24U)
10701#define RCC_CFGR_MCO1PRE_Msk (0x7UL << RCC_CFGR_MCO1PRE_Pos)
10702#define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk
10703#define RCC_CFGR_MCO1PRE_0 (0x1UL << RCC_CFGR_MCO1PRE_Pos)
10704#define RCC_CFGR_MCO1PRE_1 (0x2UL << RCC_CFGR_MCO1PRE_Pos)
10705#define RCC_CFGR_MCO1PRE_2 (0x4UL << RCC_CFGR_MCO1PRE_Pos)
10706
10707#define RCC_CFGR_MCO2PRE_Pos (27U)
10708#define RCC_CFGR_MCO2PRE_Msk (0x7UL << RCC_CFGR_MCO2PRE_Pos)
10709#define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk
10710#define RCC_CFGR_MCO2PRE_0 (0x1UL << RCC_CFGR_MCO2PRE_Pos)
10711#define RCC_CFGR_MCO2PRE_1 (0x2UL << RCC_CFGR_MCO2PRE_Pos)
10712#define RCC_CFGR_MCO2PRE_2 (0x4UL << RCC_CFGR_MCO2PRE_Pos)
10713
10714#define RCC_CFGR_MCO2_Pos (30U)
10715#define RCC_CFGR_MCO2_Msk (0x3UL << RCC_CFGR_MCO2_Pos)
10716#define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk
10717#define RCC_CFGR_MCO2_0 (0x1UL << RCC_CFGR_MCO2_Pos)
10718#define RCC_CFGR_MCO2_1 (0x2UL << RCC_CFGR_MCO2_Pos)
10719
10720/******************** Bit definition for RCC_CIR register *******************/
10721#define RCC_CIR_LSIRDYF_Pos (0U)
10722#define RCC_CIR_LSIRDYF_Msk (0x1UL << RCC_CIR_LSIRDYF_Pos)
10723#define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk
10724#define RCC_CIR_LSERDYF_Pos (1U)
10725#define RCC_CIR_LSERDYF_Msk (0x1UL << RCC_CIR_LSERDYF_Pos)
10726#define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk
10727#define RCC_CIR_HSIRDYF_Pos (2U)
10728#define RCC_CIR_HSIRDYF_Msk (0x1UL << RCC_CIR_HSIRDYF_Pos)
10729#define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk
10730#define RCC_CIR_HSERDYF_Pos (3U)
10731#define RCC_CIR_HSERDYF_Msk (0x1UL << RCC_CIR_HSERDYF_Pos)
10732#define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk
10733#define RCC_CIR_PLLRDYF_Pos (4U)
10734#define RCC_CIR_PLLRDYF_Msk (0x1UL << RCC_CIR_PLLRDYF_Pos)
10735#define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk
10736#define RCC_CIR_PLLI2SRDYF_Pos (5U)
10737#define RCC_CIR_PLLI2SRDYF_Msk (0x1UL << RCC_CIR_PLLI2SRDYF_Pos)
10738#define RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF_Msk
10739
10740#define RCC_CIR_PLLSAIRDYF_Pos (6U)
10741#define RCC_CIR_PLLSAIRDYF_Msk (0x1UL << RCC_CIR_PLLSAIRDYF_Pos)
10742#define RCC_CIR_PLLSAIRDYF RCC_CIR_PLLSAIRDYF_Msk
10743#define RCC_CIR_CSSF_Pos (7U)
10744#define RCC_CIR_CSSF_Msk (0x1UL << RCC_CIR_CSSF_Pos)
10745#define RCC_CIR_CSSF RCC_CIR_CSSF_Msk
10746#define RCC_CIR_LSIRDYIE_Pos (8U)
10747#define RCC_CIR_LSIRDYIE_Msk (0x1UL << RCC_CIR_LSIRDYIE_Pos)
10748#define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk
10749#define RCC_CIR_LSERDYIE_Pos (9U)
10750#define RCC_CIR_LSERDYIE_Msk (0x1UL << RCC_CIR_LSERDYIE_Pos)
10751#define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk
10752#define RCC_CIR_HSIRDYIE_Pos (10U)
10753#define RCC_CIR_HSIRDYIE_Msk (0x1UL << RCC_CIR_HSIRDYIE_Pos)
10754#define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk
10755#define RCC_CIR_HSERDYIE_Pos (11U)
10756#define RCC_CIR_HSERDYIE_Msk (0x1UL << RCC_CIR_HSERDYIE_Pos)
10757#define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk
10758#define RCC_CIR_PLLRDYIE_Pos (12U)
10759#define RCC_CIR_PLLRDYIE_Msk (0x1UL << RCC_CIR_PLLRDYIE_Pos)
10760#define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk
10761#define RCC_CIR_PLLI2SRDYIE_Pos (13U)
10762#define RCC_CIR_PLLI2SRDYIE_Msk (0x1UL << RCC_CIR_PLLI2SRDYIE_Pos)
10763#define RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE_Msk
10764
10765#define RCC_CIR_PLLSAIRDYIE_Pos (14U)
10766#define RCC_CIR_PLLSAIRDYIE_Msk (0x1UL << RCC_CIR_PLLSAIRDYIE_Pos)
10767#define RCC_CIR_PLLSAIRDYIE RCC_CIR_PLLSAIRDYIE_Msk
10768#define RCC_CIR_LSIRDYC_Pos (16U)
10769#define RCC_CIR_LSIRDYC_Msk (0x1UL << RCC_CIR_LSIRDYC_Pos)
10770#define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk
10771#define RCC_CIR_LSERDYC_Pos (17U)
10772#define RCC_CIR_LSERDYC_Msk (0x1UL << RCC_CIR_LSERDYC_Pos)
10773#define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk
10774#define RCC_CIR_HSIRDYC_Pos (18U)
10775#define RCC_CIR_HSIRDYC_Msk (0x1UL << RCC_CIR_HSIRDYC_Pos)
10776#define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk
10777#define RCC_CIR_HSERDYC_Pos (19U)
10778#define RCC_CIR_HSERDYC_Msk (0x1UL << RCC_CIR_HSERDYC_Pos)
10779#define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk
10780#define RCC_CIR_PLLRDYC_Pos (20U)
10781#define RCC_CIR_PLLRDYC_Msk (0x1UL << RCC_CIR_PLLRDYC_Pos)
10782#define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk
10783#define RCC_CIR_PLLI2SRDYC_Pos (21U)
10784#define RCC_CIR_PLLI2SRDYC_Msk (0x1UL << RCC_CIR_PLLI2SRDYC_Pos)
10785#define RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC_Msk
10786#define RCC_CIR_PLLSAIRDYC_Pos (22U)
10787#define RCC_CIR_PLLSAIRDYC_Msk (0x1UL << RCC_CIR_PLLSAIRDYC_Pos)
10788#define RCC_CIR_PLLSAIRDYC RCC_CIR_PLLSAIRDYC_Msk
10789
10790#define RCC_CIR_CSSC_Pos (23U)
10791#define RCC_CIR_CSSC_Msk (0x1UL << RCC_CIR_CSSC_Pos)
10792#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk
10793
10794/******************** Bit definition for RCC_AHB1RSTR register **************/
10795#define RCC_AHB1RSTR_GPIOARST_Pos (0U)
10796#define RCC_AHB1RSTR_GPIOARST_Msk (0x1UL << RCC_AHB1RSTR_GPIOARST_Pos)
10797#define RCC_AHB1RSTR_GPIOARST RCC_AHB1RSTR_GPIOARST_Msk
10798#define RCC_AHB1RSTR_GPIOBRST_Pos (1U)
10799#define RCC_AHB1RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOBRST_Pos)
10800#define RCC_AHB1RSTR_GPIOBRST RCC_AHB1RSTR_GPIOBRST_Msk
10801#define RCC_AHB1RSTR_GPIOCRST_Pos (2U)
10802#define RCC_AHB1RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOCRST_Pos)
10803#define RCC_AHB1RSTR_GPIOCRST RCC_AHB1RSTR_GPIOCRST_Msk
10804#define RCC_AHB1RSTR_GPIODRST_Pos (3U)
10805#define RCC_AHB1RSTR_GPIODRST_Msk (0x1UL << RCC_AHB1RSTR_GPIODRST_Pos)
10806#define RCC_AHB1RSTR_GPIODRST RCC_AHB1RSTR_GPIODRST_Msk
10807#define RCC_AHB1RSTR_GPIOERST_Pos (4U)
10808#define RCC_AHB1RSTR_GPIOERST_Msk (0x1UL << RCC_AHB1RSTR_GPIOERST_Pos)
10809#define RCC_AHB1RSTR_GPIOERST RCC_AHB1RSTR_GPIOERST_Msk
10810#define RCC_AHB1RSTR_GPIOFRST_Pos (5U)
10811#define RCC_AHB1RSTR_GPIOFRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOFRST_Pos)
10812#define RCC_AHB1RSTR_GPIOFRST RCC_AHB1RSTR_GPIOFRST_Msk
10813#define RCC_AHB1RSTR_GPIOGRST_Pos (6U)
10814#define RCC_AHB1RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOGRST_Pos)
10815#define RCC_AHB1RSTR_GPIOGRST RCC_AHB1RSTR_GPIOGRST_Msk
10816#define RCC_AHB1RSTR_GPIOHRST_Pos (7U)
10817#define RCC_AHB1RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOHRST_Pos)
10818#define RCC_AHB1RSTR_GPIOHRST RCC_AHB1RSTR_GPIOHRST_Msk
10819#define RCC_AHB1RSTR_GPIOIRST_Pos (8U)
10820#define RCC_AHB1RSTR_GPIOIRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOIRST_Pos)
10821#define RCC_AHB1RSTR_GPIOIRST RCC_AHB1RSTR_GPIOIRST_Msk
10822#define RCC_AHB1RSTR_GPIOJRST_Pos (9U)
10823#define RCC_AHB1RSTR_GPIOJRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOJRST_Pos)
10824#define RCC_AHB1RSTR_GPIOJRST RCC_AHB1RSTR_GPIOJRST_Msk
10825#define RCC_AHB1RSTR_GPIOKRST_Pos (10U)
10826#define RCC_AHB1RSTR_GPIOKRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOKRST_Pos)
10827#define RCC_AHB1RSTR_GPIOKRST RCC_AHB1RSTR_GPIOKRST_Msk
10828#define RCC_AHB1RSTR_CRCRST_Pos (12U)
10829#define RCC_AHB1RSTR_CRCRST_Msk (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)
10830#define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
10831#define RCC_AHB1RSTR_DMA1RST_Pos (21U)
10832#define RCC_AHB1RSTR_DMA1RST_Msk (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)
10833#define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
10834#define RCC_AHB1RSTR_DMA2RST_Pos (22U)
10835#define RCC_AHB1RSTR_DMA2RST_Msk (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)
10836#define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
10837#define RCC_AHB1RSTR_DMA2DRST_Pos (23U)
10838#define RCC_AHB1RSTR_DMA2DRST_Msk (0x1UL << RCC_AHB1RSTR_DMA2DRST_Pos)
10839#define RCC_AHB1RSTR_DMA2DRST RCC_AHB1RSTR_DMA2DRST_Msk
10840#define RCC_AHB1RSTR_ETHMACRST_Pos (25U)
10841#define RCC_AHB1RSTR_ETHMACRST_Msk (0x1UL << RCC_AHB1RSTR_ETHMACRST_Pos)
10842#define RCC_AHB1RSTR_ETHMACRST RCC_AHB1RSTR_ETHMACRST_Msk
10843#define RCC_AHB1RSTR_OTGHRST_Pos (29U)
10844#define RCC_AHB1RSTR_OTGHRST_Msk (0x1UL << RCC_AHB1RSTR_OTGHRST_Pos)
10845#define RCC_AHB1RSTR_OTGHRST RCC_AHB1RSTR_OTGHRST_Msk
10846
10847/******************** Bit definition for RCC_AHB2RSTR register **************/
10848#define RCC_AHB2RSTR_DCMIRST_Pos (0U)
10849#define RCC_AHB2RSTR_DCMIRST_Msk (0x1UL << RCC_AHB2RSTR_DCMIRST_Pos)
10850#define RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMIRST_Msk
10851#define RCC_AHB2RSTR_RNGRST_Pos (6U)
10852#define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)
10853#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
10854#define RCC_AHB2RSTR_OTGFSRST_Pos (7U)
10855#define RCC_AHB2RSTR_OTGFSRST_Msk (0x1UL << RCC_AHB2RSTR_OTGFSRST_Pos)
10856#define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk
10857/******************** Bit definition for RCC_AHB3RSTR register **************/
10858#define RCC_AHB3RSTR_FMCRST_Pos (0U)
10859#define RCC_AHB3RSTR_FMCRST_Msk (0x1UL << RCC_AHB3RSTR_FMCRST_Pos)
10860#define RCC_AHB3RSTR_FMCRST RCC_AHB3RSTR_FMCRST_Msk
10861
10862
10863/******************** Bit definition for RCC_APB1RSTR register **************/
10864#define RCC_APB1RSTR_TIM2RST_Pos (0U)
10865#define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos)
10866#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk
10867#define RCC_APB1RSTR_TIM3RST_Pos (1U)
10868#define RCC_APB1RSTR_TIM3RST_Msk (0x1UL << RCC_APB1RSTR_TIM3RST_Pos)
10869#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk
10870#define RCC_APB1RSTR_TIM4RST_Pos (2U)
10871#define RCC_APB1RSTR_TIM4RST_Msk (0x1UL << RCC_APB1RSTR_TIM4RST_Pos)
10872#define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk
10873#define RCC_APB1RSTR_TIM5RST_Pos (3U)
10874#define RCC_APB1RSTR_TIM5RST_Msk (0x1UL << RCC_APB1RSTR_TIM5RST_Pos)
10875#define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk
10876#define RCC_APB1RSTR_TIM6RST_Pos (4U)
10877#define RCC_APB1RSTR_TIM6RST_Msk (0x1UL << RCC_APB1RSTR_TIM6RST_Pos)
10878#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk
10879#define RCC_APB1RSTR_TIM7RST_Pos (5U)
10880#define RCC_APB1RSTR_TIM7RST_Msk (0x1UL << RCC_APB1RSTR_TIM7RST_Pos)
10881#define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk
10882#define RCC_APB1RSTR_TIM12RST_Pos (6U)
10883#define RCC_APB1RSTR_TIM12RST_Msk (0x1UL << RCC_APB1RSTR_TIM12RST_Pos)
10884#define RCC_APB1RSTR_TIM12RST RCC_APB1RSTR_TIM12RST_Msk
10885#define RCC_APB1RSTR_TIM13RST_Pos (7U)
10886#define RCC_APB1RSTR_TIM13RST_Msk (0x1UL << RCC_APB1RSTR_TIM13RST_Pos)
10887#define RCC_APB1RSTR_TIM13RST RCC_APB1RSTR_TIM13RST_Msk
10888#define RCC_APB1RSTR_TIM14RST_Pos (8U)
10889#define RCC_APB1RSTR_TIM14RST_Msk (0x1UL << RCC_APB1RSTR_TIM14RST_Pos)
10890#define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk
10891#define RCC_APB1RSTR_WWDGRST_Pos (11U)
10892#define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos)
10893#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk
10894#define RCC_APB1RSTR_SPI2RST_Pos (14U)
10895#define RCC_APB1RSTR_SPI2RST_Msk (0x1UL << RCC_APB1RSTR_SPI2RST_Pos)
10896#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk
10897#define RCC_APB1RSTR_SPI3RST_Pos (15U)
10898#define RCC_APB1RSTR_SPI3RST_Msk (0x1UL << RCC_APB1RSTR_SPI3RST_Pos)
10899#define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk
10900#define RCC_APB1RSTR_USART2RST_Pos (17U)
10901#define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos)
10902#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk
10903#define RCC_APB1RSTR_USART3RST_Pos (18U)
10904#define RCC_APB1RSTR_USART3RST_Msk (0x1UL << RCC_APB1RSTR_USART3RST_Pos)
10905#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk
10906#define RCC_APB1RSTR_UART4RST_Pos (19U)
10907#define RCC_APB1RSTR_UART4RST_Msk (0x1UL << RCC_APB1RSTR_UART4RST_Pos)
10908#define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk
10909#define RCC_APB1RSTR_UART5RST_Pos (20U)
10910#define RCC_APB1RSTR_UART5RST_Msk (0x1UL << RCC_APB1RSTR_UART5RST_Pos)
10911#define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk
10912#define RCC_APB1RSTR_I2C1RST_Pos (21U)
10913#define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos)
10914#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk
10915#define RCC_APB1RSTR_I2C2RST_Pos (22U)
10916#define RCC_APB1RSTR_I2C2RST_Msk (0x1UL << RCC_APB1RSTR_I2C2RST_Pos)
10917#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk
10918#define RCC_APB1RSTR_I2C3RST_Pos (23U)
10919#define RCC_APB1RSTR_I2C3RST_Msk (0x1UL << RCC_APB1RSTR_I2C3RST_Pos)
10920#define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk
10921#define RCC_APB1RSTR_CAN1RST_Pos (25U)
10922#define RCC_APB1RSTR_CAN1RST_Msk (0x1UL << RCC_APB1RSTR_CAN1RST_Pos)
10923#define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk
10924#define RCC_APB1RSTR_CAN2RST_Pos (26U)
10925#define RCC_APB1RSTR_CAN2RST_Msk (0x1UL << RCC_APB1RSTR_CAN2RST_Pos)
10926#define RCC_APB1RSTR_CAN2RST RCC_APB1RSTR_CAN2RST_Msk
10927#define RCC_APB1RSTR_PWRRST_Pos (28U)
10928#define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos)
10929#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk
10930#define RCC_APB1RSTR_DACRST_Pos (29U)
10931#define RCC_APB1RSTR_DACRST_Msk (0x1UL << RCC_APB1RSTR_DACRST_Pos)
10932#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk
10933#define RCC_APB1RSTR_UART7RST_Pos (30U)
10934#define RCC_APB1RSTR_UART7RST_Msk (0x1UL << RCC_APB1RSTR_UART7RST_Pos)
10935#define RCC_APB1RSTR_UART7RST RCC_APB1RSTR_UART7RST_Msk
10936#define RCC_APB1RSTR_UART8RST_Pos (31U)
10937#define RCC_APB1RSTR_UART8RST_Msk (0x1UL << RCC_APB1RSTR_UART8RST_Pos)
10938#define RCC_APB1RSTR_UART8RST RCC_APB1RSTR_UART8RST_Msk
10939
10940/******************** Bit definition for RCC_APB2RSTR register **************/
10941#define RCC_APB2RSTR_TIM1RST_Pos (0U)
10942#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)
10943#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
10944#define RCC_APB2RSTR_TIM8RST_Pos (1U)
10945#define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)
10946#define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
10947#define RCC_APB2RSTR_USART1RST_Pos (4U)
10948#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos)
10949#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
10950#define RCC_APB2RSTR_USART6RST_Pos (5U)
10951#define RCC_APB2RSTR_USART6RST_Msk (0x1UL << RCC_APB2RSTR_USART6RST_Pos)
10952#define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
10953#define RCC_APB2RSTR_ADCRST_Pos (8U)
10954#define RCC_APB2RSTR_ADCRST_Msk (0x1UL << RCC_APB2RSTR_ADCRST_Pos)
10955#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk
10956#define RCC_APB2RSTR_SDIORST_Pos (11U)
10957#define RCC_APB2RSTR_SDIORST_Msk (0x1UL << RCC_APB2RSTR_SDIORST_Pos)
10958#define RCC_APB2RSTR_SDIORST RCC_APB2RSTR_SDIORST_Msk
10959#define RCC_APB2RSTR_SPI1RST_Pos (12U)
10960#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)
10961#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
10962#define RCC_APB2RSTR_SPI4RST_Pos (13U)
10963#define RCC_APB2RSTR_SPI4RST_Msk (0x1UL << RCC_APB2RSTR_SPI4RST_Pos)
10964#define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk
10965#define RCC_APB2RSTR_SYSCFGRST_Pos (14U)
10966#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos)
10967#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
10968#define RCC_APB2RSTR_TIM9RST_Pos (16U)
10969#define RCC_APB2RSTR_TIM9RST_Msk (0x1UL << RCC_APB2RSTR_TIM9RST_Pos)
10970#define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk
10971#define RCC_APB2RSTR_TIM10RST_Pos (17U)
10972#define RCC_APB2RSTR_TIM10RST_Msk (0x1UL << RCC_APB2RSTR_TIM10RST_Pos)
10973#define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk
10974#define RCC_APB2RSTR_TIM11RST_Pos (18U)
10975#define RCC_APB2RSTR_TIM11RST_Msk (0x1UL << RCC_APB2RSTR_TIM11RST_Pos)
10976#define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk
10977#define RCC_APB2RSTR_SPI5RST_Pos (20U)
10978#define RCC_APB2RSTR_SPI5RST_Msk (0x1UL << RCC_APB2RSTR_SPI5RST_Pos)
10979#define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk
10980#define RCC_APB2RSTR_SPI6RST_Pos (21U)
10981#define RCC_APB2RSTR_SPI6RST_Msk (0x1UL << RCC_APB2RSTR_SPI6RST_Pos)
10982#define RCC_APB2RSTR_SPI6RST RCC_APB2RSTR_SPI6RST_Msk
10983#define RCC_APB2RSTR_SAI1RST_Pos (22U)
10984#define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos)
10985#define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
10986#define RCC_APB2RSTR_LTDCRST_Pos (26U)
10987#define RCC_APB2RSTR_LTDCRST_Msk (0x1UL << RCC_APB2RSTR_LTDCRST_Pos)
10988#define RCC_APB2RSTR_LTDCRST RCC_APB2RSTR_LTDCRST_Msk
10989
10990/* Old SPI1RST bit definition, maintained for legacy purpose */
10991#define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
10992
10993/******************** Bit definition for RCC_AHB1ENR register ***************/
10994#define RCC_AHB1ENR_GPIOAEN_Pos (0U)
10995#define RCC_AHB1ENR_GPIOAEN_Msk (0x1UL << RCC_AHB1ENR_GPIOAEN_Pos)
10996#define RCC_AHB1ENR_GPIOAEN RCC_AHB1ENR_GPIOAEN_Msk
10997#define RCC_AHB1ENR_GPIOBEN_Pos (1U)
10998#define RCC_AHB1ENR_GPIOBEN_Msk (0x1UL << RCC_AHB1ENR_GPIOBEN_Pos)
10999#define RCC_AHB1ENR_GPIOBEN RCC_AHB1ENR_GPIOBEN_Msk
11000#define RCC_AHB1ENR_GPIOCEN_Pos (2U)
11001#define RCC_AHB1ENR_GPIOCEN_Msk (0x1UL << RCC_AHB1ENR_GPIOCEN_Pos)
11002#define RCC_AHB1ENR_GPIOCEN RCC_AHB1ENR_GPIOCEN_Msk
11003#define RCC_AHB1ENR_GPIODEN_Pos (3U)
11004#define RCC_AHB1ENR_GPIODEN_Msk (0x1UL << RCC_AHB1ENR_GPIODEN_Pos)
11005#define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk
11006#define RCC_AHB1ENR_GPIOEEN_Pos (4U)
11007#define RCC_AHB1ENR_GPIOEEN_Msk (0x1UL << RCC_AHB1ENR_GPIOEEN_Pos)
11008#define RCC_AHB1ENR_GPIOEEN RCC_AHB1ENR_GPIOEEN_Msk
11009#define RCC_AHB1ENR_GPIOFEN_Pos (5U)
11010#define RCC_AHB1ENR_GPIOFEN_Msk (0x1UL << RCC_AHB1ENR_GPIOFEN_Pos)
11011#define RCC_AHB1ENR_GPIOFEN RCC_AHB1ENR_GPIOFEN_Msk
11012#define RCC_AHB1ENR_GPIOGEN_Pos (6U)
11013#define RCC_AHB1ENR_GPIOGEN_Msk (0x1UL << RCC_AHB1ENR_GPIOGEN_Pos)
11014#define RCC_AHB1ENR_GPIOGEN RCC_AHB1ENR_GPIOGEN_Msk
11015#define RCC_AHB1ENR_GPIOHEN_Pos (7U)
11016#define RCC_AHB1ENR_GPIOHEN_Msk (0x1UL << RCC_AHB1ENR_GPIOHEN_Pos)
11017#define RCC_AHB1ENR_GPIOHEN RCC_AHB1ENR_GPIOHEN_Msk
11018#define RCC_AHB1ENR_GPIOIEN_Pos (8U)
11019#define RCC_AHB1ENR_GPIOIEN_Msk (0x1UL << RCC_AHB1ENR_GPIOIEN_Pos)
11020#define RCC_AHB1ENR_GPIOIEN RCC_AHB1ENR_GPIOIEN_Msk
11021#define RCC_AHB1ENR_GPIOJEN_Pos (9U)
11022#define RCC_AHB1ENR_GPIOJEN_Msk (0x1UL << RCC_AHB1ENR_GPIOJEN_Pos)
11023#define RCC_AHB1ENR_GPIOJEN RCC_AHB1ENR_GPIOJEN_Msk
11024#define RCC_AHB1ENR_GPIOKEN_Pos (10U)
11025#define RCC_AHB1ENR_GPIOKEN_Msk (0x1UL << RCC_AHB1ENR_GPIOKEN_Pos)
11026#define RCC_AHB1ENR_GPIOKEN RCC_AHB1ENR_GPIOKEN_Msk
11027#define RCC_AHB1ENR_CRCEN_Pos (12U)
11028#define RCC_AHB1ENR_CRCEN_Msk (0x1UL << RCC_AHB1ENR_CRCEN_Pos)
11029#define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
11030#define RCC_AHB1ENR_BKPSRAMEN_Pos (18U)
11031#define RCC_AHB1ENR_BKPSRAMEN_Msk (0x1UL << RCC_AHB1ENR_BKPSRAMEN_Pos)
11032#define RCC_AHB1ENR_BKPSRAMEN RCC_AHB1ENR_BKPSRAMEN_Msk
11033#define RCC_AHB1ENR_CCMDATARAMEN_Pos (20U)
11034#define RCC_AHB1ENR_CCMDATARAMEN_Msk (0x1UL << RCC_AHB1ENR_CCMDATARAMEN_Pos)
11035#define RCC_AHB1ENR_CCMDATARAMEN RCC_AHB1ENR_CCMDATARAMEN_Msk
11036#define RCC_AHB1ENR_DMA1EN_Pos (21U)
11037#define RCC_AHB1ENR_DMA1EN_Msk (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)
11038#define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
11039#define RCC_AHB1ENR_DMA2EN_Pos (22U)
11040#define RCC_AHB1ENR_DMA2EN_Msk (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)
11041#define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
11042#define RCC_AHB1ENR_DMA2DEN_Pos (23U)
11043#define RCC_AHB1ENR_DMA2DEN_Msk (0x1UL << RCC_AHB1ENR_DMA2DEN_Pos)
11044#define RCC_AHB1ENR_DMA2DEN RCC_AHB1ENR_DMA2DEN_Msk
11045#define RCC_AHB1ENR_ETHMACEN_Pos (25U)
11046#define RCC_AHB1ENR_ETHMACEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACEN_Pos)
11047#define RCC_AHB1ENR_ETHMACEN RCC_AHB1ENR_ETHMACEN_Msk
11048#define RCC_AHB1ENR_ETHMACTXEN_Pos (26U)
11049#define RCC_AHB1ENR_ETHMACTXEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACTXEN_Pos)
11050#define RCC_AHB1ENR_ETHMACTXEN RCC_AHB1ENR_ETHMACTXEN_Msk
11051#define RCC_AHB1ENR_ETHMACRXEN_Pos (27U)
11052#define RCC_AHB1ENR_ETHMACRXEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACRXEN_Pos)
11053#define RCC_AHB1ENR_ETHMACRXEN RCC_AHB1ENR_ETHMACRXEN_Msk
11054#define RCC_AHB1ENR_ETHMACPTPEN_Pos (28U)
11055#define RCC_AHB1ENR_ETHMACPTPEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACPTPEN_Pos)
11056#define RCC_AHB1ENR_ETHMACPTPEN RCC_AHB1ENR_ETHMACPTPEN_Msk
11057#define RCC_AHB1ENR_OTGHSEN_Pos (29U)
11058#define RCC_AHB1ENR_OTGHSEN_Msk (0x1UL << RCC_AHB1ENR_OTGHSEN_Pos)
11059#define RCC_AHB1ENR_OTGHSEN RCC_AHB1ENR_OTGHSEN_Msk
11060#define RCC_AHB1ENR_OTGHSULPIEN_Pos (30U)
11061#define RCC_AHB1ENR_OTGHSULPIEN_Msk (0x1UL << RCC_AHB1ENR_OTGHSULPIEN_Pos)
11062#define RCC_AHB1ENR_OTGHSULPIEN RCC_AHB1ENR_OTGHSULPIEN_Msk
11063/******************** Bit definition for RCC_AHB2ENR register ***************/
11064/*
11065 * @brief Specific device feature definitions (not present on all devices in the STM32F4 series)
11066 */
11067#define RCC_AHB2_SUPPORT
11068
11069#define RCC_AHB2ENR_DCMIEN_Pos (0U)
11070#define RCC_AHB2ENR_DCMIEN_Msk (0x1UL << RCC_AHB2ENR_DCMIEN_Pos)
11071#define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMIEN_Msk
11072#define RCC_AHB2ENR_RNGEN_Pos (6U)
11073#define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos)
11074#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
11075#define RCC_AHB2ENR_OTGFSEN_Pos (7U)
11076#define RCC_AHB2ENR_OTGFSEN_Msk (0x1UL << RCC_AHB2ENR_OTGFSEN_Pos)
11077#define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk
11078
11079/******************** Bit definition for RCC_AHB3ENR register ***************/
11080/*
11081 * @brief Specific device feature definitions (not present on all devices in the STM32F4 series)
11082 */
11083#define RCC_AHB3_SUPPORT
11084
11085#define RCC_AHB3ENR_FMCEN_Pos (0U)
11086#define RCC_AHB3ENR_FMCEN_Msk (0x1UL << RCC_AHB3ENR_FMCEN_Pos)
11087#define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk
11088
11089/******************** Bit definition for RCC_APB1ENR register ***************/
11090#define RCC_APB1ENR_TIM2EN_Pos (0U)
11091#define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos)
11092#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk
11093#define RCC_APB1ENR_TIM3EN_Pos (1U)
11094#define RCC_APB1ENR_TIM3EN_Msk (0x1UL << RCC_APB1ENR_TIM3EN_Pos)
11095#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk
11096#define RCC_APB1ENR_TIM4EN_Pos (2U)
11097#define RCC_APB1ENR_TIM4EN_Msk (0x1UL << RCC_APB1ENR_TIM4EN_Pos)
11098#define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk
11099#define RCC_APB1ENR_TIM5EN_Pos (3U)
11100#define RCC_APB1ENR_TIM5EN_Msk (0x1UL << RCC_APB1ENR_TIM5EN_Pos)
11101#define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk
11102#define RCC_APB1ENR_TIM6EN_Pos (4U)
11103#define RCC_APB1ENR_TIM6EN_Msk (0x1UL << RCC_APB1ENR_TIM6EN_Pos)
11104#define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk
11105#define RCC_APB1ENR_TIM7EN_Pos (5U)
11106#define RCC_APB1ENR_TIM7EN_Msk (0x1UL << RCC_APB1ENR_TIM7EN_Pos)
11107#define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk
11108#define RCC_APB1ENR_TIM12EN_Pos (6U)
11109#define RCC_APB1ENR_TIM12EN_Msk (0x1UL << RCC_APB1ENR_TIM12EN_Pos)
11110#define RCC_APB1ENR_TIM12EN RCC_APB1ENR_TIM12EN_Msk
11111#define RCC_APB1ENR_TIM13EN_Pos (7U)
11112#define RCC_APB1ENR_TIM13EN_Msk (0x1UL << RCC_APB1ENR_TIM13EN_Pos)
11113#define RCC_APB1ENR_TIM13EN RCC_APB1ENR_TIM13EN_Msk
11114#define RCC_APB1ENR_TIM14EN_Pos (8U)
11115#define RCC_APB1ENR_TIM14EN_Msk (0x1UL << RCC_APB1ENR_TIM14EN_Pos)
11116#define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk
11117#define RCC_APB1ENR_WWDGEN_Pos (11U)
11118#define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos)
11119#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk
11120#define RCC_APB1ENR_SPI2EN_Pos (14U)
11121#define RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos)
11122#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk
11123#define RCC_APB1ENR_SPI3EN_Pos (15U)
11124#define RCC_APB1ENR_SPI3EN_Msk (0x1UL << RCC_APB1ENR_SPI3EN_Pos)
11125#define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk
11126#define RCC_APB1ENR_USART2EN_Pos (17U)
11127#define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos)
11128#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk
11129#define RCC_APB1ENR_USART3EN_Pos (18U)
11130#define RCC_APB1ENR_USART3EN_Msk (0x1UL << RCC_APB1ENR_USART3EN_Pos)
11131#define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk
11132#define RCC_APB1ENR_UART4EN_Pos (19U)
11133#define RCC_APB1ENR_UART4EN_Msk (0x1UL << RCC_APB1ENR_UART4EN_Pos)
11134#define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk
11135#define RCC_APB1ENR_UART5EN_Pos (20U)
11136#define RCC_APB1ENR_UART5EN_Msk (0x1UL << RCC_APB1ENR_UART5EN_Pos)
11137#define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk
11138#define RCC_APB1ENR_I2C1EN_Pos (21U)
11139#define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos)
11140#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk
11141#define RCC_APB1ENR_I2C2EN_Pos (22U)
11142#define RCC_APB1ENR_I2C2EN_Msk (0x1UL << RCC_APB1ENR_I2C2EN_Pos)
11143#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk
11144#define RCC_APB1ENR_I2C3EN_Pos (23U)
11145#define RCC_APB1ENR_I2C3EN_Msk (0x1UL << RCC_APB1ENR_I2C3EN_Pos)
11146#define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk
11147#define RCC_APB1ENR_CAN1EN_Pos (25U)
11148#define RCC_APB1ENR_CAN1EN_Msk (0x1UL << RCC_APB1ENR_CAN1EN_Pos)
11149#define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk
11150#define RCC_APB1ENR_CAN2EN_Pos (26U)
11151#define RCC_APB1ENR_CAN2EN_Msk (0x1UL << RCC_APB1ENR_CAN2EN_Pos)
11152#define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk
11153#define RCC_APB1ENR_PWREN_Pos (28U)
11154#define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos)
11155#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk
11156#define RCC_APB1ENR_DACEN_Pos (29U)
11157#define RCC_APB1ENR_DACEN_Msk (0x1UL << RCC_APB1ENR_DACEN_Pos)
11158#define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk
11159#define RCC_APB1ENR_UART7EN_Pos (30U)
11160#define RCC_APB1ENR_UART7EN_Msk (0x1UL << RCC_APB1ENR_UART7EN_Pos)
11161#define RCC_APB1ENR_UART7EN RCC_APB1ENR_UART7EN_Msk
11162#define RCC_APB1ENR_UART8EN_Pos (31U)
11163#define RCC_APB1ENR_UART8EN_Msk (0x1UL << RCC_APB1ENR_UART8EN_Pos)
11164#define RCC_APB1ENR_UART8EN RCC_APB1ENR_UART8EN_Msk
11165
11166/******************** Bit definition for RCC_APB2ENR register ***************/
11167#define RCC_APB2ENR_TIM1EN_Pos (0U)
11168#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos)
11169#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
11170#define RCC_APB2ENR_TIM8EN_Pos (1U)
11171#define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos)
11172#define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
11173#define RCC_APB2ENR_USART1EN_Pos (4U)
11174#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos)
11175#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
11176#define RCC_APB2ENR_USART6EN_Pos (5U)
11177#define RCC_APB2ENR_USART6EN_Msk (0x1UL << RCC_APB2ENR_USART6EN_Pos)
11178#define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
11179#define RCC_APB2ENR_ADC1EN_Pos (8U)
11180#define RCC_APB2ENR_ADC1EN_Msk (0x1UL << RCC_APB2ENR_ADC1EN_Pos)
11181#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk
11182#define RCC_APB2ENR_ADC2EN_Pos (9U)
11183#define RCC_APB2ENR_ADC2EN_Msk (0x1UL << RCC_APB2ENR_ADC2EN_Pos)
11184#define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk
11185#define RCC_APB2ENR_ADC3EN_Pos (10U)
11186#define RCC_APB2ENR_ADC3EN_Msk (0x1UL << RCC_APB2ENR_ADC3EN_Pos)
11187#define RCC_APB2ENR_ADC3EN RCC_APB2ENR_ADC3EN_Msk
11188#define RCC_APB2ENR_SDIOEN_Pos (11U)
11189#define RCC_APB2ENR_SDIOEN_Msk (0x1UL << RCC_APB2ENR_SDIOEN_Pos)
11190#define RCC_APB2ENR_SDIOEN RCC_APB2ENR_SDIOEN_Msk
11191#define RCC_APB2ENR_SPI1EN_Pos (12U)
11192#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos)
11193#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
11194#define RCC_APB2ENR_SPI4EN_Pos (13U)
11195#define RCC_APB2ENR_SPI4EN_Msk (0x1UL << RCC_APB2ENR_SPI4EN_Pos)
11196#define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk
11197#define RCC_APB2ENR_SYSCFGEN_Pos (14U)
11198#define RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)
11199#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
11200#define RCC_APB2ENR_TIM9EN_Pos (16U)
11201#define RCC_APB2ENR_TIM9EN_Msk (0x1UL << RCC_APB2ENR_TIM9EN_Pos)
11202#define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk
11203#define RCC_APB2ENR_TIM10EN_Pos (17U)
11204#define RCC_APB2ENR_TIM10EN_Msk (0x1UL << RCC_APB2ENR_TIM10EN_Pos)
11205#define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk
11206#define RCC_APB2ENR_TIM11EN_Pos (18U)
11207#define RCC_APB2ENR_TIM11EN_Msk (0x1UL << RCC_APB2ENR_TIM11EN_Pos)
11208#define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk
11209#define RCC_APB2ENR_SPI5EN_Pos (20U)
11210#define RCC_APB2ENR_SPI5EN_Msk (0x1UL << RCC_APB2ENR_SPI5EN_Pos)
11211#define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk
11212#define RCC_APB2ENR_SPI6EN_Pos (21U)
11213#define RCC_APB2ENR_SPI6EN_Msk (0x1UL << RCC_APB2ENR_SPI6EN_Pos)
11214#define RCC_APB2ENR_SPI6EN RCC_APB2ENR_SPI6EN_Msk
11215#define RCC_APB2ENR_SAI1EN_Pos (22U)
11216#define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos)
11217#define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
11218#define RCC_APB2ENR_LTDCEN_Pos (26U)
11219#define RCC_APB2ENR_LTDCEN_Msk (0x1UL << RCC_APB2ENR_LTDCEN_Pos)
11220#define RCC_APB2ENR_LTDCEN RCC_APB2ENR_LTDCEN_Msk
11221
11222/******************** Bit definition for RCC_AHB1LPENR register *************/
11223#define RCC_AHB1LPENR_GPIOALPEN_Pos (0U)
11224#define RCC_AHB1LPENR_GPIOALPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOALPEN_Pos)
11225#define RCC_AHB1LPENR_GPIOALPEN RCC_AHB1LPENR_GPIOALPEN_Msk
11226#define RCC_AHB1LPENR_GPIOBLPEN_Pos (1U)
11227#define RCC_AHB1LPENR_GPIOBLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOBLPEN_Pos)
11228#define RCC_AHB1LPENR_GPIOBLPEN RCC_AHB1LPENR_GPIOBLPEN_Msk
11229#define RCC_AHB1LPENR_GPIOCLPEN_Pos (2U)
11230#define RCC_AHB1LPENR_GPIOCLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOCLPEN_Pos)
11231#define RCC_AHB1LPENR_GPIOCLPEN RCC_AHB1LPENR_GPIOCLPEN_Msk
11232#define RCC_AHB1LPENR_GPIODLPEN_Pos (3U)
11233#define RCC_AHB1LPENR_GPIODLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIODLPEN_Pos)
11234#define RCC_AHB1LPENR_GPIODLPEN RCC_AHB1LPENR_GPIODLPEN_Msk
11235#define RCC_AHB1LPENR_GPIOELPEN_Pos (4U)
11236#define RCC_AHB1LPENR_GPIOELPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOELPEN_Pos)
11237#define RCC_AHB1LPENR_GPIOELPEN RCC_AHB1LPENR_GPIOELPEN_Msk
11238#define RCC_AHB1LPENR_GPIOFLPEN_Pos (5U)
11239#define RCC_AHB1LPENR_GPIOFLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOFLPEN_Pos)
11240#define RCC_AHB1LPENR_GPIOFLPEN RCC_AHB1LPENR_GPIOFLPEN_Msk
11241#define RCC_AHB1LPENR_GPIOGLPEN_Pos (6U)
11242#define RCC_AHB1LPENR_GPIOGLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOGLPEN_Pos)
11243#define RCC_AHB1LPENR_GPIOGLPEN RCC_AHB1LPENR_GPIOGLPEN_Msk
11244#define RCC_AHB1LPENR_GPIOHLPEN_Pos (7U)
11245#define RCC_AHB1LPENR_GPIOHLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOHLPEN_Pos)
11246#define RCC_AHB1LPENR_GPIOHLPEN RCC_AHB1LPENR_GPIOHLPEN_Msk
11247#define RCC_AHB1LPENR_GPIOILPEN_Pos (8U)
11248#define RCC_AHB1LPENR_GPIOILPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOILPEN_Pos)
11249#define RCC_AHB1LPENR_GPIOILPEN RCC_AHB1LPENR_GPIOILPEN_Msk
11250#define RCC_AHB1LPENR_GPIOJLPEN_Pos (9U)
11251#define RCC_AHB1LPENR_GPIOJLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOJLPEN_Pos)
11252#define RCC_AHB1LPENR_GPIOJLPEN RCC_AHB1LPENR_GPIOJLPEN_Msk
11253#define RCC_AHB1LPENR_GPIOKLPEN_Pos (10U)
11254#define RCC_AHB1LPENR_GPIOKLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOKLPEN_Pos)
11255#define RCC_AHB1LPENR_GPIOKLPEN RCC_AHB1LPENR_GPIOKLPEN_Msk
11256#define RCC_AHB1LPENR_CRCLPEN_Pos (12U)
11257#define RCC_AHB1LPENR_CRCLPEN_Msk (0x1UL << RCC_AHB1LPENR_CRCLPEN_Pos)
11258#define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk
11259#define RCC_AHB1LPENR_FLITFLPEN_Pos (15U)
11260#define RCC_AHB1LPENR_FLITFLPEN_Msk (0x1UL << RCC_AHB1LPENR_FLITFLPEN_Pos)
11261#define RCC_AHB1LPENR_FLITFLPEN RCC_AHB1LPENR_FLITFLPEN_Msk
11262#define RCC_AHB1LPENR_SRAM1LPEN_Pos (16U)
11263#define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM1LPEN_Pos)
11264#define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk
11265#define RCC_AHB1LPENR_SRAM2LPEN_Pos (17U)
11266#define RCC_AHB1LPENR_SRAM2LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM2LPEN_Pos)
11267#define RCC_AHB1LPENR_SRAM2LPEN RCC_AHB1LPENR_SRAM2LPEN_Msk
11268#define RCC_AHB1LPENR_BKPSRAMLPEN_Pos (18U)
11269#define RCC_AHB1LPENR_BKPSRAMLPEN_Msk (0x1UL << RCC_AHB1LPENR_BKPSRAMLPEN_Pos)
11270#define RCC_AHB1LPENR_BKPSRAMLPEN RCC_AHB1LPENR_BKPSRAMLPEN_Msk
11271#define RCC_AHB1LPENR_SRAM3LPEN_Pos (19U)
11272#define RCC_AHB1LPENR_SRAM3LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM3LPEN_Pos)
11273#define RCC_AHB1LPENR_SRAM3LPEN RCC_AHB1LPENR_SRAM3LPEN_Msk
11274#define RCC_AHB1LPENR_DMA1LPEN_Pos (21U)
11275#define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos)
11276#define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
11277#define RCC_AHB1LPENR_DMA2LPEN_Pos (22U)
11278#define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos)
11279#define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
11280#define RCC_AHB1LPENR_DMA2DLPEN_Pos (23U)
11281#define RCC_AHB1LPENR_DMA2DLPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA2DLPEN_Pos)
11282#define RCC_AHB1LPENR_DMA2DLPEN RCC_AHB1LPENR_DMA2DLPEN_Msk
11283
11284#define RCC_AHB1LPENR_ETHMACLPEN_Pos (25U)
11285#define RCC_AHB1LPENR_ETHMACLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACLPEN_Pos)
11286#define RCC_AHB1LPENR_ETHMACLPEN RCC_AHB1LPENR_ETHMACLPEN_Msk
11287#define RCC_AHB1LPENR_ETHMACTXLPEN_Pos (26U)
11288#define RCC_AHB1LPENR_ETHMACTXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACTXLPEN_Pos)
11289#define RCC_AHB1LPENR_ETHMACTXLPEN RCC_AHB1LPENR_ETHMACTXLPEN_Msk
11290#define RCC_AHB1LPENR_ETHMACRXLPEN_Pos (27U)
11291#define RCC_AHB1LPENR_ETHMACRXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACRXLPEN_Pos)
11292#define RCC_AHB1LPENR_ETHMACRXLPEN RCC_AHB1LPENR_ETHMACRXLPEN_Msk
11293#define RCC_AHB1LPENR_ETHMACPTPLPEN_Pos (28U)
11294#define RCC_AHB1LPENR_ETHMACPTPLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACPTPLPEN_Pos)
11295#define RCC_AHB1LPENR_ETHMACPTPLPEN RCC_AHB1LPENR_ETHMACPTPLPEN_Msk
11296#define RCC_AHB1LPENR_OTGHSLPEN_Pos (29U)
11297#define RCC_AHB1LPENR_OTGHSLPEN_Msk (0x1UL << RCC_AHB1LPENR_OTGHSLPEN_Pos)
11298#define RCC_AHB1LPENR_OTGHSLPEN RCC_AHB1LPENR_OTGHSLPEN_Msk
11299#define RCC_AHB1LPENR_OTGHSULPILPEN_Pos (30U)
11300#define RCC_AHB1LPENR_OTGHSULPILPEN_Msk (0x1UL << RCC_AHB1LPENR_OTGHSULPILPEN_Pos)
11301#define RCC_AHB1LPENR_OTGHSULPILPEN RCC_AHB1LPENR_OTGHSULPILPEN_Msk
11302
11303/******************** Bit definition for RCC_AHB2LPENR register *************/
11304#define RCC_AHB2LPENR_DCMILPEN_Pos (0U)
11305#define RCC_AHB2LPENR_DCMILPEN_Msk (0x1UL << RCC_AHB2LPENR_DCMILPEN_Pos)
11306#define RCC_AHB2LPENR_DCMILPEN RCC_AHB2LPENR_DCMILPEN_Msk
11307#define RCC_AHB2LPENR_RNGLPEN_Pos (6U)
11308#define RCC_AHB2LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos)
11309#define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
11310#define RCC_AHB2LPENR_OTGFSLPEN_Pos (7U)
11311#define RCC_AHB2LPENR_OTGFSLPEN_Msk (0x1UL << RCC_AHB2LPENR_OTGFSLPEN_Pos)
11312#define RCC_AHB2LPENR_OTGFSLPEN RCC_AHB2LPENR_OTGFSLPEN_Msk
11313
11314/******************** Bit definition for RCC_AHB3LPENR register *************/
11315#define RCC_AHB3LPENR_FMCLPEN_Pos (0U)
11316#define RCC_AHB3LPENR_FMCLPEN_Msk (0x1UL << RCC_AHB3LPENR_FMCLPEN_Pos)
11317#define RCC_AHB3LPENR_FMCLPEN RCC_AHB3LPENR_FMCLPEN_Msk
11318
11319/******************** Bit definition for RCC_APB1LPENR register *************/
11320#define RCC_APB1LPENR_TIM2LPEN_Pos (0U)
11321#define RCC_APB1LPENR_TIM2LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos)
11322#define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk
11323#define RCC_APB1LPENR_TIM3LPEN_Pos (1U)
11324#define RCC_APB1LPENR_TIM3LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos)
11325#define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk
11326#define RCC_APB1LPENR_TIM4LPEN_Pos (2U)
11327#define RCC_APB1LPENR_TIM4LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos)
11328#define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk
11329#define RCC_APB1LPENR_TIM5LPEN_Pos (3U)
11330#define RCC_APB1LPENR_TIM5LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM5LPEN_Pos)
11331#define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk
11332#define RCC_APB1LPENR_TIM6LPEN_Pos (4U)
11333#define RCC_APB1LPENR_TIM6LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos)
11334#define RCC_APB1LPENR_TIM6LPEN RCC_APB1LPENR_TIM6LPEN_Msk
11335#define RCC_APB1LPENR_TIM7LPEN_Pos (5U)
11336#define RCC_APB1LPENR_TIM7LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM7LPEN_Pos)
11337#define RCC_APB1LPENR_TIM7LPEN RCC_APB1LPENR_TIM7LPEN_Msk
11338#define RCC_APB1LPENR_TIM12LPEN_Pos (6U)
11339#define RCC_APB1LPENR_TIM12LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM12LPEN_Pos)
11340#define RCC_APB1LPENR_TIM12LPEN RCC_APB1LPENR_TIM12LPEN_Msk
11341#define RCC_APB1LPENR_TIM13LPEN_Pos (7U)
11342#define RCC_APB1LPENR_TIM13LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM13LPEN_Pos)
11343#define RCC_APB1LPENR_TIM13LPEN RCC_APB1LPENR_TIM13LPEN_Msk
11344#define RCC_APB1LPENR_TIM14LPEN_Pos (8U)
11345#define RCC_APB1LPENR_TIM14LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM14LPEN_Pos)
11346#define RCC_APB1LPENR_TIM14LPEN RCC_APB1LPENR_TIM14LPEN_Msk
11347#define RCC_APB1LPENR_WWDGLPEN_Pos (11U)
11348#define RCC_APB1LPENR_WWDGLPEN_Msk (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos)
11349#define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk
11350#define RCC_APB1LPENR_SPI2LPEN_Pos (14U)
11351#define RCC_APB1LPENR_SPI2LPEN_Msk (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos)
11352#define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk
11353#define RCC_APB1LPENR_SPI3LPEN_Pos (15U)
11354#define RCC_APB1LPENR_SPI3LPEN_Msk (0x1UL << RCC_APB1LPENR_SPI3LPEN_Pos)
11355#define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk
11356#define RCC_APB1LPENR_USART2LPEN_Pos (17U)
11357#define RCC_APB1LPENR_USART2LPEN_Msk (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos)
11358#define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk
11359#define RCC_APB1LPENR_USART3LPEN_Pos (18U)
11360#define RCC_APB1LPENR_USART3LPEN_Msk (0x1UL << RCC_APB1LPENR_USART3LPEN_Pos)
11361#define RCC_APB1LPENR_USART3LPEN RCC_APB1LPENR_USART3LPEN_Msk
11362#define RCC_APB1LPENR_UART4LPEN_Pos (19U)
11363#define RCC_APB1LPENR_UART4LPEN_Msk (0x1UL << RCC_APB1LPENR_UART4LPEN_Pos)
11364#define RCC_APB1LPENR_UART4LPEN RCC_APB1LPENR_UART4LPEN_Msk
11365#define RCC_APB1LPENR_UART5LPEN_Pos (20U)
11366#define RCC_APB1LPENR_UART5LPEN_Msk (0x1UL << RCC_APB1LPENR_UART5LPEN_Pos)
11367#define RCC_APB1LPENR_UART5LPEN RCC_APB1LPENR_UART5LPEN_Msk
11368#define RCC_APB1LPENR_I2C1LPEN_Pos (21U)
11369#define RCC_APB1LPENR_I2C1LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos)
11370#define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk
11371#define RCC_APB1LPENR_I2C2LPEN_Pos (22U)
11372#define RCC_APB1LPENR_I2C2LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos)
11373#define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk
11374#define RCC_APB1LPENR_I2C3LPEN_Pos (23U)
11375#define RCC_APB1LPENR_I2C3LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C3LPEN_Pos)
11376#define RCC_APB1LPENR_I2C3LPEN RCC_APB1LPENR_I2C3LPEN_Msk
11377#define RCC_APB1LPENR_CAN1LPEN_Pos (25U)
11378#define RCC_APB1LPENR_CAN1LPEN_Msk (0x1UL << RCC_APB1LPENR_CAN1LPEN_Pos)
11379#define RCC_APB1LPENR_CAN1LPEN RCC_APB1LPENR_CAN1LPEN_Msk
11380#define RCC_APB1LPENR_CAN2LPEN_Pos (26U)
11381#define RCC_APB1LPENR_CAN2LPEN_Msk (0x1UL << RCC_APB1LPENR_CAN2LPEN_Pos)
11382#define RCC_APB1LPENR_CAN2LPEN RCC_APB1LPENR_CAN2LPEN_Msk
11383#define RCC_APB1LPENR_PWRLPEN_Pos (28U)
11384#define RCC_APB1LPENR_PWRLPEN_Msk (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos)
11385#define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk
11386#define RCC_APB1LPENR_DACLPEN_Pos (29U)
11387#define RCC_APB1LPENR_DACLPEN_Msk (0x1UL << RCC_APB1LPENR_DACLPEN_Pos)
11388#define RCC_APB1LPENR_DACLPEN RCC_APB1LPENR_DACLPEN_Msk
11389#define RCC_APB1LPENR_UART7LPEN_Pos (30U)
11390#define RCC_APB1LPENR_UART7LPEN_Msk (0x1UL << RCC_APB1LPENR_UART7LPEN_Pos)
11391#define RCC_APB1LPENR_UART7LPEN RCC_APB1LPENR_UART7LPEN_Msk
11392#define RCC_APB1LPENR_UART8LPEN_Pos (31U)
11393#define RCC_APB1LPENR_UART8LPEN_Msk (0x1UL << RCC_APB1LPENR_UART8LPEN_Pos)
11394#define RCC_APB1LPENR_UART8LPEN RCC_APB1LPENR_UART8LPEN_Msk
11395
11396/******************** Bit definition for RCC_APB2LPENR register *************/
11397#define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
11398#define RCC_APB2LPENR_TIM1LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos)
11399#define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
11400#define RCC_APB2LPENR_TIM8LPEN_Pos (1U)
11401#define RCC_APB2LPENR_TIM8LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos)
11402#define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk
11403#define RCC_APB2LPENR_USART1LPEN_Pos (4U)
11404#define RCC_APB2LPENR_USART1LPEN_Msk (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos)
11405#define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
11406#define RCC_APB2LPENR_USART6LPEN_Pos (5U)
11407#define RCC_APB2LPENR_USART6LPEN_Msk (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos)
11408#define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
11409#define RCC_APB2LPENR_ADC1LPEN_Pos (8U)
11410#define RCC_APB2LPENR_ADC1LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos)
11411#define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk
11412#define RCC_APB2LPENR_ADC2LPEN_Pos (9U)
11413#define RCC_APB2LPENR_ADC2LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC2LPEN_Pos)
11414#define RCC_APB2LPENR_ADC2LPEN RCC_APB2LPENR_ADC2LPEN_Msk
11415#define RCC_APB2LPENR_ADC3LPEN_Pos (10U)
11416#define RCC_APB2LPENR_ADC3LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC3LPEN_Pos)
11417#define RCC_APB2LPENR_ADC3LPEN RCC_APB2LPENR_ADC3LPEN_Msk
11418#define RCC_APB2LPENR_SDIOLPEN_Pos (11U)
11419#define RCC_APB2LPENR_SDIOLPEN_Msk (0x1UL << RCC_APB2LPENR_SDIOLPEN_Pos)
11420#define RCC_APB2LPENR_SDIOLPEN RCC_APB2LPENR_SDIOLPEN_Msk
11421#define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
11422#define RCC_APB2LPENR_SPI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos)
11423#define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
11424#define RCC_APB2LPENR_SPI4LPEN_Pos (13U)
11425#define RCC_APB2LPENR_SPI4LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos)
11426#define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk
11427#define RCC_APB2LPENR_SYSCFGLPEN_Pos (14U)
11428#define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos)
11429#define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk
11430#define RCC_APB2LPENR_TIM9LPEN_Pos (16U)
11431#define RCC_APB2LPENR_TIM9LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos)
11432#define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk
11433#define RCC_APB2LPENR_TIM10LPEN_Pos (17U)
11434#define RCC_APB2LPENR_TIM10LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos)
11435#define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk
11436#define RCC_APB2LPENR_TIM11LPEN_Pos (18U)
11437#define RCC_APB2LPENR_TIM11LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos)
11438#define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk
11439#define RCC_APB2LPENR_SPI5LPEN_Pos (20U)
11440#define RCC_APB2LPENR_SPI5LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos)
11441#define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk
11442#define RCC_APB2LPENR_SPI6LPEN_Pos (21U)
11443#define RCC_APB2LPENR_SPI6LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI6LPEN_Pos)
11444#define RCC_APB2LPENR_SPI6LPEN RCC_APB2LPENR_SPI6LPEN_Msk
11445#define RCC_APB2LPENR_SAI1LPEN_Pos (22U)
11446#define RCC_APB2LPENR_SAI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos)
11447#define RCC_APB2LPENR_SAI1LPEN RCC_APB2LPENR_SAI1LPEN_Msk
11448#define RCC_APB2LPENR_LTDCLPEN_Pos (26U)
11449#define RCC_APB2LPENR_LTDCLPEN_Msk (0x1UL << RCC_APB2LPENR_LTDCLPEN_Pos)
11450#define RCC_APB2LPENR_LTDCLPEN RCC_APB2LPENR_LTDCLPEN_Msk
11451
11452/******************** Bit definition for RCC_BDCR register ******************/
11453#define RCC_BDCR_LSEON_Pos (0U)
11454#define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos)
11455#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
11456#define RCC_BDCR_LSERDY_Pos (1U)
11457#define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos)
11458#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
11459#define RCC_BDCR_LSEBYP_Pos (2U)
11460#define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos)
11461#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
11462
11463#define RCC_BDCR_RTCSEL_Pos (8U)
11464#define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos)
11465#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
11466#define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos)
11467#define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos)
11468
11469#define RCC_BDCR_RTCEN_Pos (15U)
11470#define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos)
11471#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
11472#define RCC_BDCR_BDRST_Pos (16U)
11473#define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos)
11474#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
11475
11476/******************** Bit definition for RCC_CSR register *******************/
11477#define RCC_CSR_LSION_Pos (0U)
11478#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos)
11479#define RCC_CSR_LSION RCC_CSR_LSION_Msk
11480#define RCC_CSR_LSIRDY_Pos (1U)
11481#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos)
11482#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
11483#define RCC_CSR_RMVF_Pos (24U)
11484#define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos)
11485#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
11486#define RCC_CSR_BORRSTF_Pos (25U)
11487#define RCC_CSR_BORRSTF_Msk (0x1UL << RCC_CSR_BORRSTF_Pos)
11488#define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
11489#define RCC_CSR_PINRSTF_Pos (26U)
11490#define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos)
11491#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
11492#define RCC_CSR_PORRSTF_Pos (27U)
11493#define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos)
11494#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk
11495#define RCC_CSR_SFTRSTF_Pos (28U)
11496#define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos)
11497#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
11498#define RCC_CSR_IWDGRSTF_Pos (29U)
11499#define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos)
11500#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
11501#define RCC_CSR_WWDGRSTF_Pos (30U)
11502#define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos)
11503#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
11504#define RCC_CSR_LPWRRSTF_Pos (31U)
11505#define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos)
11506#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
11507/* Legacy defines */
11508#define RCC_CSR_PADRSTF RCC_CSR_PINRSTF
11509#define RCC_CSR_WDGRSTF RCC_CSR_IWDGRSTF
11510
11511/******************** Bit definition for RCC_SSCGR register *****************/
11512#define RCC_SSCGR_MODPER_Pos (0U)
11513#define RCC_SSCGR_MODPER_Msk (0x1FFFUL << RCC_SSCGR_MODPER_Pos)
11514#define RCC_SSCGR_MODPER RCC_SSCGR_MODPER_Msk
11515#define RCC_SSCGR_INCSTEP_Pos (13U)
11516#define RCC_SSCGR_INCSTEP_Msk (0x7FFFUL << RCC_SSCGR_INCSTEP_Pos)
11517#define RCC_SSCGR_INCSTEP RCC_SSCGR_INCSTEP_Msk
11518#define RCC_SSCGR_SPREADSEL_Pos (30U)
11519#define RCC_SSCGR_SPREADSEL_Msk (0x1UL << RCC_SSCGR_SPREADSEL_Pos)
11520#define RCC_SSCGR_SPREADSEL RCC_SSCGR_SPREADSEL_Msk
11521#define RCC_SSCGR_SSCGEN_Pos (31U)
11522#define RCC_SSCGR_SSCGEN_Msk (0x1UL << RCC_SSCGR_SSCGEN_Pos)
11523#define RCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_Msk
11524
11525/******************** Bit definition for RCC_PLLI2SCFGR register ************/
11526#define RCC_PLLI2SCFGR_PLLI2SN_Pos (6U)
11527#define RCC_PLLI2SCFGR_PLLI2SN_Msk (0x1FFUL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
11528#define RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN_Msk
11529#define RCC_PLLI2SCFGR_PLLI2SN_0 (0x001UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
11530#define RCC_PLLI2SCFGR_PLLI2SN_1 (0x002UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
11531#define RCC_PLLI2SCFGR_PLLI2SN_2 (0x004UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
11532#define RCC_PLLI2SCFGR_PLLI2SN_3 (0x008UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
11533#define RCC_PLLI2SCFGR_PLLI2SN_4 (0x010UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
11534#define RCC_PLLI2SCFGR_PLLI2SN_5 (0x020UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
11535#define RCC_PLLI2SCFGR_PLLI2SN_6 (0x040UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
11536#define RCC_PLLI2SCFGR_PLLI2SN_7 (0x080UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
11537#define RCC_PLLI2SCFGR_PLLI2SN_8 (0x100UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
11538
11539#define RCC_PLLI2SCFGR_PLLI2SQ_Pos (24U)
11540#define RCC_PLLI2SCFGR_PLLI2SQ_Msk (0xFUL << RCC_PLLI2SCFGR_PLLI2SQ_Pos)
11541#define RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ_Msk
11542#define RCC_PLLI2SCFGR_PLLI2SQ_0 (0x1UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos)
11543#define RCC_PLLI2SCFGR_PLLI2SQ_1 (0x2UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos)
11544#define RCC_PLLI2SCFGR_PLLI2SQ_2 (0x4UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos)
11545#define RCC_PLLI2SCFGR_PLLI2SQ_3 (0x8UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos)
11546#define RCC_PLLI2SCFGR_PLLI2SR_Pos (28U)
11547#define RCC_PLLI2SCFGR_PLLI2SR_Msk (0x7UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
11548#define RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR_Msk
11549#define RCC_PLLI2SCFGR_PLLI2SR_0 (0x1UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
11550#define RCC_PLLI2SCFGR_PLLI2SR_1 (0x2UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
11551#define RCC_PLLI2SCFGR_PLLI2SR_2 (0x4UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
11552
11553/******************** Bit definition for RCC_PLLSAICFGR register ************/
11554#define RCC_PLLSAICFGR_PLLSAIN_Pos (6U)
11555#define RCC_PLLSAICFGR_PLLSAIN_Msk (0x1FFUL << RCC_PLLSAICFGR_PLLSAIN_Pos)
11556#define RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN_Msk
11557#define RCC_PLLSAICFGR_PLLSAIN_0 (0x001UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
11558#define RCC_PLLSAICFGR_PLLSAIN_1 (0x002UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
11559#define RCC_PLLSAICFGR_PLLSAIN_2 (0x004UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
11560#define RCC_PLLSAICFGR_PLLSAIN_3 (0x008UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
11561#define RCC_PLLSAICFGR_PLLSAIN_4 (0x010UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
11562#define RCC_PLLSAICFGR_PLLSAIN_5 (0x020UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
11563#define RCC_PLLSAICFGR_PLLSAIN_6 (0x040UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
11564#define RCC_PLLSAICFGR_PLLSAIN_7 (0x080UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
11565#define RCC_PLLSAICFGR_PLLSAIN_8 (0x100UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
11566
11567
11568#define RCC_PLLSAICFGR_PLLSAIQ_Pos (24U)
11569#define RCC_PLLSAICFGR_PLLSAIQ_Msk (0xFUL << RCC_PLLSAICFGR_PLLSAIQ_Pos)
11570#define RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ_Msk
11571#define RCC_PLLSAICFGR_PLLSAIQ_0 (0x1UL << RCC_PLLSAICFGR_PLLSAIQ_Pos)
11572#define RCC_PLLSAICFGR_PLLSAIQ_1 (0x2UL << RCC_PLLSAICFGR_PLLSAIQ_Pos)
11573#define RCC_PLLSAICFGR_PLLSAIQ_2 (0x4UL << RCC_PLLSAICFGR_PLLSAIQ_Pos)
11574#define RCC_PLLSAICFGR_PLLSAIQ_3 (0x8UL << RCC_PLLSAICFGR_PLLSAIQ_Pos)
11575
11576#define RCC_PLLSAICFGR_PLLSAIR_Pos (28U)
11577#define RCC_PLLSAICFGR_PLLSAIR_Msk (0x7UL << RCC_PLLSAICFGR_PLLSAIR_Pos)
11578#define RCC_PLLSAICFGR_PLLSAIR RCC_PLLSAICFGR_PLLSAIR_Msk
11579#define RCC_PLLSAICFGR_PLLSAIR_0 (0x1UL << RCC_PLLSAICFGR_PLLSAIR_Pos)
11580#define RCC_PLLSAICFGR_PLLSAIR_1 (0x2UL << RCC_PLLSAICFGR_PLLSAIR_Pos)
11581#define RCC_PLLSAICFGR_PLLSAIR_2 (0x4UL << RCC_PLLSAICFGR_PLLSAIR_Pos)
11582
11583/******************** Bit definition for RCC_DCKCFGR register ***************/
11584#define RCC_DCKCFGR_PLLI2SDIVQ_Pos (0U)
11585#define RCC_DCKCFGR_PLLI2SDIVQ_Msk (0x1FUL << RCC_DCKCFGR_PLLI2SDIVQ_Pos)
11586#define RCC_DCKCFGR_PLLI2SDIVQ RCC_DCKCFGR_PLLI2SDIVQ_Msk
11587#define RCC_DCKCFGR_PLLI2SDIVQ_0 (0x01UL << RCC_DCKCFGR_PLLI2SDIVQ_Pos)
11588#define RCC_DCKCFGR_PLLI2SDIVQ_1 (0x02UL << RCC_DCKCFGR_PLLI2SDIVQ_Pos)
11589#define RCC_DCKCFGR_PLLI2SDIVQ_2 (0x04UL << RCC_DCKCFGR_PLLI2SDIVQ_Pos)
11590#define RCC_DCKCFGR_PLLI2SDIVQ_3 (0x08UL << RCC_DCKCFGR_PLLI2SDIVQ_Pos)
11591#define RCC_DCKCFGR_PLLI2SDIVQ_4 (0x10UL << RCC_DCKCFGR_PLLI2SDIVQ_Pos)
11592
11593#define RCC_DCKCFGR_PLLSAIDIVQ_Pos (8U)
11594#define RCC_DCKCFGR_PLLSAIDIVQ_Msk (0x1FUL << RCC_DCKCFGR_PLLSAIDIVQ_Pos)
11595#define RCC_DCKCFGR_PLLSAIDIVQ RCC_DCKCFGR_PLLSAIDIVQ_Msk
11596#define RCC_DCKCFGR_PLLSAIDIVQ_0 (0x01UL << RCC_DCKCFGR_PLLSAIDIVQ_Pos)
11597#define RCC_DCKCFGR_PLLSAIDIVQ_1 (0x02UL << RCC_DCKCFGR_PLLSAIDIVQ_Pos)
11598#define RCC_DCKCFGR_PLLSAIDIVQ_2 (0x04UL << RCC_DCKCFGR_PLLSAIDIVQ_Pos)
11599#define RCC_DCKCFGR_PLLSAIDIVQ_3 (0x08UL << RCC_DCKCFGR_PLLSAIDIVQ_Pos)
11600#define RCC_DCKCFGR_PLLSAIDIVQ_4 (0x10UL << RCC_DCKCFGR_PLLSAIDIVQ_Pos)
11601#define RCC_DCKCFGR_PLLSAIDIVR_Pos (16U)
11602#define RCC_DCKCFGR_PLLSAIDIVR_Msk (0x3UL << RCC_DCKCFGR_PLLSAIDIVR_Pos)
11603#define RCC_DCKCFGR_PLLSAIDIVR RCC_DCKCFGR_PLLSAIDIVR_Msk
11604#define RCC_DCKCFGR_PLLSAIDIVR_0 (0x1UL << RCC_DCKCFGR_PLLSAIDIVR_Pos)
11605#define RCC_DCKCFGR_PLLSAIDIVR_1 (0x2UL << RCC_DCKCFGR_PLLSAIDIVR_Pos)
11606
11607#define RCC_DCKCFGR_SAI1ASRC_Pos (20U)
11608#define RCC_DCKCFGR_SAI1ASRC_Msk (0x3UL << RCC_DCKCFGR_SAI1ASRC_Pos)
11609#define RCC_DCKCFGR_SAI1ASRC RCC_DCKCFGR_SAI1ASRC_Msk
11610#define RCC_DCKCFGR_SAI1ASRC_0 (0x1UL << RCC_DCKCFGR_SAI1ASRC_Pos)
11611#define RCC_DCKCFGR_SAI1ASRC_1 (0x2UL << RCC_DCKCFGR_SAI1ASRC_Pos)
11612#define RCC_DCKCFGR_SAI1BSRC_Pos (22U)
11613#define RCC_DCKCFGR_SAI1BSRC_Msk (0x3UL << RCC_DCKCFGR_SAI1BSRC_Pos)
11614#define RCC_DCKCFGR_SAI1BSRC RCC_DCKCFGR_SAI1BSRC_Msk
11615#define RCC_DCKCFGR_SAI1BSRC_0 (0x1UL << RCC_DCKCFGR_SAI1BSRC_Pos)
11616#define RCC_DCKCFGR_SAI1BSRC_1 (0x2UL << RCC_DCKCFGR_SAI1BSRC_Pos)
11617#define RCC_DCKCFGR_TIMPRE_Pos (24U)
11618#define RCC_DCKCFGR_TIMPRE_Msk (0x1UL << RCC_DCKCFGR_TIMPRE_Pos)
11619#define RCC_DCKCFGR_TIMPRE RCC_DCKCFGR_TIMPRE_Msk
11620
11621
11622/******************************************************************************/
11623/* */
11624/* RNG */
11625/* */
11626/******************************************************************************/
11627/******************** Bits definition for RNG_CR register *******************/
11628#define RNG_CR_RNGEN_Pos (2U)
11629#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos)
11630#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
11631#define RNG_CR_IE_Pos (3U)
11632#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos)
11633#define RNG_CR_IE RNG_CR_IE_Msk
11634
11635/******************** Bits definition for RNG_SR register *******************/
11636#define RNG_SR_DRDY_Pos (0U)
11637#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos)
11638#define RNG_SR_DRDY RNG_SR_DRDY_Msk
11639#define RNG_SR_CECS_Pos (1U)
11640#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos)
11641#define RNG_SR_CECS RNG_SR_CECS_Msk
11642#define RNG_SR_SECS_Pos (2U)
11643#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos)
11644#define RNG_SR_SECS RNG_SR_SECS_Msk
11645#define RNG_SR_CEIS_Pos (5U)
11646#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos)
11647#define RNG_SR_CEIS RNG_SR_CEIS_Msk
11648#define RNG_SR_SEIS_Pos (6U)
11649#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos)
11650#define RNG_SR_SEIS RNG_SR_SEIS_Msk
11651
11652/******************************************************************************/
11653/* */
11654/* Real-Time Clock (RTC) */
11655/* */
11656/******************************************************************************/
11657/*
11658 * @brief Specific device feature definitions (not present on all devices in the STM32F4 series)
11659 */
11660#define RTC_TAMPER2_SUPPORT
11661#define RTC_AF2_SUPPORT
11662/******************** Bits definition for RTC_TR register *******************/
11663#define RTC_TR_PM_Pos (22U)
11664#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos)
11665#define RTC_TR_PM RTC_TR_PM_Msk
11666#define RTC_TR_HT_Pos (20U)
11667#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos)
11668#define RTC_TR_HT RTC_TR_HT_Msk
11669#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos)
11670#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos)
11671#define RTC_TR_HU_Pos (16U)
11672#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos)
11673#define RTC_TR_HU RTC_TR_HU_Msk
11674#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos)
11675#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos)
11676#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos)
11677#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos)
11678#define RTC_TR_MNT_Pos (12U)
11679#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos)
11680#define RTC_TR_MNT RTC_TR_MNT_Msk
11681#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos)
11682#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos)
11683#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos)
11684#define RTC_TR_MNU_Pos (8U)
11685#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos)
11686#define RTC_TR_MNU RTC_TR_MNU_Msk
11687#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos)
11688#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos)
11689#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos)
11690#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos)
11691#define RTC_TR_ST_Pos (4U)
11692#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos)
11693#define RTC_TR_ST RTC_TR_ST_Msk
11694#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos)
11695#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos)
11696#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos)
11697#define RTC_TR_SU_Pos (0U)
11698#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos)
11699#define RTC_TR_SU RTC_TR_SU_Msk
11700#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos)
11701#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos)
11702#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos)
11703#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos)
11704
11705/******************** Bits definition for RTC_DR register *******************/
11706#define RTC_DR_YT_Pos (20U)
11707#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos)
11708#define RTC_DR_YT RTC_DR_YT_Msk
11709#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos)
11710#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos)
11711#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos)
11712#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos)
11713#define RTC_DR_YU_Pos (16U)
11714#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos)
11715#define RTC_DR_YU RTC_DR_YU_Msk
11716#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos)
11717#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos)
11718#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos)
11719#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos)
11720#define RTC_DR_WDU_Pos (13U)
11721#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos)
11722#define RTC_DR_WDU RTC_DR_WDU_Msk
11723#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos)
11724#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos)
11725#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos)
11726#define RTC_DR_MT_Pos (12U)
11727#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos)
11728#define RTC_DR_MT RTC_DR_MT_Msk
11729#define RTC_DR_MU_Pos (8U)
11730#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos)
11731#define RTC_DR_MU RTC_DR_MU_Msk
11732#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos)
11733#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos)
11734#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos)
11735#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos)
11736#define RTC_DR_DT_Pos (4U)
11737#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos)
11738#define RTC_DR_DT RTC_DR_DT_Msk
11739#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos)
11740#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos)
11741#define RTC_DR_DU_Pos (0U)
11742#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos)
11743#define RTC_DR_DU RTC_DR_DU_Msk
11744#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos)
11745#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos)
11746#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos)
11747#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos)
11748
11749/******************** Bits definition for RTC_CR register *******************/
11750#define RTC_CR_COE_Pos (23U)
11751#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos)
11752#define RTC_CR_COE RTC_CR_COE_Msk
11753#define RTC_CR_OSEL_Pos (21U)
11754#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos)
11755#define RTC_CR_OSEL RTC_CR_OSEL_Msk
11756#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos)
11757#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos)
11758#define RTC_CR_POL_Pos (20U)
11759#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos)
11760#define RTC_CR_POL RTC_CR_POL_Msk
11761#define RTC_CR_COSEL_Pos (19U)
11762#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos)
11763#define RTC_CR_COSEL RTC_CR_COSEL_Msk
11764#define RTC_CR_BKP_Pos (18U)
11765#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos)
11766#define RTC_CR_BKP RTC_CR_BKP_Msk
11767#define RTC_CR_SUB1H_Pos (17U)
11768#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos)
11769#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
11770#define RTC_CR_ADD1H_Pos (16U)
11771#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos)
11772#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
11773#define RTC_CR_TSIE_Pos (15U)
11774#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos)
11775#define RTC_CR_TSIE RTC_CR_TSIE_Msk
11776#define RTC_CR_WUTIE_Pos (14U)
11777#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos)
11778#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
11779#define RTC_CR_ALRBIE_Pos (13U)
11780#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos)
11781#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
11782#define RTC_CR_ALRAIE_Pos (12U)
11783#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos)
11784#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
11785#define RTC_CR_TSE_Pos (11U)
11786#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos)
11787#define RTC_CR_TSE RTC_CR_TSE_Msk
11788#define RTC_CR_WUTE_Pos (10U)
11789#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos)
11790#define RTC_CR_WUTE RTC_CR_WUTE_Msk
11791#define RTC_CR_ALRBE_Pos (9U)
11792#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos)
11793#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
11794#define RTC_CR_ALRAE_Pos (8U)
11795#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos)
11796#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
11797#define RTC_CR_DCE_Pos (7U)
11798#define RTC_CR_DCE_Msk (0x1UL << RTC_CR_DCE_Pos)
11799#define RTC_CR_DCE RTC_CR_DCE_Msk
11800#define RTC_CR_FMT_Pos (6U)
11801#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos)
11802#define RTC_CR_FMT RTC_CR_FMT_Msk
11803#define RTC_CR_BYPSHAD_Pos (5U)
11804#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos)
11805#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
11806#define RTC_CR_REFCKON_Pos (4U)
11807#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos)
11808#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
11809#define RTC_CR_TSEDGE_Pos (3U)
11810#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos)
11811#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
11812#define RTC_CR_WUCKSEL_Pos (0U)
11813#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos)
11814#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
11815#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos)
11816#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos)
11817#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos)
11818
11819/* Legacy defines */
11820#define RTC_CR_BCK RTC_CR_BKP
11821
11822/******************** Bits definition for RTC_ISR register ******************/
11823#define RTC_ISR_RECALPF_Pos (16U)
11824#define RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos)
11825#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
11826#define RTC_ISR_TAMP1F_Pos (13U)
11827#define RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos)
11828#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
11829#define RTC_ISR_TAMP2F_Pos (14U)
11830#define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos)
11831#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
11832#define RTC_ISR_TSOVF_Pos (12U)
11833#define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos)
11834#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
11835#define RTC_ISR_TSF_Pos (11U)
11836#define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos)
11837#define RTC_ISR_TSF RTC_ISR_TSF_Msk
11838#define RTC_ISR_WUTF_Pos (10U)
11839#define RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos)
11840#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
11841#define RTC_ISR_ALRBF_Pos (9U)
11842#define RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos)
11843#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
11844#define RTC_ISR_ALRAF_Pos (8U)
11845#define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos)
11846#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
11847#define RTC_ISR_INIT_Pos (7U)
11848#define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos)
11849#define RTC_ISR_INIT RTC_ISR_INIT_Msk
11850#define RTC_ISR_INITF_Pos (6U)
11851#define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos)
11852#define RTC_ISR_INITF RTC_ISR_INITF_Msk
11853#define RTC_ISR_RSF_Pos (5U)
11854#define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos)
11855#define RTC_ISR_RSF RTC_ISR_RSF_Msk
11856#define RTC_ISR_INITS_Pos (4U)
11857#define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos)
11858#define RTC_ISR_INITS RTC_ISR_INITS_Msk
11859#define RTC_ISR_SHPF_Pos (3U)
11860#define RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos)
11861#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
11862#define RTC_ISR_WUTWF_Pos (2U)
11863#define RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos)
11864#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
11865#define RTC_ISR_ALRBWF_Pos (1U)
11866#define RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos)
11867#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
11868#define RTC_ISR_ALRAWF_Pos (0U)
11869#define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos)
11870#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
11871
11872/******************** Bits definition for RTC_PRER register *****************/
11873#define RTC_PRER_PREDIV_A_Pos (16U)
11874#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos)
11875#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
11876#define RTC_PRER_PREDIV_S_Pos (0U)
11877#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)
11878#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
11879
11880/******************** Bits definition for RTC_WUTR register *****************/
11881#define RTC_WUTR_WUT_Pos (0U)
11882#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos)
11883#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
11884
11885/******************** Bits definition for RTC_CALIBR register ***************/
11886#define RTC_CALIBR_DCS_Pos (7U)
11887#define RTC_CALIBR_DCS_Msk (0x1UL << RTC_CALIBR_DCS_Pos)
11888#define RTC_CALIBR_DCS RTC_CALIBR_DCS_Msk
11889#define RTC_CALIBR_DC_Pos (0U)
11890#define RTC_CALIBR_DC_Msk (0x1FUL << RTC_CALIBR_DC_Pos)
11891#define RTC_CALIBR_DC RTC_CALIBR_DC_Msk
11892
11893/******************** Bits definition for RTC_ALRMAR register ***************/
11894#define RTC_ALRMAR_MSK4_Pos (31U)
11895#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos)
11896#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
11897#define RTC_ALRMAR_WDSEL_Pos (30U)
11898#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos)
11899#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
11900#define RTC_ALRMAR_DT_Pos (28U)
11901#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos)
11902#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
11903#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos)
11904#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos)
11905#define RTC_ALRMAR_DU_Pos (24U)
11906#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos)
11907#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
11908#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos)
11909#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos)
11910#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos)
11911#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos)
11912#define RTC_ALRMAR_MSK3_Pos (23U)
11913#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos)
11914#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
11915#define RTC_ALRMAR_PM_Pos (22U)
11916#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos)
11917#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
11918#define RTC_ALRMAR_HT_Pos (20U)
11919#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos)
11920#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
11921#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos)
11922#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos)
11923#define RTC_ALRMAR_HU_Pos (16U)
11924#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos)
11925#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
11926#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos)
11927#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos)
11928#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos)
11929#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos)
11930#define RTC_ALRMAR_MSK2_Pos (15U)
11931#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos)
11932#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
11933#define RTC_ALRMAR_MNT_Pos (12U)
11934#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos)
11935#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
11936#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos)
11937#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos)
11938#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos)
11939#define RTC_ALRMAR_MNU_Pos (8U)
11940#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos)
11941#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
11942#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos)
11943#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos)
11944#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos)
11945#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos)
11946#define RTC_ALRMAR_MSK1_Pos (7U)
11947#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos)
11948#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
11949#define RTC_ALRMAR_ST_Pos (4U)
11950#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos)
11951#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
11952#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos)
11953#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos)
11954#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos)
11955#define RTC_ALRMAR_SU_Pos (0U)
11956#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos)
11957#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
11958#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos)
11959#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos)
11960#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos)
11961#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos)
11962
11963/******************** Bits definition for RTC_ALRMBR register ***************/
11964#define RTC_ALRMBR_MSK4_Pos (31U)
11965#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos)
11966#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
11967#define RTC_ALRMBR_WDSEL_Pos (30U)
11968#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos)
11969#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
11970#define RTC_ALRMBR_DT_Pos (28U)
11971#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos)
11972#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
11973#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos)
11974#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos)
11975#define RTC_ALRMBR_DU_Pos (24U)
11976#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos)
11977#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
11978#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos)
11979#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos)
11980#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos)
11981#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos)
11982#define RTC_ALRMBR_MSK3_Pos (23U)
11983#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos)
11984#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
11985#define RTC_ALRMBR_PM_Pos (22U)
11986#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos)
11987#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
11988#define RTC_ALRMBR_HT_Pos (20U)
11989#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos)
11990#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
11991#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos)
11992#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos)
11993#define RTC_ALRMBR_HU_Pos (16U)
11994#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos)
11995#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
11996#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos)
11997#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos)
11998#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos)
11999#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos)
12000#define RTC_ALRMBR_MSK2_Pos (15U)
12001#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos)
12002#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
12003#define RTC_ALRMBR_MNT_Pos (12U)
12004#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos)
12005#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
12006#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos)
12007#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos)
12008#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos)
12009#define RTC_ALRMBR_MNU_Pos (8U)
12010#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos)
12011#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
12012#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos)
12013#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos)
12014#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos)
12015#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos)
12016#define RTC_ALRMBR_MSK1_Pos (7U)
12017#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos)
12018#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
12019#define RTC_ALRMBR_ST_Pos (4U)
12020#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos)
12021#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
12022#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos)
12023#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos)
12024#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos)
12025#define RTC_ALRMBR_SU_Pos (0U)
12026#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos)
12027#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
12028#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos)
12029#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos)
12030#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos)
12031#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos)
12032
12033/******************** Bits definition for RTC_WPR register ******************/
12034#define RTC_WPR_KEY_Pos (0U)
12035#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos)
12036#define RTC_WPR_KEY RTC_WPR_KEY_Msk
12037
12038/******************** Bits definition for RTC_SSR register ******************/
12039#define RTC_SSR_SS_Pos (0U)
12040#define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos)
12041#define RTC_SSR_SS RTC_SSR_SS_Msk
12042
12043/******************** Bits definition for RTC_SHIFTR register ***************/
12044#define RTC_SHIFTR_SUBFS_Pos (0U)
12045#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)
12046#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
12047#define RTC_SHIFTR_ADD1S_Pos (31U)
12048#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos)
12049#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
12050
12051/******************** Bits definition for RTC_TSTR register *****************/
12052#define RTC_TSTR_PM_Pos (22U)
12053#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos)
12054#define RTC_TSTR_PM RTC_TSTR_PM_Msk
12055#define RTC_TSTR_HT_Pos (20U)
12056#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos)
12057#define RTC_TSTR_HT RTC_TSTR_HT_Msk
12058#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos)
12059#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos)
12060#define RTC_TSTR_HU_Pos (16U)
12061#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos)
12062#define RTC_TSTR_HU RTC_TSTR_HU_Msk
12063#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos)
12064#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos)
12065#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos)
12066#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos)
12067#define RTC_TSTR_MNT_Pos (12U)
12068#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos)
12069#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
12070#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos)
12071#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos)
12072#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos)
12073#define RTC_TSTR_MNU_Pos (8U)
12074#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos)
12075#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
12076#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos)
12077#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos)
12078#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos)
12079#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos)
12080#define RTC_TSTR_ST_Pos (4U)
12081#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos)
12082#define RTC_TSTR_ST RTC_TSTR_ST_Msk
12083#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos)
12084#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos)
12085#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos)
12086#define RTC_TSTR_SU_Pos (0U)
12087#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos)
12088#define RTC_TSTR_SU RTC_TSTR_SU_Msk
12089#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos)
12090#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos)
12091#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos)
12092#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos)
12093
12094/******************** Bits definition for RTC_TSDR register *****************/
12095#define RTC_TSDR_WDU_Pos (13U)
12096#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos)
12097#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
12098#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos)
12099#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos)
12100#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos)
12101#define RTC_TSDR_MT_Pos (12U)
12102#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos)
12103#define RTC_TSDR_MT RTC_TSDR_MT_Msk
12104#define RTC_TSDR_MU_Pos (8U)
12105#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos)
12106#define RTC_TSDR_MU RTC_TSDR_MU_Msk
12107#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos)
12108#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos)
12109#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos)
12110#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos)
12111#define RTC_TSDR_DT_Pos (4U)
12112#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos)
12113#define RTC_TSDR_DT RTC_TSDR_DT_Msk
12114#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos)
12115#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos)
12116#define RTC_TSDR_DU_Pos (0U)
12117#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos)
12118#define RTC_TSDR_DU RTC_TSDR_DU_Msk
12119#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos)
12120#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos)
12121#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos)
12122#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos)
12123
12124/******************** Bits definition for RTC_TSSSR register ****************/
12125#define RTC_TSSSR_SS_Pos (0U)
12126#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos)
12127#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
12128
12129/******************** Bits definition for RTC_CAL register *****************/
12130#define RTC_CALR_CALP_Pos (15U)
12131#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos)
12132#define RTC_CALR_CALP RTC_CALR_CALP_Msk
12133#define RTC_CALR_CALW8_Pos (14U)
12134#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos)
12135#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
12136#define RTC_CALR_CALW16_Pos (13U)
12137#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos)
12138#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
12139#define RTC_CALR_CALM_Pos (0U)
12140#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos)
12141#define RTC_CALR_CALM RTC_CALR_CALM_Msk
12142#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos)
12143#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos)
12144#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos)
12145#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos)
12146#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos)
12147#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos)
12148#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos)
12149#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos)
12150#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos)
12151
12152/******************** Bits definition for RTC_TAFCR register ****************/
12153#define RTC_TAFCR_ALARMOUTTYPE_Pos (18U)
12154#define RTC_TAFCR_ALARMOUTTYPE_Msk (0x1UL << RTC_TAFCR_ALARMOUTTYPE_Pos)
12155#define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_ALARMOUTTYPE_Msk
12156#define RTC_TAFCR_TSINSEL_Pos (17U)
12157#define RTC_TAFCR_TSINSEL_Msk (0x1UL << RTC_TAFCR_TSINSEL_Pos)
12158#define RTC_TAFCR_TSINSEL RTC_TAFCR_TSINSEL_Msk
12159#define RTC_TAFCR_TAMP1INSEL_Pos (16U)
12160#define RTC_TAFCR_TAMP1INSEL_Msk (0x1UL << RTC_TAFCR_TAMP1INSEL_Pos)
12161#define RTC_TAFCR_TAMP1INSEL RTC_TAFCR_TAMP1INSEL_Msk
12162#define RTC_TAFCR_TAMPPUDIS_Pos (15U)
12163#define RTC_TAFCR_TAMPPUDIS_Msk (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos)
12164#define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk
12165#define RTC_TAFCR_TAMPPRCH_Pos (13U)
12166#define RTC_TAFCR_TAMPPRCH_Msk (0x3UL << RTC_TAFCR_TAMPPRCH_Pos)
12167#define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk
12168#define RTC_TAFCR_TAMPPRCH_0 (0x1UL << RTC_TAFCR_TAMPPRCH_Pos)
12169#define RTC_TAFCR_TAMPPRCH_1 (0x2UL << RTC_TAFCR_TAMPPRCH_Pos)
12170#define RTC_TAFCR_TAMPFLT_Pos (11U)
12171#define RTC_TAFCR_TAMPFLT_Msk (0x3UL << RTC_TAFCR_TAMPFLT_Pos)
12172#define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk
12173#define RTC_TAFCR_TAMPFLT_0 (0x1UL << RTC_TAFCR_TAMPFLT_Pos)
12174#define RTC_TAFCR_TAMPFLT_1 (0x2UL << RTC_TAFCR_TAMPFLT_Pos)
12175#define RTC_TAFCR_TAMPFREQ_Pos (8U)
12176#define RTC_TAFCR_TAMPFREQ_Msk (0x7UL << RTC_TAFCR_TAMPFREQ_Pos)
12177#define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk
12178#define RTC_TAFCR_TAMPFREQ_0 (0x1UL << RTC_TAFCR_TAMPFREQ_Pos)
12179#define RTC_TAFCR_TAMPFREQ_1 (0x2UL << RTC_TAFCR_TAMPFREQ_Pos)
12180#define RTC_TAFCR_TAMPFREQ_2 (0x4UL << RTC_TAFCR_TAMPFREQ_Pos)
12181#define RTC_TAFCR_TAMPTS_Pos (7U)
12182#define RTC_TAFCR_TAMPTS_Msk (0x1UL << RTC_TAFCR_TAMPTS_Pos)
12183#define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk
12184#define RTC_TAFCR_TAMP2TRG_Pos (4U)
12185#define RTC_TAFCR_TAMP2TRG_Msk (0x1UL << RTC_TAFCR_TAMP2TRG_Pos)
12186#define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk
12187#define RTC_TAFCR_TAMP2E_Pos (3U)
12188#define RTC_TAFCR_TAMP2E_Msk (0x1UL << RTC_TAFCR_TAMP2E_Pos)
12189#define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk
12190#define RTC_TAFCR_TAMPIE_Pos (2U)
12191#define RTC_TAFCR_TAMPIE_Msk (0x1UL << RTC_TAFCR_TAMPIE_Pos)
12192#define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk
12193#define RTC_TAFCR_TAMP1TRG_Pos (1U)
12194#define RTC_TAFCR_TAMP1TRG_Msk (0x1UL << RTC_TAFCR_TAMP1TRG_Pos)
12195#define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk
12196#define RTC_TAFCR_TAMP1E_Pos (0U)
12197#define RTC_TAFCR_TAMP1E_Msk (0x1UL << RTC_TAFCR_TAMP1E_Pos)
12198#define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
12199
12200/* Legacy defines */
12201#define RTC_TAFCR_TAMPINSEL RTC_TAFCR_TAMP1INSEL
12202
12203/******************** Bits definition for RTC_ALRMASSR register *************/
12204#define RTC_ALRMASSR_MASKSS_Pos (24U)
12205#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos)
12206#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
12207#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos)
12208#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos)
12209#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos)
12210#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos)
12211#define RTC_ALRMASSR_SS_Pos (0U)
12212#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos)
12213#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
12214
12215/******************** Bits definition for RTC_ALRMBSSR register *************/
12216#define RTC_ALRMBSSR_MASKSS_Pos (24U)
12217#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)
12218#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
12219#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)
12220#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)
12221#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)
12222#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)
12223#define RTC_ALRMBSSR_SS_Pos (0U)
12224#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)
12225#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
12226
12227/******************** Bits definition for RTC_BKP0R register ****************/
12228#define RTC_BKP0R_Pos (0U)
12229#define RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos)
12230#define RTC_BKP0R RTC_BKP0R_Msk
12231
12232/******************** Bits definition for RTC_BKP1R register ****************/
12233#define RTC_BKP1R_Pos (0U)
12234#define RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos)
12235#define RTC_BKP1R RTC_BKP1R_Msk
12236
12237/******************** Bits definition for RTC_BKP2R register ****************/
12238#define RTC_BKP2R_Pos (0U)
12239#define RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos)
12240#define RTC_BKP2R RTC_BKP2R_Msk
12241
12242/******************** Bits definition for RTC_BKP3R register ****************/
12243#define RTC_BKP3R_Pos (0U)
12244#define RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos)
12245#define RTC_BKP3R RTC_BKP3R_Msk
12246
12247/******************** Bits definition for RTC_BKP4R register ****************/
12248#define RTC_BKP4R_Pos (0U)
12249#define RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos)
12250#define RTC_BKP4R RTC_BKP4R_Msk
12251
12252/******************** Bits definition for RTC_BKP5R register ****************/
12253#define RTC_BKP5R_Pos (0U)
12254#define RTC_BKP5R_Msk (0xFFFFFFFFUL << RTC_BKP5R_Pos)
12255#define RTC_BKP5R RTC_BKP5R_Msk
12256
12257/******************** Bits definition for RTC_BKP6R register ****************/
12258#define RTC_BKP6R_Pos (0U)
12259#define RTC_BKP6R_Msk (0xFFFFFFFFUL << RTC_BKP6R_Pos)
12260#define RTC_BKP6R RTC_BKP6R_Msk
12261
12262/******************** Bits definition for RTC_BKP7R register ****************/
12263#define RTC_BKP7R_Pos (0U)
12264#define RTC_BKP7R_Msk (0xFFFFFFFFUL << RTC_BKP7R_Pos)
12265#define RTC_BKP7R RTC_BKP7R_Msk
12266
12267/******************** Bits definition for RTC_BKP8R register ****************/
12268#define RTC_BKP8R_Pos (0U)
12269#define RTC_BKP8R_Msk (0xFFFFFFFFUL << RTC_BKP8R_Pos)
12270#define RTC_BKP8R RTC_BKP8R_Msk
12271
12272/******************** Bits definition for RTC_BKP9R register ****************/
12273#define RTC_BKP9R_Pos (0U)
12274#define RTC_BKP9R_Msk (0xFFFFFFFFUL << RTC_BKP9R_Pos)
12275#define RTC_BKP9R RTC_BKP9R_Msk
12276
12277/******************** Bits definition for RTC_BKP10R register ***************/
12278#define RTC_BKP10R_Pos (0U)
12279#define RTC_BKP10R_Msk (0xFFFFFFFFUL << RTC_BKP10R_Pos)
12280#define RTC_BKP10R RTC_BKP10R_Msk
12281
12282/******************** Bits definition for RTC_BKP11R register ***************/
12283#define RTC_BKP11R_Pos (0U)
12284#define RTC_BKP11R_Msk (0xFFFFFFFFUL << RTC_BKP11R_Pos)
12285#define RTC_BKP11R RTC_BKP11R_Msk
12286
12287/******************** Bits definition for RTC_BKP12R register ***************/
12288#define RTC_BKP12R_Pos (0U)
12289#define RTC_BKP12R_Msk (0xFFFFFFFFUL << RTC_BKP12R_Pos)
12290#define RTC_BKP12R RTC_BKP12R_Msk
12291
12292/******************** Bits definition for RTC_BKP13R register ***************/
12293#define RTC_BKP13R_Pos (0U)
12294#define RTC_BKP13R_Msk (0xFFFFFFFFUL << RTC_BKP13R_Pos)
12295#define RTC_BKP13R RTC_BKP13R_Msk
12296
12297/******************** Bits definition for RTC_BKP14R register ***************/
12298#define RTC_BKP14R_Pos (0U)
12299#define RTC_BKP14R_Msk (0xFFFFFFFFUL << RTC_BKP14R_Pos)
12300#define RTC_BKP14R RTC_BKP14R_Msk
12301
12302/******************** Bits definition for RTC_BKP15R register ***************/
12303#define RTC_BKP15R_Pos (0U)
12304#define RTC_BKP15R_Msk (0xFFFFFFFFUL << RTC_BKP15R_Pos)
12305#define RTC_BKP15R RTC_BKP15R_Msk
12306
12307/******************** Bits definition for RTC_BKP16R register ***************/
12308#define RTC_BKP16R_Pos (0U)
12309#define RTC_BKP16R_Msk (0xFFFFFFFFUL << RTC_BKP16R_Pos)
12310#define RTC_BKP16R RTC_BKP16R_Msk
12311
12312/******************** Bits definition for RTC_BKP17R register ***************/
12313#define RTC_BKP17R_Pos (0U)
12314#define RTC_BKP17R_Msk (0xFFFFFFFFUL << RTC_BKP17R_Pos)
12315#define RTC_BKP17R RTC_BKP17R_Msk
12316
12317/******************** Bits definition for RTC_BKP18R register ***************/
12318#define RTC_BKP18R_Pos (0U)
12319#define RTC_BKP18R_Msk (0xFFFFFFFFUL << RTC_BKP18R_Pos)
12320#define RTC_BKP18R RTC_BKP18R_Msk
12321
12322/******************** Bits definition for RTC_BKP19R register ***************/
12323#define RTC_BKP19R_Pos (0U)
12324#define RTC_BKP19R_Msk (0xFFFFFFFFUL << RTC_BKP19R_Pos)
12325#define RTC_BKP19R RTC_BKP19R_Msk
12326
12327/******************** Number of backup registers ******************************/
12328#define RTC_BKP_NUMBER 0x000000014U
12329
12330/******************************************************************************/
12331/* */
12332/* Serial Audio Interface */
12333/* */
12334/******************************************************************************/
12335/******************** Bit definition for SAI_GCR register *******************/
12336#define SAI_GCR_SYNCIN_Pos (0U)
12337#define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos)
12338#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk
12339#define SAI_GCR_SYNCIN_0 (0x1UL << SAI_GCR_SYNCIN_Pos)
12340#define SAI_GCR_SYNCIN_1 (0x2UL << SAI_GCR_SYNCIN_Pos)
12341
12342#define SAI_GCR_SYNCOUT_Pos (4U)
12343#define SAI_GCR_SYNCOUT_Msk (0x3UL << SAI_GCR_SYNCOUT_Pos)
12344#define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk
12345#define SAI_GCR_SYNCOUT_0 (0x1UL << SAI_GCR_SYNCOUT_Pos)
12346#define SAI_GCR_SYNCOUT_1 (0x2UL << SAI_GCR_SYNCOUT_Pos)
12347
12348/******************* Bit definition for SAI_xCR1 register *******************/
12349#define SAI_xCR1_MODE_Pos (0U)
12350#define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos)
12351#define SAI_xCR1_MODE SAI_xCR1_MODE_Msk
12352#define SAI_xCR1_MODE_0 (0x1UL << SAI_xCR1_MODE_Pos)
12353#define SAI_xCR1_MODE_1 (0x2UL << SAI_xCR1_MODE_Pos)
12354
12355#define SAI_xCR1_PRTCFG_Pos (2U)
12356#define SAI_xCR1_PRTCFG_Msk (0x3UL << SAI_xCR1_PRTCFG_Pos)
12357#define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk
12358#define SAI_xCR1_PRTCFG_0 (0x1UL << SAI_xCR1_PRTCFG_Pos)
12359#define SAI_xCR1_PRTCFG_1 (0x2UL << SAI_xCR1_PRTCFG_Pos)
12360
12361#define SAI_xCR1_DS_Pos (5U)
12362#define SAI_xCR1_DS_Msk (0x7UL << SAI_xCR1_DS_Pos)
12363#define SAI_xCR1_DS SAI_xCR1_DS_Msk
12364#define SAI_xCR1_DS_0 (0x1UL << SAI_xCR1_DS_Pos)
12365#define SAI_xCR1_DS_1 (0x2UL << SAI_xCR1_DS_Pos)
12366#define SAI_xCR1_DS_2 (0x4UL << SAI_xCR1_DS_Pos)
12367
12368#define SAI_xCR1_LSBFIRST_Pos (8U)
12369#define SAI_xCR1_LSBFIRST_Msk (0x1UL << SAI_xCR1_LSBFIRST_Pos)
12370#define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk
12371#define SAI_xCR1_CKSTR_Pos (9U)
12372#define SAI_xCR1_CKSTR_Msk (0x1UL << SAI_xCR1_CKSTR_Pos)
12373#define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk
12374
12375#define SAI_xCR1_SYNCEN_Pos (10U)
12376#define SAI_xCR1_SYNCEN_Msk (0x3UL << SAI_xCR1_SYNCEN_Pos)
12377#define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk
12378#define SAI_xCR1_SYNCEN_0 (0x1UL << SAI_xCR1_SYNCEN_Pos)
12379#define SAI_xCR1_SYNCEN_1 (0x2UL << SAI_xCR1_SYNCEN_Pos)
12380
12381#define SAI_xCR1_MONO_Pos (12U)
12382#define SAI_xCR1_MONO_Msk (0x1UL << SAI_xCR1_MONO_Pos)
12383#define SAI_xCR1_MONO SAI_xCR1_MONO_Msk
12384#define SAI_xCR1_OUTDRIV_Pos (13U)
12385#define SAI_xCR1_OUTDRIV_Msk (0x1UL << SAI_xCR1_OUTDRIV_Pos)
12386#define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk
12387#define SAI_xCR1_SAIEN_Pos (16U)
12388#define SAI_xCR1_SAIEN_Msk (0x1UL << SAI_xCR1_SAIEN_Pos)
12389#define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk
12390#define SAI_xCR1_DMAEN_Pos (17U)
12391#define SAI_xCR1_DMAEN_Msk (0x1UL << SAI_xCR1_DMAEN_Pos)
12392#define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk
12393#define SAI_xCR1_NODIV_Pos (19U)
12394#define SAI_xCR1_NODIV_Msk (0x1UL << SAI_xCR1_NODIV_Pos)
12395#define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk
12396
12397#define SAI_xCR1_MCKDIV_Pos (20U)
12398#define SAI_xCR1_MCKDIV_Msk (0xFUL << SAI_xCR1_MCKDIV_Pos)
12399#define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk
12400#define SAI_xCR1_MCKDIV_0 (0x1UL << SAI_xCR1_MCKDIV_Pos)
12401#define SAI_xCR1_MCKDIV_1 (0x2UL << SAI_xCR1_MCKDIV_Pos)
12402#define SAI_xCR1_MCKDIV_2 (0x4UL << SAI_xCR1_MCKDIV_Pos)
12403#define SAI_xCR1_MCKDIV_3 (0x8UL << SAI_xCR1_MCKDIV_Pos)
12404
12405/******************* Bit definition for SAI_xCR2 register *******************/
12406#define SAI_xCR2_FTH_Pos (0U)
12407#define SAI_xCR2_FTH_Msk (0x7UL << SAI_xCR2_FTH_Pos)
12408#define SAI_xCR2_FTH SAI_xCR2_FTH_Msk
12409#define SAI_xCR2_FTH_0 (0x1UL << SAI_xCR2_FTH_Pos)
12410#define SAI_xCR2_FTH_1 (0x2UL << SAI_xCR2_FTH_Pos)
12411#define SAI_xCR2_FTH_2 (0x4UL << SAI_xCR2_FTH_Pos)
12412
12413#define SAI_xCR2_FFLUSH_Pos (3U)
12414#define SAI_xCR2_FFLUSH_Msk (0x1UL << SAI_xCR2_FFLUSH_Pos)
12415#define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk
12416#define SAI_xCR2_TRIS_Pos (4U)
12417#define SAI_xCR2_TRIS_Msk (0x1UL << SAI_xCR2_TRIS_Pos)
12418#define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk
12419#define SAI_xCR2_MUTE_Pos (5U)
12420#define SAI_xCR2_MUTE_Msk (0x1UL << SAI_xCR2_MUTE_Pos)
12421#define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk
12422#define SAI_xCR2_MUTEVAL_Pos (6U)
12423#define SAI_xCR2_MUTEVAL_Msk (0x1UL << SAI_xCR2_MUTEVAL_Pos)
12424#define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk
12425
12426#define SAI_xCR2_MUTECNT_Pos (7U)
12427#define SAI_xCR2_MUTECNT_Msk (0x3FUL << SAI_xCR2_MUTECNT_Pos)
12428#define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk
12429#define SAI_xCR2_MUTECNT_0 (0x01UL << SAI_xCR2_MUTECNT_Pos)
12430#define SAI_xCR2_MUTECNT_1 (0x02UL << SAI_xCR2_MUTECNT_Pos)
12431#define SAI_xCR2_MUTECNT_2 (0x04UL << SAI_xCR2_MUTECNT_Pos)
12432#define SAI_xCR2_MUTECNT_3 (0x08UL << SAI_xCR2_MUTECNT_Pos)
12433#define SAI_xCR2_MUTECNT_4 (0x10UL << SAI_xCR2_MUTECNT_Pos)
12434#define SAI_xCR2_MUTECNT_5 (0x20UL << SAI_xCR2_MUTECNT_Pos)
12435
12436#define SAI_xCR2_CPL_Pos (13U)
12437#define SAI_xCR2_CPL_Msk (0x1UL << SAI_xCR2_CPL_Pos)
12438#define SAI_xCR2_CPL SAI_xCR2_CPL_Msk
12439
12440#define SAI_xCR2_COMP_Pos (14U)
12441#define SAI_xCR2_COMP_Msk (0x3UL << SAI_xCR2_COMP_Pos)
12442#define SAI_xCR2_COMP SAI_xCR2_COMP_Msk
12443#define SAI_xCR2_COMP_0 (0x1UL << SAI_xCR2_COMP_Pos)
12444#define SAI_xCR2_COMP_1 (0x2UL << SAI_xCR2_COMP_Pos)
12445
12446/****************** Bit definition for SAI_xFRCR register *******************/
12447#define SAI_xFRCR_FRL_Pos (0U)
12448#define SAI_xFRCR_FRL_Msk (0xFFUL << SAI_xFRCR_FRL_Pos)
12449#define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk
12450#define SAI_xFRCR_FRL_0 (0x01UL << SAI_xFRCR_FRL_Pos)
12451#define SAI_xFRCR_FRL_1 (0x02UL << SAI_xFRCR_FRL_Pos)
12452#define SAI_xFRCR_FRL_2 (0x04UL << SAI_xFRCR_FRL_Pos)
12453#define SAI_xFRCR_FRL_3 (0x08UL << SAI_xFRCR_FRL_Pos)
12454#define SAI_xFRCR_FRL_4 (0x10UL << SAI_xFRCR_FRL_Pos)
12455#define SAI_xFRCR_FRL_5 (0x20UL << SAI_xFRCR_FRL_Pos)
12456#define SAI_xFRCR_FRL_6 (0x40UL << SAI_xFRCR_FRL_Pos)
12457#define SAI_xFRCR_FRL_7 (0x80UL << SAI_xFRCR_FRL_Pos)
12458
12459#define SAI_xFRCR_FSALL_Pos (8U)
12460#define SAI_xFRCR_FSALL_Msk (0x7FUL << SAI_xFRCR_FSALL_Pos)
12461#define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk
12462#define SAI_xFRCR_FSALL_0 (0x01UL << SAI_xFRCR_FSALL_Pos)
12463#define SAI_xFRCR_FSALL_1 (0x02UL << SAI_xFRCR_FSALL_Pos)
12464#define SAI_xFRCR_FSALL_2 (0x04UL << SAI_xFRCR_FSALL_Pos)
12465#define SAI_xFRCR_FSALL_3 (0x08UL << SAI_xFRCR_FSALL_Pos)
12466#define SAI_xFRCR_FSALL_4 (0x10UL << SAI_xFRCR_FSALL_Pos)
12467#define SAI_xFRCR_FSALL_5 (0x20UL << SAI_xFRCR_FSALL_Pos)
12468#define SAI_xFRCR_FSALL_6 (0x40UL << SAI_xFRCR_FSALL_Pos)
12469
12470#define SAI_xFRCR_FSDEF_Pos (16U)
12471#define SAI_xFRCR_FSDEF_Msk (0x1UL << SAI_xFRCR_FSDEF_Pos)
12472#define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk
12473#define SAI_xFRCR_FSPOL_Pos (17U)
12474#define SAI_xFRCR_FSPOL_Msk (0x1UL << SAI_xFRCR_FSPOL_Pos)
12475#define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk
12476#define SAI_xFRCR_FSOFF_Pos (18U)
12477#define SAI_xFRCR_FSOFF_Msk (0x1UL << SAI_xFRCR_FSOFF_Pos)
12478#define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk
12479/* Legacy defines */
12480#define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
12481
12482/****************** Bit definition for SAI_xSLOTR register *******************/
12483#define SAI_xSLOTR_FBOFF_Pos (0U)
12484#define SAI_xSLOTR_FBOFF_Msk (0x1FUL << SAI_xSLOTR_FBOFF_Pos)
12485#define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk
12486#define SAI_xSLOTR_FBOFF_0 (0x01UL << SAI_xSLOTR_FBOFF_Pos)
12487#define SAI_xSLOTR_FBOFF_1 (0x02UL << SAI_xSLOTR_FBOFF_Pos)
12488#define SAI_xSLOTR_FBOFF_2 (0x04UL << SAI_xSLOTR_FBOFF_Pos)
12489#define SAI_xSLOTR_FBOFF_3 (0x08UL << SAI_xSLOTR_FBOFF_Pos)
12490#define SAI_xSLOTR_FBOFF_4 (0x10UL << SAI_xSLOTR_FBOFF_Pos)
12491
12492#define SAI_xSLOTR_SLOTSZ_Pos (6U)
12493#define SAI_xSLOTR_SLOTSZ_Msk (0x3UL << SAI_xSLOTR_SLOTSZ_Pos)
12494#define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk
12495#define SAI_xSLOTR_SLOTSZ_0 (0x1UL << SAI_xSLOTR_SLOTSZ_Pos)
12496#define SAI_xSLOTR_SLOTSZ_1 (0x2UL << SAI_xSLOTR_SLOTSZ_Pos)
12497
12498#define SAI_xSLOTR_NBSLOT_Pos (8U)
12499#define SAI_xSLOTR_NBSLOT_Msk (0xFUL << SAI_xSLOTR_NBSLOT_Pos)
12500#define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk
12501#define SAI_xSLOTR_NBSLOT_0 (0x1UL << SAI_xSLOTR_NBSLOT_Pos)
12502#define SAI_xSLOTR_NBSLOT_1 (0x2UL << SAI_xSLOTR_NBSLOT_Pos)
12503#define SAI_xSLOTR_NBSLOT_2 (0x4UL << SAI_xSLOTR_NBSLOT_Pos)
12504#define SAI_xSLOTR_NBSLOT_3 (0x8UL << SAI_xSLOTR_NBSLOT_Pos)
12505
12506#define SAI_xSLOTR_SLOTEN_Pos (16U)
12507#define SAI_xSLOTR_SLOTEN_Msk (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos)
12508#define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk
12509
12510/******************* Bit definition for SAI_xIMR register *******************/
12511#define SAI_xIMR_OVRUDRIE_Pos (0U)
12512#define SAI_xIMR_OVRUDRIE_Msk (0x1UL << SAI_xIMR_OVRUDRIE_Pos)
12513#define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk
12514#define SAI_xIMR_MUTEDETIE_Pos (1U)
12515#define SAI_xIMR_MUTEDETIE_Msk (0x1UL << SAI_xIMR_MUTEDETIE_Pos)
12516#define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk
12517#define SAI_xIMR_WCKCFGIE_Pos (2U)
12518#define SAI_xIMR_WCKCFGIE_Msk (0x1UL << SAI_xIMR_WCKCFGIE_Pos)
12519#define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk
12520#define SAI_xIMR_FREQIE_Pos (3U)
12521#define SAI_xIMR_FREQIE_Msk (0x1UL << SAI_xIMR_FREQIE_Pos)
12522#define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk
12523#define SAI_xIMR_CNRDYIE_Pos (4U)
12524#define SAI_xIMR_CNRDYIE_Msk (0x1UL << SAI_xIMR_CNRDYIE_Pos)
12525#define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk
12526#define SAI_xIMR_AFSDETIE_Pos (5U)
12527#define SAI_xIMR_AFSDETIE_Msk (0x1UL << SAI_xIMR_AFSDETIE_Pos)
12528#define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk
12529#define SAI_xIMR_LFSDETIE_Pos (6U)
12530#define SAI_xIMR_LFSDETIE_Msk (0x1UL << SAI_xIMR_LFSDETIE_Pos)
12531#define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk
12532
12533/******************** Bit definition for SAI_xSR register *******************/
12534#define SAI_xSR_OVRUDR_Pos (0U)
12535#define SAI_xSR_OVRUDR_Msk (0x1UL << SAI_xSR_OVRUDR_Pos)
12536#define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk
12537#define SAI_xSR_MUTEDET_Pos (1U)
12538#define SAI_xSR_MUTEDET_Msk (0x1UL << SAI_xSR_MUTEDET_Pos)
12539#define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk
12540#define SAI_xSR_WCKCFG_Pos (2U)
12541#define SAI_xSR_WCKCFG_Msk (0x1UL << SAI_xSR_WCKCFG_Pos)
12542#define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk
12543#define SAI_xSR_FREQ_Pos (3U)
12544#define SAI_xSR_FREQ_Msk (0x1UL << SAI_xSR_FREQ_Pos)
12545#define SAI_xSR_FREQ SAI_xSR_FREQ_Msk
12546#define SAI_xSR_CNRDY_Pos (4U)
12547#define SAI_xSR_CNRDY_Msk (0x1UL << SAI_xSR_CNRDY_Pos)
12548#define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk
12549#define SAI_xSR_AFSDET_Pos (5U)
12550#define SAI_xSR_AFSDET_Msk (0x1UL << SAI_xSR_AFSDET_Pos)
12551#define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk
12552#define SAI_xSR_LFSDET_Pos (6U)
12553#define SAI_xSR_LFSDET_Msk (0x1UL << SAI_xSR_LFSDET_Pos)
12554#define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk
12555
12556#define SAI_xSR_FLVL_Pos (16U)
12557#define SAI_xSR_FLVL_Msk (0x7UL << SAI_xSR_FLVL_Pos)
12558#define SAI_xSR_FLVL SAI_xSR_FLVL_Msk
12559#define SAI_xSR_FLVL_0 (0x1UL << SAI_xSR_FLVL_Pos)
12560#define SAI_xSR_FLVL_1 (0x2UL << SAI_xSR_FLVL_Pos)
12561#define SAI_xSR_FLVL_2 (0x4UL << SAI_xSR_FLVL_Pos)
12562
12563/****************** Bit definition for SAI_xCLRFR register ******************/
12564#define SAI_xCLRFR_COVRUDR_Pos (0U)
12565#define SAI_xCLRFR_COVRUDR_Msk (0x1UL << SAI_xCLRFR_COVRUDR_Pos)
12566#define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk
12567#define SAI_xCLRFR_CMUTEDET_Pos (1U)
12568#define SAI_xCLRFR_CMUTEDET_Msk (0x1UL << SAI_xCLRFR_CMUTEDET_Pos)
12569#define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk
12570#define SAI_xCLRFR_CWCKCFG_Pos (2U)
12571#define SAI_xCLRFR_CWCKCFG_Msk (0x1UL << SAI_xCLRFR_CWCKCFG_Pos)
12572#define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk
12573#define SAI_xCLRFR_CFREQ_Pos (3U)
12574#define SAI_xCLRFR_CFREQ_Msk (0x1UL << SAI_xCLRFR_CFREQ_Pos)
12575#define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk
12576#define SAI_xCLRFR_CCNRDY_Pos (4U)
12577#define SAI_xCLRFR_CCNRDY_Msk (0x1UL << SAI_xCLRFR_CCNRDY_Pos)
12578#define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk
12579#define SAI_xCLRFR_CAFSDET_Pos (5U)
12580#define SAI_xCLRFR_CAFSDET_Msk (0x1UL << SAI_xCLRFR_CAFSDET_Pos)
12581#define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk
12582#define SAI_xCLRFR_CLFSDET_Pos (6U)
12583#define SAI_xCLRFR_CLFSDET_Msk (0x1UL << SAI_xCLRFR_CLFSDET_Pos)
12584#define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk
12585
12586/****************** Bit definition for SAI_xDR register ******************/
12587#define SAI_xDR_DATA_Pos (0U)
12588#define SAI_xDR_DATA_Msk (0xFFFFFFFFUL << SAI_xDR_DATA_Pos)
12589#define SAI_xDR_DATA SAI_xDR_DATA_Msk
12590
12591
12592/******************************************************************************/
12593/* */
12594/* SD host Interface */
12595/* */
12596/******************************************************************************/
12597/****************** Bit definition for SDIO_POWER register ******************/
12598#define SDIO_POWER_PWRCTRL_Pos (0U)
12599#define SDIO_POWER_PWRCTRL_Msk (0x3UL << SDIO_POWER_PWRCTRL_Pos)
12600#define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk
12601#define SDIO_POWER_PWRCTRL_0 (0x1UL << SDIO_POWER_PWRCTRL_Pos)
12602#define SDIO_POWER_PWRCTRL_1 (0x2UL << SDIO_POWER_PWRCTRL_Pos)
12603
12604/****************** Bit definition for SDIO_CLKCR register ******************/
12605#define SDIO_CLKCR_CLKDIV_Pos (0U)
12606#define SDIO_CLKCR_CLKDIV_Msk (0xFFUL << SDIO_CLKCR_CLKDIV_Pos)
12607#define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk
12608#define SDIO_CLKCR_CLKEN_Pos (8U)
12609#define SDIO_CLKCR_CLKEN_Msk (0x1UL << SDIO_CLKCR_CLKEN_Pos)
12610#define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk
12611#define SDIO_CLKCR_PWRSAV_Pos (9U)
12612#define SDIO_CLKCR_PWRSAV_Msk (0x1UL << SDIO_CLKCR_PWRSAV_Pos)
12613#define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk
12614#define SDIO_CLKCR_BYPASS_Pos (10U)
12615#define SDIO_CLKCR_BYPASS_Msk (0x1UL << SDIO_CLKCR_BYPASS_Pos)
12616#define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk
12617
12618#define SDIO_CLKCR_WIDBUS_Pos (11U)
12619#define SDIO_CLKCR_WIDBUS_Msk (0x3UL << SDIO_CLKCR_WIDBUS_Pos)
12620#define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk
12621#define SDIO_CLKCR_WIDBUS_0 (0x1UL << SDIO_CLKCR_WIDBUS_Pos)
12622#define SDIO_CLKCR_WIDBUS_1 (0x2UL << SDIO_CLKCR_WIDBUS_Pos)
12623
12624#define SDIO_CLKCR_NEGEDGE_Pos (13U)
12625#define SDIO_CLKCR_NEGEDGE_Msk (0x1UL << SDIO_CLKCR_NEGEDGE_Pos)
12626#define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk
12627#define SDIO_CLKCR_HWFC_EN_Pos (14U)
12628#define SDIO_CLKCR_HWFC_EN_Msk (0x1UL << SDIO_CLKCR_HWFC_EN_Pos)
12629#define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk
12630
12631/******************* Bit definition for SDIO_ARG register *******************/
12632#define SDIO_ARG_CMDARG_Pos (0U)
12633#define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFUL << SDIO_ARG_CMDARG_Pos)
12634#define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk
12635
12636/******************* Bit definition for SDIO_CMD register *******************/
12637#define SDIO_CMD_CMDINDEX_Pos (0U)
12638#define SDIO_CMD_CMDINDEX_Msk (0x3FUL << SDIO_CMD_CMDINDEX_Pos)
12639#define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk
12640
12641#define SDIO_CMD_WAITRESP_Pos (6U)
12642#define SDIO_CMD_WAITRESP_Msk (0x3UL << SDIO_CMD_WAITRESP_Pos)
12643#define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk
12644#define SDIO_CMD_WAITRESP_0 (0x1UL << SDIO_CMD_WAITRESP_Pos)
12645#define SDIO_CMD_WAITRESP_1 (0x2UL << SDIO_CMD_WAITRESP_Pos)
12646
12647#define SDIO_CMD_WAITINT_Pos (8U)
12648#define SDIO_CMD_WAITINT_Msk (0x1UL << SDIO_CMD_WAITINT_Pos)
12649#define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk
12650#define SDIO_CMD_WAITPEND_Pos (9U)
12651#define SDIO_CMD_WAITPEND_Msk (0x1UL << SDIO_CMD_WAITPEND_Pos)
12652#define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk
12653#define SDIO_CMD_CPSMEN_Pos (10U)
12654#define SDIO_CMD_CPSMEN_Msk (0x1UL << SDIO_CMD_CPSMEN_Pos)
12655#define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk
12656#define SDIO_CMD_SDIOSUSPEND_Pos (11U)
12657#define SDIO_CMD_SDIOSUSPEND_Msk (0x1UL << SDIO_CMD_SDIOSUSPEND_Pos)
12658#define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk
12659#define SDIO_CMD_ENCMDCOMPL_Pos (12U)
12660#define SDIO_CMD_ENCMDCOMPL_Msk (0x1UL << SDIO_CMD_ENCMDCOMPL_Pos)
12661#define SDIO_CMD_ENCMDCOMPL SDIO_CMD_ENCMDCOMPL_Msk
12662#define SDIO_CMD_NIEN_Pos (13U)
12663#define SDIO_CMD_NIEN_Msk (0x1UL << SDIO_CMD_NIEN_Pos)
12664#define SDIO_CMD_NIEN SDIO_CMD_NIEN_Msk
12665#define SDIO_CMD_CEATACMD_Pos (14U)
12666#define SDIO_CMD_CEATACMD_Msk (0x1UL << SDIO_CMD_CEATACMD_Pos)
12667#define SDIO_CMD_CEATACMD SDIO_CMD_CEATACMD_Msk
12668
12669/***************** Bit definition for SDIO_RESPCMD register *****************/
12670#define SDIO_RESPCMD_RESPCMD_Pos (0U)
12671#define SDIO_RESPCMD_RESPCMD_Msk (0x3FUL << SDIO_RESPCMD_RESPCMD_Pos)
12672#define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk
12673
12674/****************** Bit definition for SDIO_RESP0 register ******************/
12675#define SDIO_RESP0_CARDSTATUS0_Pos (0U)
12676#define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFUL << SDIO_RESP0_CARDSTATUS0_Pos)
12677#define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk
12678
12679/****************** Bit definition for SDIO_RESP1 register ******************/
12680#define SDIO_RESP1_CARDSTATUS1_Pos (0U)
12681#define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFUL << SDIO_RESP1_CARDSTATUS1_Pos)
12682#define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk
12683
12684/****************** Bit definition for SDIO_RESP2 register ******************/
12685#define SDIO_RESP2_CARDSTATUS2_Pos (0U)
12686#define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFUL << SDIO_RESP2_CARDSTATUS2_Pos)
12687#define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk
12688
12689/****************** Bit definition for SDIO_RESP3 register ******************/
12690#define SDIO_RESP3_CARDSTATUS3_Pos (0U)
12691#define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFUL << SDIO_RESP3_CARDSTATUS3_Pos)
12692#define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk
12693
12694/****************** Bit definition for SDIO_RESP4 register ******************/
12695#define SDIO_RESP4_CARDSTATUS4_Pos (0U)
12696#define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFUL << SDIO_RESP4_CARDSTATUS4_Pos)
12697#define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk
12698
12699/****************** Bit definition for SDIO_DTIMER register *****************/
12700#define SDIO_DTIMER_DATATIME_Pos (0U)
12701#define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFUL << SDIO_DTIMER_DATATIME_Pos)
12702#define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk
12703
12704/****************** Bit definition for SDIO_DLEN register *******************/
12705#define SDIO_DLEN_DATALENGTH_Pos (0U)
12706#define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFUL << SDIO_DLEN_DATALENGTH_Pos)
12707#define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk
12708
12709/****************** Bit definition for SDIO_DCTRL register ******************/
12710#define SDIO_DCTRL_DTEN_Pos (0U)
12711#define SDIO_DCTRL_DTEN_Msk (0x1UL << SDIO_DCTRL_DTEN_Pos)
12712#define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk
12713#define SDIO_DCTRL_DTDIR_Pos (1U)
12714#define SDIO_DCTRL_DTDIR_Msk (0x1UL << SDIO_DCTRL_DTDIR_Pos)
12715#define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk
12716#define SDIO_DCTRL_DTMODE_Pos (2U)
12717#define SDIO_DCTRL_DTMODE_Msk (0x1UL << SDIO_DCTRL_DTMODE_Pos)
12718#define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk
12719#define SDIO_DCTRL_DMAEN_Pos (3U)
12720#define SDIO_DCTRL_DMAEN_Msk (0x1UL << SDIO_DCTRL_DMAEN_Pos)
12721#define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk
12722
12723#define SDIO_DCTRL_DBLOCKSIZE_Pos (4U)
12724#define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFUL << SDIO_DCTRL_DBLOCKSIZE_Pos)
12725#define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk
12726#define SDIO_DCTRL_DBLOCKSIZE_0 (0x1UL << SDIO_DCTRL_DBLOCKSIZE_Pos)
12727#define SDIO_DCTRL_DBLOCKSIZE_1 (0x2UL << SDIO_DCTRL_DBLOCKSIZE_Pos)
12728#define SDIO_DCTRL_DBLOCKSIZE_2 (0x4UL << SDIO_DCTRL_DBLOCKSIZE_Pos)
12729#define SDIO_DCTRL_DBLOCKSIZE_3 (0x8UL << SDIO_DCTRL_DBLOCKSIZE_Pos)
12730
12731#define SDIO_DCTRL_RWSTART_Pos (8U)
12732#define SDIO_DCTRL_RWSTART_Msk (0x1UL << SDIO_DCTRL_RWSTART_Pos)
12733#define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk
12734#define SDIO_DCTRL_RWSTOP_Pos (9U)
12735#define SDIO_DCTRL_RWSTOP_Msk (0x1UL << SDIO_DCTRL_RWSTOP_Pos)
12736#define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk
12737#define SDIO_DCTRL_RWMOD_Pos (10U)
12738#define SDIO_DCTRL_RWMOD_Msk (0x1UL << SDIO_DCTRL_RWMOD_Pos)
12739#define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk
12740#define SDIO_DCTRL_SDIOEN_Pos (11U)
12741#define SDIO_DCTRL_SDIOEN_Msk (0x1UL << SDIO_DCTRL_SDIOEN_Pos)
12742#define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk
12743
12744/****************** Bit definition for SDIO_DCOUNT register *****************/
12745#define SDIO_DCOUNT_DATACOUNT_Pos (0U)
12746#define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDIO_DCOUNT_DATACOUNT_Pos)
12747#define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk
12748
12749/****************** Bit definition for SDIO_STA register ********************/
12750#define SDIO_STA_CCRCFAIL_Pos (0U)
12751#define SDIO_STA_CCRCFAIL_Msk (0x1UL << SDIO_STA_CCRCFAIL_Pos)
12752#define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk
12753#define SDIO_STA_DCRCFAIL_Pos (1U)
12754#define SDIO_STA_DCRCFAIL_Msk (0x1UL << SDIO_STA_DCRCFAIL_Pos)
12755#define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk
12756#define SDIO_STA_CTIMEOUT_Pos (2U)
12757#define SDIO_STA_CTIMEOUT_Msk (0x1UL << SDIO_STA_CTIMEOUT_Pos)
12758#define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk
12759#define SDIO_STA_DTIMEOUT_Pos (3U)
12760#define SDIO_STA_DTIMEOUT_Msk (0x1UL << SDIO_STA_DTIMEOUT_Pos)
12761#define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk
12762#define SDIO_STA_TXUNDERR_Pos (4U)
12763#define SDIO_STA_TXUNDERR_Msk (0x1UL << SDIO_STA_TXUNDERR_Pos)
12764#define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk
12765#define SDIO_STA_RXOVERR_Pos (5U)
12766#define SDIO_STA_RXOVERR_Msk (0x1UL << SDIO_STA_RXOVERR_Pos)
12767#define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk
12768#define SDIO_STA_CMDREND_Pos (6U)
12769#define SDIO_STA_CMDREND_Msk (0x1UL << SDIO_STA_CMDREND_Pos)
12770#define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk
12771#define SDIO_STA_CMDSENT_Pos (7U)
12772#define SDIO_STA_CMDSENT_Msk (0x1UL << SDIO_STA_CMDSENT_Pos)
12773#define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk
12774#define SDIO_STA_DATAEND_Pos (8U)
12775#define SDIO_STA_DATAEND_Msk (0x1UL << SDIO_STA_DATAEND_Pos)
12776#define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk
12777#define SDIO_STA_STBITERR_Pos (9U)
12778#define SDIO_STA_STBITERR_Msk (0x1UL << SDIO_STA_STBITERR_Pos)
12779#define SDIO_STA_STBITERR SDIO_STA_STBITERR_Msk
12780#define SDIO_STA_DBCKEND_Pos (10U)
12781#define SDIO_STA_DBCKEND_Msk (0x1UL << SDIO_STA_DBCKEND_Pos)
12782#define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk
12783#define SDIO_STA_CMDACT_Pos (11U)
12784#define SDIO_STA_CMDACT_Msk (0x1UL << SDIO_STA_CMDACT_Pos)
12785#define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk
12786#define SDIO_STA_TXACT_Pos (12U)
12787#define SDIO_STA_TXACT_Msk (0x1UL << SDIO_STA_TXACT_Pos)
12788#define SDIO_STA_TXACT SDIO_STA_TXACT_Msk
12789#define SDIO_STA_RXACT_Pos (13U)
12790#define SDIO_STA_RXACT_Msk (0x1UL << SDIO_STA_RXACT_Pos)
12791#define SDIO_STA_RXACT SDIO_STA_RXACT_Msk
12792#define SDIO_STA_TXFIFOHE_Pos (14U)
12793#define SDIO_STA_TXFIFOHE_Msk (0x1UL << SDIO_STA_TXFIFOHE_Pos)
12794#define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk
12795#define SDIO_STA_RXFIFOHF_Pos (15U)
12796#define SDIO_STA_RXFIFOHF_Msk (0x1UL << SDIO_STA_RXFIFOHF_Pos)
12797#define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk
12798#define SDIO_STA_TXFIFOF_Pos (16U)
12799#define SDIO_STA_TXFIFOF_Msk (0x1UL << SDIO_STA_TXFIFOF_Pos)
12800#define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk
12801#define SDIO_STA_RXFIFOF_Pos (17U)
12802#define SDIO_STA_RXFIFOF_Msk (0x1UL << SDIO_STA_RXFIFOF_Pos)
12803#define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk
12804#define SDIO_STA_TXFIFOE_Pos (18U)
12805#define SDIO_STA_TXFIFOE_Msk (0x1UL << SDIO_STA_TXFIFOE_Pos)
12806#define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk
12807#define SDIO_STA_RXFIFOE_Pos (19U)
12808#define SDIO_STA_RXFIFOE_Msk (0x1UL << SDIO_STA_RXFIFOE_Pos)
12809#define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk
12810#define SDIO_STA_TXDAVL_Pos (20U)
12811#define SDIO_STA_TXDAVL_Msk (0x1UL << SDIO_STA_TXDAVL_Pos)
12812#define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk
12813#define SDIO_STA_RXDAVL_Pos (21U)
12814#define SDIO_STA_RXDAVL_Msk (0x1UL << SDIO_STA_RXDAVL_Pos)
12815#define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk
12816#define SDIO_STA_SDIOIT_Pos (22U)
12817#define SDIO_STA_SDIOIT_Msk (0x1UL << SDIO_STA_SDIOIT_Pos)
12818#define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk
12819#define SDIO_STA_CEATAEND_Pos (23U)
12820#define SDIO_STA_CEATAEND_Msk (0x1UL << SDIO_STA_CEATAEND_Pos)
12821#define SDIO_STA_CEATAEND SDIO_STA_CEATAEND_Msk
12822
12823/******************* Bit definition for SDIO_ICR register *******************/
12824#define SDIO_ICR_CCRCFAILC_Pos (0U)
12825#define SDIO_ICR_CCRCFAILC_Msk (0x1UL << SDIO_ICR_CCRCFAILC_Pos)
12826#define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk
12827#define SDIO_ICR_DCRCFAILC_Pos (1U)
12828#define SDIO_ICR_DCRCFAILC_Msk (0x1UL << SDIO_ICR_DCRCFAILC_Pos)
12829#define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk
12830#define SDIO_ICR_CTIMEOUTC_Pos (2U)
12831#define SDIO_ICR_CTIMEOUTC_Msk (0x1UL << SDIO_ICR_CTIMEOUTC_Pos)
12832#define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk
12833#define SDIO_ICR_DTIMEOUTC_Pos (3U)
12834#define SDIO_ICR_DTIMEOUTC_Msk (0x1UL << SDIO_ICR_DTIMEOUTC_Pos)
12835#define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk
12836#define SDIO_ICR_TXUNDERRC_Pos (4U)
12837#define SDIO_ICR_TXUNDERRC_Msk (0x1UL << SDIO_ICR_TXUNDERRC_Pos)
12838#define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk
12839#define SDIO_ICR_RXOVERRC_Pos (5U)
12840#define SDIO_ICR_RXOVERRC_Msk (0x1UL << SDIO_ICR_RXOVERRC_Pos)
12841#define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk
12842#define SDIO_ICR_CMDRENDC_Pos (6U)
12843#define SDIO_ICR_CMDRENDC_Msk (0x1UL << SDIO_ICR_CMDRENDC_Pos)
12844#define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk
12845#define SDIO_ICR_CMDSENTC_Pos (7U)
12846#define SDIO_ICR_CMDSENTC_Msk (0x1UL << SDIO_ICR_CMDSENTC_Pos)
12847#define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk
12848#define SDIO_ICR_DATAENDC_Pos (8U)
12849#define SDIO_ICR_DATAENDC_Msk (0x1UL << SDIO_ICR_DATAENDC_Pos)
12850#define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk
12851#define SDIO_ICR_STBITERRC_Pos (9U)
12852#define SDIO_ICR_STBITERRC_Msk (0x1UL << SDIO_ICR_STBITERRC_Pos)
12853#define SDIO_ICR_STBITERRC SDIO_ICR_STBITERRC_Msk
12854#define SDIO_ICR_DBCKENDC_Pos (10U)
12855#define SDIO_ICR_DBCKENDC_Msk (0x1UL << SDIO_ICR_DBCKENDC_Pos)
12856#define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk
12857#define SDIO_ICR_SDIOITC_Pos (22U)
12858#define SDIO_ICR_SDIOITC_Msk (0x1UL << SDIO_ICR_SDIOITC_Pos)
12859#define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk
12860#define SDIO_ICR_CEATAENDC_Pos (23U)
12861#define SDIO_ICR_CEATAENDC_Msk (0x1UL << SDIO_ICR_CEATAENDC_Pos)
12862#define SDIO_ICR_CEATAENDC SDIO_ICR_CEATAENDC_Msk
12863
12864/****************** Bit definition for SDIO_MASK register *******************/
12865#define SDIO_MASK_CCRCFAILIE_Pos (0U)
12866#define SDIO_MASK_CCRCFAILIE_Msk (0x1UL << SDIO_MASK_CCRCFAILIE_Pos)
12867#define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk
12868#define SDIO_MASK_DCRCFAILIE_Pos (1U)
12869#define SDIO_MASK_DCRCFAILIE_Msk (0x1UL << SDIO_MASK_DCRCFAILIE_Pos)
12870#define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk
12871#define SDIO_MASK_CTIMEOUTIE_Pos (2U)
12872#define SDIO_MASK_CTIMEOUTIE_Msk (0x1UL << SDIO_MASK_CTIMEOUTIE_Pos)
12873#define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk
12874#define SDIO_MASK_DTIMEOUTIE_Pos (3U)
12875#define SDIO_MASK_DTIMEOUTIE_Msk (0x1UL << SDIO_MASK_DTIMEOUTIE_Pos)
12876#define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk
12877#define SDIO_MASK_TXUNDERRIE_Pos (4U)
12878#define SDIO_MASK_TXUNDERRIE_Msk (0x1UL << SDIO_MASK_TXUNDERRIE_Pos)
12879#define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk
12880#define SDIO_MASK_RXOVERRIE_Pos (5U)
12881#define SDIO_MASK_RXOVERRIE_Msk (0x1UL << SDIO_MASK_RXOVERRIE_Pos)
12882#define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk
12883#define SDIO_MASK_CMDRENDIE_Pos (6U)
12884#define SDIO_MASK_CMDRENDIE_Msk (0x1UL << SDIO_MASK_CMDRENDIE_Pos)
12885#define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk
12886#define SDIO_MASK_CMDSENTIE_Pos (7U)
12887#define SDIO_MASK_CMDSENTIE_Msk (0x1UL << SDIO_MASK_CMDSENTIE_Pos)
12888#define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk
12889#define SDIO_MASK_DATAENDIE_Pos (8U)
12890#define SDIO_MASK_DATAENDIE_Msk (0x1UL << SDIO_MASK_DATAENDIE_Pos)
12891#define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk
12892#define SDIO_MASK_STBITERRIE_Pos (9U)
12893#define SDIO_MASK_STBITERRIE_Msk (0x1UL << SDIO_MASK_STBITERRIE_Pos)
12894#define SDIO_MASK_STBITERRIE SDIO_MASK_STBITERRIE_Msk
12895#define SDIO_MASK_DBCKENDIE_Pos (10U)
12896#define SDIO_MASK_DBCKENDIE_Msk (0x1UL << SDIO_MASK_DBCKENDIE_Pos)
12897#define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk
12898#define SDIO_MASK_CMDACTIE_Pos (11U)
12899#define SDIO_MASK_CMDACTIE_Msk (0x1UL << SDIO_MASK_CMDACTIE_Pos)
12900#define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk
12901#define SDIO_MASK_TXACTIE_Pos (12U)
12902#define SDIO_MASK_TXACTIE_Msk (0x1UL << SDIO_MASK_TXACTIE_Pos)
12903#define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk
12904#define SDIO_MASK_RXACTIE_Pos (13U)
12905#define SDIO_MASK_RXACTIE_Msk (0x1UL << SDIO_MASK_RXACTIE_Pos)
12906#define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk
12907#define SDIO_MASK_TXFIFOHEIE_Pos (14U)
12908#define SDIO_MASK_TXFIFOHEIE_Msk (0x1UL << SDIO_MASK_TXFIFOHEIE_Pos)
12909#define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk
12910#define SDIO_MASK_RXFIFOHFIE_Pos (15U)
12911#define SDIO_MASK_RXFIFOHFIE_Msk (0x1UL << SDIO_MASK_RXFIFOHFIE_Pos)
12912#define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk
12913#define SDIO_MASK_TXFIFOFIE_Pos (16U)
12914#define SDIO_MASK_TXFIFOFIE_Msk (0x1UL << SDIO_MASK_TXFIFOFIE_Pos)
12915#define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk
12916#define SDIO_MASK_RXFIFOFIE_Pos (17U)
12917#define SDIO_MASK_RXFIFOFIE_Msk (0x1UL << SDIO_MASK_RXFIFOFIE_Pos)
12918#define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk
12919#define SDIO_MASK_TXFIFOEIE_Pos (18U)
12920#define SDIO_MASK_TXFIFOEIE_Msk (0x1UL << SDIO_MASK_TXFIFOEIE_Pos)
12921#define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk
12922#define SDIO_MASK_RXFIFOEIE_Pos (19U)
12923#define SDIO_MASK_RXFIFOEIE_Msk (0x1UL << SDIO_MASK_RXFIFOEIE_Pos)
12924#define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk
12925#define SDIO_MASK_TXDAVLIE_Pos (20U)
12926#define SDIO_MASK_TXDAVLIE_Msk (0x1UL << SDIO_MASK_TXDAVLIE_Pos)
12927#define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk
12928#define SDIO_MASK_RXDAVLIE_Pos (21U)
12929#define SDIO_MASK_RXDAVLIE_Msk (0x1UL << SDIO_MASK_RXDAVLIE_Pos)
12930#define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk
12931#define SDIO_MASK_SDIOITIE_Pos (22U)
12932#define SDIO_MASK_SDIOITIE_Msk (0x1UL << SDIO_MASK_SDIOITIE_Pos)
12933#define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk
12934#define SDIO_MASK_CEATAENDIE_Pos (23U)
12935#define SDIO_MASK_CEATAENDIE_Msk (0x1UL << SDIO_MASK_CEATAENDIE_Pos)
12936#define SDIO_MASK_CEATAENDIE SDIO_MASK_CEATAENDIE_Msk
12937
12938/***************** Bit definition for SDIO_FIFOCNT register *****************/
12939#define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)
12940#define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFUL << SDIO_FIFOCNT_FIFOCOUNT_Pos)
12941#define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk
12942
12943/****************** Bit definition for SDIO_FIFO register *******************/
12944#define SDIO_FIFO_FIFODATA_Pos (0U)
12945#define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFUL << SDIO_FIFO_FIFODATA_Pos)
12946#define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk
12947
12948/******************************************************************************/
12949/* */
12950/* Serial Peripheral Interface */
12951/* */
12952/******************************************************************************/
12953#define SPI_I2S_FULLDUPLEX_SUPPORT
12954
12955/******************* Bit definition for SPI_CR1 register ********************/
12956#define SPI_CR1_CPHA_Pos (0U)
12957#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos)
12958#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk
12959#define SPI_CR1_CPOL_Pos (1U)
12960#define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos)
12961#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk
12962#define SPI_CR1_MSTR_Pos (2U)
12963#define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos)
12964#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk
12965
12966#define SPI_CR1_BR_Pos (3U)
12967#define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos)
12968#define SPI_CR1_BR SPI_CR1_BR_Msk
12969#define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos)
12970#define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos)
12971#define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos)
12972
12973#define SPI_CR1_SPE_Pos (6U)
12974#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos)
12975#define SPI_CR1_SPE SPI_CR1_SPE_Msk
12976#define SPI_CR1_LSBFIRST_Pos (7U)
12977#define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos)
12978#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk
12979#define SPI_CR1_SSI_Pos (8U)
12980#define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos)
12981#define SPI_CR1_SSI SPI_CR1_SSI_Msk
12982#define SPI_CR1_SSM_Pos (9U)
12983#define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos)
12984#define SPI_CR1_SSM SPI_CR1_SSM_Msk
12985#define SPI_CR1_RXONLY_Pos (10U)
12986#define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos)
12987#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk
12988#define SPI_CR1_DFF_Pos (11U)
12989#define SPI_CR1_DFF_Msk (0x1UL << SPI_CR1_DFF_Pos)
12990#define SPI_CR1_DFF SPI_CR1_DFF_Msk
12991#define SPI_CR1_CRCNEXT_Pos (12U)
12992#define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos)
12993#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk
12994#define SPI_CR1_CRCEN_Pos (13U)
12995#define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos)
12996#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk
12997#define SPI_CR1_BIDIOE_Pos (14U)
12998#define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos)
12999#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk
13000#define SPI_CR1_BIDIMODE_Pos (15U)
13001#define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos)
13002#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk
13003
13004/******************* Bit definition for SPI_CR2 register ********************/
13005#define SPI_CR2_RXDMAEN_Pos (0U)
13006#define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos)
13007#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk
13008#define SPI_CR2_TXDMAEN_Pos (1U)
13009#define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos)
13010#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk
13011#define SPI_CR2_SSOE_Pos (2U)
13012#define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos)
13013#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk
13014#define SPI_CR2_FRF_Pos (4U)
13015#define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos)
13016#define SPI_CR2_FRF SPI_CR2_FRF_Msk
13017#define SPI_CR2_ERRIE_Pos (5U)
13018#define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos)
13019#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk
13020#define SPI_CR2_RXNEIE_Pos (6U)
13021#define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos)
13022#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk
13023#define SPI_CR2_TXEIE_Pos (7U)
13024#define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos)
13025#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk
13026
13027/******************** Bit definition for SPI_SR register ********************/
13028#define SPI_SR_RXNE_Pos (0U)
13029#define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos)
13030#define SPI_SR_RXNE SPI_SR_RXNE_Msk
13031#define SPI_SR_TXE_Pos (1U)
13032#define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos)
13033#define SPI_SR_TXE SPI_SR_TXE_Msk
13034#define SPI_SR_CHSIDE_Pos (2U)
13035#define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos)
13036#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk
13037#define SPI_SR_UDR_Pos (3U)
13038#define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos)
13039#define SPI_SR_UDR SPI_SR_UDR_Msk
13040#define SPI_SR_CRCERR_Pos (4U)
13041#define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos)
13042#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk
13043#define SPI_SR_MODF_Pos (5U)
13044#define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos)
13045#define SPI_SR_MODF SPI_SR_MODF_Msk
13046#define SPI_SR_OVR_Pos (6U)
13047#define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos)
13048#define SPI_SR_OVR SPI_SR_OVR_Msk
13049#define SPI_SR_BSY_Pos (7U)
13050#define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos)
13051#define SPI_SR_BSY SPI_SR_BSY_Msk
13052#define SPI_SR_FRE_Pos (8U)
13053#define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos)
13054#define SPI_SR_FRE SPI_SR_FRE_Msk
13055
13056/******************** Bit definition for SPI_DR register ********************/
13057#define SPI_DR_DR_Pos (0U)
13058#define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos)
13059#define SPI_DR_DR SPI_DR_DR_Msk
13060
13061/******************* Bit definition for SPI_CRCPR register ******************/
13062#define SPI_CRCPR_CRCPOLY_Pos (0U)
13063#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)
13064#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk
13065
13066/****************** Bit definition for SPI_RXCRCR register ******************/
13067#define SPI_RXCRCR_RXCRC_Pos (0U)
13068#define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)
13069#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk
13070
13071/****************** Bit definition for SPI_TXCRCR register ******************/
13072#define SPI_TXCRCR_TXCRC_Pos (0U)
13073#define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)
13074#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk
13075
13076/****************** Bit definition for SPI_I2SCFGR register *****************/
13077#define SPI_I2SCFGR_CHLEN_Pos (0U)
13078#define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos)
13079#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk
13080
13081#define SPI_I2SCFGR_DATLEN_Pos (1U)
13082#define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos)
13083#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk
13084#define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos)
13085#define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos)
13086
13087#define SPI_I2SCFGR_CKPOL_Pos (3U)
13088#define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos)
13089#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk
13090
13091#define SPI_I2SCFGR_I2SSTD_Pos (4U)
13092#define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)
13093#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk
13094#define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)
13095#define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)
13096
13097#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
13098#define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)
13099#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk
13100
13101#define SPI_I2SCFGR_I2SCFG_Pos (8U)
13102#define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)
13103#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk
13104#define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)
13105#define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)
13106
13107#define SPI_I2SCFGR_I2SE_Pos (10U)
13108#define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos)
13109#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk
13110#define SPI_I2SCFGR_I2SMOD_Pos (11U)
13111#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)
13112#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk
13113
13114/****************** Bit definition for SPI_I2SPR register *******************/
13115#define SPI_I2SPR_I2SDIV_Pos (0U)
13116#define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos)
13117#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk
13118#define SPI_I2SPR_ODD_Pos (8U)
13119#define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos)
13120#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk
13121#define SPI_I2SPR_MCKOE_Pos (9U)
13122#define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos)
13123#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk
13124
13125/******************************************************************************/
13126/* */
13127/* SYSCFG */
13128/* */
13129/******************************************************************************/
13130/****************** Bit definition for SYSCFG_MEMRMP register ***************/
13131#define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
13132#define SYSCFG_MEMRMP_MEM_MODE_Msk (0x7UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
13133#define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk
13134#define SYSCFG_MEMRMP_MEM_MODE_0 (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
13135#define SYSCFG_MEMRMP_MEM_MODE_1 (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
13136#define SYSCFG_MEMRMP_MEM_MODE_2 (0x4UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
13137#define SYSCFG_MEMRMP_UFB_MODE_Pos (8U)
13138#define SYSCFG_MEMRMP_UFB_MODE_Msk (0x1UL << SYSCFG_MEMRMP_UFB_MODE_Pos)
13139#define SYSCFG_MEMRMP_UFB_MODE SYSCFG_MEMRMP_UFB_MODE_Msk
13140#define SYSCFG_MEMRMP_SWP_FMC_Pos (10U)
13141#define SYSCFG_MEMRMP_SWP_FMC_Msk (0x3UL << SYSCFG_MEMRMP_SWP_FMC_Pos)
13142#define SYSCFG_MEMRMP_SWP_FMC SYSCFG_MEMRMP_SWP_FMC_Msk
13143#define SYSCFG_MEMRMP_SWP_FMC_0 (0x1UL << SYSCFG_MEMRMP_SWP_FMC_Pos)
13144/* Legacy Defines */
13145#define SYSCFG_SWP_FMC SYSCFG_MEMRMP_SWP_FMC
13146/****************** Bit definition for SYSCFG_PMC register ******************/
13147#define SYSCFG_PMC_ADCxDC2_Pos (16U)
13148#define SYSCFG_PMC_ADCxDC2_Msk (0x7UL << SYSCFG_PMC_ADCxDC2_Pos)
13149#define SYSCFG_PMC_ADCxDC2 SYSCFG_PMC_ADCxDC2_Msk
13150#define SYSCFG_PMC_ADC1DC2_Pos (16U)
13151#define SYSCFG_PMC_ADC1DC2_Msk (0x1UL << SYSCFG_PMC_ADC1DC2_Pos)
13152#define SYSCFG_PMC_ADC1DC2 SYSCFG_PMC_ADC1DC2_Msk
13153#define SYSCFG_PMC_ADC2DC2_Pos (17U)
13154#define SYSCFG_PMC_ADC2DC2_Msk (0x1UL << SYSCFG_PMC_ADC2DC2_Pos)
13155#define SYSCFG_PMC_ADC2DC2 SYSCFG_PMC_ADC2DC2_Msk
13156#define SYSCFG_PMC_ADC3DC2_Pos (18U)
13157#define SYSCFG_PMC_ADC3DC2_Msk (0x1UL << SYSCFG_PMC_ADC3DC2_Pos)
13158#define SYSCFG_PMC_ADC3DC2 SYSCFG_PMC_ADC3DC2_Msk
13159#define SYSCFG_PMC_MII_RMII_SEL_Pos (23U)
13160#define SYSCFG_PMC_MII_RMII_SEL_Msk (0x1UL << SYSCFG_PMC_MII_RMII_SEL_Pos)
13161#define SYSCFG_PMC_MII_RMII_SEL SYSCFG_PMC_MII_RMII_SEL_Msk
13162/* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
13163#define SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL
13164
13165/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
13166#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
13167#define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)
13168#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk
13169#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
13170#define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)
13171#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk
13172#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
13173#define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)
13174#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk
13175#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
13176#define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)
13177#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk
13181#define SYSCFG_EXTICR1_EXTI0_PA 0x0000U
13182#define SYSCFG_EXTICR1_EXTI0_PB 0x0001U
13183#define SYSCFG_EXTICR1_EXTI0_PC 0x0002U
13184#define SYSCFG_EXTICR1_EXTI0_PD 0x0003U
13185#define SYSCFG_EXTICR1_EXTI0_PE 0x0004U
13186#define SYSCFG_EXTICR1_EXTI0_PF 0x0005U
13187#define SYSCFG_EXTICR1_EXTI0_PG 0x0006U
13188#define SYSCFG_EXTICR1_EXTI0_PH 0x0007U
13189#define SYSCFG_EXTICR1_EXTI0_PI 0x0008U
13190#define SYSCFG_EXTICR1_EXTI0_PJ 0x0009U
13191#define SYSCFG_EXTICR1_EXTI0_PK 0x000AU
13192
13196#define SYSCFG_EXTICR1_EXTI1_PA 0x0000U
13197#define SYSCFG_EXTICR1_EXTI1_PB 0x0010U
13198#define SYSCFG_EXTICR1_EXTI1_PC 0x0020U
13199#define SYSCFG_EXTICR1_EXTI1_PD 0x0030U
13200#define SYSCFG_EXTICR1_EXTI1_PE 0x0040U
13201#define SYSCFG_EXTICR1_EXTI1_PF 0x0050U
13202#define SYSCFG_EXTICR1_EXTI1_PG 0x0060U
13203#define SYSCFG_EXTICR1_EXTI1_PH 0x0070U
13204#define SYSCFG_EXTICR1_EXTI1_PI 0x0080U
13205#define SYSCFG_EXTICR1_EXTI1_PJ 0x0090U
13206#define SYSCFG_EXTICR1_EXTI1_PK 0x00A0U
13207
13211#define SYSCFG_EXTICR1_EXTI2_PA 0x0000U
13212#define SYSCFG_EXTICR1_EXTI2_PB 0x0100U
13213#define SYSCFG_EXTICR1_EXTI2_PC 0x0200U
13214#define SYSCFG_EXTICR1_EXTI2_PD 0x0300U
13215#define SYSCFG_EXTICR1_EXTI2_PE 0x0400U
13216#define SYSCFG_EXTICR1_EXTI2_PF 0x0500U
13217#define SYSCFG_EXTICR1_EXTI2_PG 0x0600U
13218#define SYSCFG_EXTICR1_EXTI2_PH 0x0700U
13219#define SYSCFG_EXTICR1_EXTI2_PI 0x0800U
13220#define SYSCFG_EXTICR1_EXTI2_PJ 0x0900U
13221#define SYSCFG_EXTICR1_EXTI2_PK 0x0A00U
13222
13226#define SYSCFG_EXTICR1_EXTI3_PA 0x0000U
13227#define SYSCFG_EXTICR1_EXTI3_PB 0x1000U
13228#define SYSCFG_EXTICR1_EXTI3_PC 0x2000U
13229#define SYSCFG_EXTICR1_EXTI3_PD 0x3000U
13230#define SYSCFG_EXTICR1_EXTI3_PE 0x4000U
13231#define SYSCFG_EXTICR1_EXTI3_PF 0x5000U
13232#define SYSCFG_EXTICR1_EXTI3_PG 0x6000U
13233#define SYSCFG_EXTICR1_EXTI3_PH 0x7000U
13234#define SYSCFG_EXTICR1_EXTI3_PI 0x8000U
13235#define SYSCFG_EXTICR1_EXTI3_PJ 0x9000U
13236#define SYSCFG_EXTICR1_EXTI3_PK 0xA000U
13237
13238/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
13239#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
13240#define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)
13241#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk
13242#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
13243#define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)
13244#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk
13245#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
13246#define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)
13247#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk
13248#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
13249#define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)
13250#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk
13251
13255#define SYSCFG_EXTICR2_EXTI4_PA 0x0000U
13256#define SYSCFG_EXTICR2_EXTI4_PB 0x0001U
13257#define SYSCFG_EXTICR2_EXTI4_PC 0x0002U
13258#define SYSCFG_EXTICR2_EXTI4_PD 0x0003U
13259#define SYSCFG_EXTICR2_EXTI4_PE 0x0004U
13260#define SYSCFG_EXTICR2_EXTI4_PF 0x0005U
13261#define SYSCFG_EXTICR2_EXTI4_PG 0x0006U
13262#define SYSCFG_EXTICR2_EXTI4_PH 0x0007U
13263#define SYSCFG_EXTICR2_EXTI4_PI 0x0008U
13264#define SYSCFG_EXTICR2_EXTI4_PJ 0x0009U
13265#define SYSCFG_EXTICR2_EXTI4_PK 0x000AU
13266
13270#define SYSCFG_EXTICR2_EXTI5_PA 0x0000U
13271#define SYSCFG_EXTICR2_EXTI5_PB 0x0010U
13272#define SYSCFG_EXTICR2_EXTI5_PC 0x0020U
13273#define SYSCFG_EXTICR2_EXTI5_PD 0x0030U
13274#define SYSCFG_EXTICR2_EXTI5_PE 0x0040U
13275#define SYSCFG_EXTICR2_EXTI5_PF 0x0050U
13276#define SYSCFG_EXTICR2_EXTI5_PG 0x0060U
13277#define SYSCFG_EXTICR2_EXTI5_PH 0x0070U
13278#define SYSCFG_EXTICR2_EXTI5_PI 0x0080U
13279#define SYSCFG_EXTICR2_EXTI5_PJ 0x0090U
13280#define SYSCFG_EXTICR2_EXTI5_PK 0x00A0U
13281
13285#define SYSCFG_EXTICR2_EXTI6_PA 0x0000U
13286#define SYSCFG_EXTICR2_EXTI6_PB 0x0100U
13287#define SYSCFG_EXTICR2_EXTI6_PC 0x0200U
13288#define SYSCFG_EXTICR2_EXTI6_PD 0x0300U
13289#define SYSCFG_EXTICR2_EXTI6_PE 0x0400U
13290#define SYSCFG_EXTICR2_EXTI6_PF 0x0500U
13291#define SYSCFG_EXTICR2_EXTI6_PG 0x0600U
13292#define SYSCFG_EXTICR2_EXTI6_PH 0x0700U
13293#define SYSCFG_EXTICR2_EXTI6_PI 0x0800U
13294#define SYSCFG_EXTICR2_EXTI6_PJ 0x0900U
13295#define SYSCFG_EXTICR2_EXTI6_PK 0x0A00U
13296
13300#define SYSCFG_EXTICR2_EXTI7_PA 0x0000U
13301#define SYSCFG_EXTICR2_EXTI7_PB 0x1000U
13302#define SYSCFG_EXTICR2_EXTI7_PC 0x2000U
13303#define SYSCFG_EXTICR2_EXTI7_PD 0x3000U
13304#define SYSCFG_EXTICR2_EXTI7_PE 0x4000U
13305#define SYSCFG_EXTICR2_EXTI7_PF 0x5000U
13306#define SYSCFG_EXTICR2_EXTI7_PG 0x6000U
13307#define SYSCFG_EXTICR2_EXTI7_PH 0x7000U
13308#define SYSCFG_EXTICR2_EXTI7_PI 0x8000U
13309#define SYSCFG_EXTICR2_EXTI7_PJ 0x9000U
13310#define SYSCFG_EXTICR2_EXTI7_PK 0xA000U
13311
13312/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
13313#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
13314#define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)
13315#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk
13316#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
13317#define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)
13318#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk
13319#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
13320#define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)
13321#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk
13322#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
13323#define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)
13324#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk
13325
13329#define SYSCFG_EXTICR3_EXTI8_PA 0x0000U
13330#define SYSCFG_EXTICR3_EXTI8_PB 0x0001U
13331#define SYSCFG_EXTICR3_EXTI8_PC 0x0002U
13332#define SYSCFG_EXTICR3_EXTI8_PD 0x0003U
13333#define SYSCFG_EXTICR3_EXTI8_PE 0x0004U
13334#define SYSCFG_EXTICR3_EXTI8_PF 0x0005U
13335#define SYSCFG_EXTICR3_EXTI8_PG 0x0006U
13336#define SYSCFG_EXTICR3_EXTI8_PH 0x0007U
13337#define SYSCFG_EXTICR3_EXTI8_PI 0x0008U
13338#define SYSCFG_EXTICR3_EXTI8_PJ 0x0009U
13339
13343#define SYSCFG_EXTICR3_EXTI9_PA 0x0000U
13344#define SYSCFG_EXTICR3_EXTI9_PB 0x0010U
13345#define SYSCFG_EXTICR3_EXTI9_PC 0x0020U
13346#define SYSCFG_EXTICR3_EXTI9_PD 0x0030U
13347#define SYSCFG_EXTICR3_EXTI9_PE 0x0040U
13348#define SYSCFG_EXTICR3_EXTI9_PF 0x0050U
13349#define SYSCFG_EXTICR3_EXTI9_PG 0x0060U
13350#define SYSCFG_EXTICR3_EXTI9_PH 0x0070U
13351#define SYSCFG_EXTICR3_EXTI9_PI 0x0080U
13352#define SYSCFG_EXTICR3_EXTI9_PJ 0x0090U
13353
13357#define SYSCFG_EXTICR3_EXTI10_PA 0x0000U
13358#define SYSCFG_EXTICR3_EXTI10_PB 0x0100U
13359#define SYSCFG_EXTICR3_EXTI10_PC 0x0200U
13360#define SYSCFG_EXTICR3_EXTI10_PD 0x0300U
13361#define SYSCFG_EXTICR3_EXTI10_PE 0x0400U
13362#define SYSCFG_EXTICR3_EXTI10_PF 0x0500U
13363#define SYSCFG_EXTICR3_EXTI10_PG 0x0600U
13364#define SYSCFG_EXTICR3_EXTI10_PH 0x0700U
13365#define SYSCFG_EXTICR3_EXTI10_PI 0x0800U
13366#define SYSCFG_EXTICR3_EXTI10_PJ 0x0900U
13367
13371#define SYSCFG_EXTICR3_EXTI11_PA 0x0000U
13372#define SYSCFG_EXTICR3_EXTI11_PB 0x1000U
13373#define SYSCFG_EXTICR3_EXTI11_PC 0x2000U
13374#define SYSCFG_EXTICR3_EXTI11_PD 0x3000U
13375#define SYSCFG_EXTICR3_EXTI11_PE 0x4000U
13376#define SYSCFG_EXTICR3_EXTI11_PF 0x5000U
13377#define SYSCFG_EXTICR3_EXTI11_PG 0x6000U
13378#define SYSCFG_EXTICR3_EXTI11_PH 0x7000U
13379#define SYSCFG_EXTICR3_EXTI11_PI 0x8000U
13380#define SYSCFG_EXTICR3_EXTI11_PJ 0x9000U
13381
13382
13383/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
13384#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
13385#define SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)
13386#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk
13387#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
13388#define SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)
13389#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk
13390#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
13391#define SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)
13392#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk
13393#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
13394#define SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)
13395#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk
13396
13400#define SYSCFG_EXTICR4_EXTI12_PA 0x0000U
13401#define SYSCFG_EXTICR4_EXTI12_PB 0x0001U
13402#define SYSCFG_EXTICR4_EXTI12_PC 0x0002U
13403#define SYSCFG_EXTICR4_EXTI12_PD 0x0003U
13404#define SYSCFG_EXTICR4_EXTI12_PE 0x0004U
13405#define SYSCFG_EXTICR4_EXTI12_PF 0x0005U
13406#define SYSCFG_EXTICR4_EXTI12_PG 0x0006U
13407#define SYSCFG_EXTICR4_EXTI12_PH 0x0007U
13408#define SYSCFG_EXTICR4_EXTI12_PI 0x0008U
13409#define SYSCFG_EXTICR4_EXTI12_PJ 0x0009U
13410
13414#define SYSCFG_EXTICR4_EXTI13_PA 0x0000U
13415#define SYSCFG_EXTICR4_EXTI13_PB 0x0010U
13416#define SYSCFG_EXTICR4_EXTI13_PC 0x0020U
13417#define SYSCFG_EXTICR4_EXTI13_PD 0x0030U
13418#define SYSCFG_EXTICR4_EXTI13_PE 0x0040U
13419#define SYSCFG_EXTICR4_EXTI13_PF 0x0050U
13420#define SYSCFG_EXTICR4_EXTI13_PG 0x0060U
13421#define SYSCFG_EXTICR4_EXTI13_PH 0x0070U
13422#define SYSCFG_EXTICR4_EXTI13_PI 0x0008U
13423#define SYSCFG_EXTICR4_EXTI13_PJ 0x0009U
13424
13428#define SYSCFG_EXTICR4_EXTI14_PA 0x0000U
13429#define SYSCFG_EXTICR4_EXTI14_PB 0x0100U
13430#define SYSCFG_EXTICR4_EXTI14_PC 0x0200U
13431#define SYSCFG_EXTICR4_EXTI14_PD 0x0300U
13432#define SYSCFG_EXTICR4_EXTI14_PE 0x0400U
13433#define SYSCFG_EXTICR4_EXTI14_PF 0x0500U
13434#define SYSCFG_EXTICR4_EXTI14_PG 0x0600U
13435#define SYSCFG_EXTICR4_EXTI14_PH 0x0700U
13436#define SYSCFG_EXTICR4_EXTI14_PI 0x0800U
13437#define SYSCFG_EXTICR4_EXTI14_PJ 0x0900U
13438
13442#define SYSCFG_EXTICR4_EXTI15_PA 0x0000U
13443#define SYSCFG_EXTICR4_EXTI15_PB 0x1000U
13444#define SYSCFG_EXTICR4_EXTI15_PC 0x2000U
13445#define SYSCFG_EXTICR4_EXTI15_PD 0x3000U
13446#define SYSCFG_EXTICR4_EXTI15_PE 0x4000U
13447#define SYSCFG_EXTICR4_EXTI15_PF 0x5000U
13448#define SYSCFG_EXTICR4_EXTI15_PG 0x6000U
13449#define SYSCFG_EXTICR4_EXTI15_PH 0x7000U
13450#define SYSCFG_EXTICR4_EXTI15_PI 0x8000U
13451#define SYSCFG_EXTICR4_EXTI15_PJ 0x9000U
13452
13453/****************** Bit definition for SYSCFG_CMPCR register ****************/
13454#define SYSCFG_CMPCR_CMP_PD_Pos (0U)
13455#define SYSCFG_CMPCR_CMP_PD_Msk (0x1UL << SYSCFG_CMPCR_CMP_PD_Pos)
13456#define SYSCFG_CMPCR_CMP_PD SYSCFG_CMPCR_CMP_PD_Msk
13457#define SYSCFG_CMPCR_READY_Pos (8U)
13458#define SYSCFG_CMPCR_READY_Msk (0x1UL << SYSCFG_CMPCR_READY_Pos)
13459#define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk
13460
13461/******************************************************************************/
13462/* */
13463/* TIM */
13464/* */
13465/******************************************************************************/
13466/******************* Bit definition for TIM_CR1 register ********************/
13467#define TIM_CR1_CEN_Pos (0U)
13468#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos)
13469#define TIM_CR1_CEN TIM_CR1_CEN_Msk
13470#define TIM_CR1_UDIS_Pos (1U)
13471#define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos)
13472#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk
13473#define TIM_CR1_URS_Pos (2U)
13474#define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos)
13475#define TIM_CR1_URS TIM_CR1_URS_Msk
13476#define TIM_CR1_OPM_Pos (3U)
13477#define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos)
13478#define TIM_CR1_OPM TIM_CR1_OPM_Msk
13479#define TIM_CR1_DIR_Pos (4U)
13480#define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos)
13481#define TIM_CR1_DIR TIM_CR1_DIR_Msk
13482
13483#define TIM_CR1_CMS_Pos (5U)
13484#define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos)
13485#define TIM_CR1_CMS TIM_CR1_CMS_Msk
13486#define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos)
13487#define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos)
13488
13489#define TIM_CR1_ARPE_Pos (7U)
13490#define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos)
13491#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk
13492
13493#define TIM_CR1_CKD_Pos (8U)
13494#define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos)
13495#define TIM_CR1_CKD TIM_CR1_CKD_Msk
13496#define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos)
13497#define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos)
13498
13499/******************* Bit definition for TIM_CR2 register ********************/
13500#define TIM_CR2_CCPC_Pos (0U)
13501#define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos)
13502#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk
13503#define TIM_CR2_CCUS_Pos (2U)
13504#define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos)
13505#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk
13506#define TIM_CR2_CCDS_Pos (3U)
13507#define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos)
13508#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk
13509
13510#define TIM_CR2_MMS_Pos (4U)
13511#define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos)
13512#define TIM_CR2_MMS TIM_CR2_MMS_Msk
13513#define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos)
13514#define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos)
13515#define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos)
13516
13517#define TIM_CR2_TI1S_Pos (7U)
13518#define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos)
13519#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk
13520#define TIM_CR2_OIS1_Pos (8U)
13521#define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos)
13522#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk
13523#define TIM_CR2_OIS1N_Pos (9U)
13524#define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos)
13525#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk
13526#define TIM_CR2_OIS2_Pos (10U)
13527#define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos)
13528#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk
13529#define TIM_CR2_OIS2N_Pos (11U)
13530#define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos)
13531#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk
13532#define TIM_CR2_OIS3_Pos (12U)
13533#define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos)
13534#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk
13535#define TIM_CR2_OIS3N_Pos (13U)
13536#define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos)
13537#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk
13538#define TIM_CR2_OIS4_Pos (14U)
13539#define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos)
13540#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk
13541
13542/******************* Bit definition for TIM_SMCR register *******************/
13543#define TIM_SMCR_SMS_Pos (0U)
13544#define TIM_SMCR_SMS_Msk (0x7UL << TIM_SMCR_SMS_Pos)
13545#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk
13546#define TIM_SMCR_SMS_0 (0x1UL << TIM_SMCR_SMS_Pos)
13547#define TIM_SMCR_SMS_1 (0x2UL << TIM_SMCR_SMS_Pos)
13548#define TIM_SMCR_SMS_2 (0x4UL << TIM_SMCR_SMS_Pos)
13549
13550#define TIM_SMCR_TS_Pos (4U)
13551#define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos)
13552#define TIM_SMCR_TS TIM_SMCR_TS_Msk
13553#define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos)
13554#define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos)
13555#define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos)
13556
13557#define TIM_SMCR_MSM_Pos (7U)
13558#define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos)
13559#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk
13560
13561#define TIM_SMCR_ETF_Pos (8U)
13562#define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos)
13563#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk
13564#define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos)
13565#define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos)
13566#define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos)
13567#define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos)
13568
13569#define TIM_SMCR_ETPS_Pos (12U)
13570#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos)
13571#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk
13572#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos)
13573#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos)
13574
13575#define TIM_SMCR_ECE_Pos (14U)
13576#define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos)
13577#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk
13578#define TIM_SMCR_ETP_Pos (15U)
13579#define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos)
13580#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk
13581
13582/******************* Bit definition for TIM_DIER register *******************/
13583#define TIM_DIER_UIE_Pos (0U)
13584#define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos)
13585#define TIM_DIER_UIE TIM_DIER_UIE_Msk
13586#define TIM_DIER_CC1IE_Pos (1U)
13587#define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos)
13588#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk
13589#define TIM_DIER_CC2IE_Pos (2U)
13590#define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos)
13591#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk
13592#define TIM_DIER_CC3IE_Pos (3U)
13593#define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos)
13594#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk
13595#define TIM_DIER_CC4IE_Pos (4U)
13596#define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos)
13597#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk
13598#define TIM_DIER_COMIE_Pos (5U)
13599#define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos)
13600#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk
13601#define TIM_DIER_TIE_Pos (6U)
13602#define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos)
13603#define TIM_DIER_TIE TIM_DIER_TIE_Msk
13604#define TIM_DIER_BIE_Pos (7U)
13605#define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos)
13606#define TIM_DIER_BIE TIM_DIER_BIE_Msk
13607#define TIM_DIER_UDE_Pos (8U)
13608#define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos)
13609#define TIM_DIER_UDE TIM_DIER_UDE_Msk
13610#define TIM_DIER_CC1DE_Pos (9U)
13611#define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos)
13612#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk
13613#define TIM_DIER_CC2DE_Pos (10U)
13614#define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos)
13615#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk
13616#define TIM_DIER_CC3DE_Pos (11U)
13617#define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos)
13618#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk
13619#define TIM_DIER_CC4DE_Pos (12U)
13620#define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos)
13621#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk
13622#define TIM_DIER_COMDE_Pos (13U)
13623#define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos)
13624#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk
13625#define TIM_DIER_TDE_Pos (14U)
13626#define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos)
13627#define TIM_DIER_TDE TIM_DIER_TDE_Msk
13628
13629/******************** Bit definition for TIM_SR register ********************/
13630#define TIM_SR_UIF_Pos (0U)
13631#define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos)
13632#define TIM_SR_UIF TIM_SR_UIF_Msk
13633#define TIM_SR_CC1IF_Pos (1U)
13634#define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos)
13635#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk
13636#define TIM_SR_CC2IF_Pos (2U)
13637#define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos)
13638#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk
13639#define TIM_SR_CC3IF_Pos (3U)
13640#define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos)
13641#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk
13642#define TIM_SR_CC4IF_Pos (4U)
13643#define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos)
13644#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk
13645#define TIM_SR_COMIF_Pos (5U)
13646#define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos)
13647#define TIM_SR_COMIF TIM_SR_COMIF_Msk
13648#define TIM_SR_TIF_Pos (6U)
13649#define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos)
13650#define TIM_SR_TIF TIM_SR_TIF_Msk
13651#define TIM_SR_BIF_Pos (7U)
13652#define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos)
13653#define TIM_SR_BIF TIM_SR_BIF_Msk
13654#define TIM_SR_CC1OF_Pos (9U)
13655#define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos)
13656#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk
13657#define TIM_SR_CC2OF_Pos (10U)
13658#define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos)
13659#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk
13660#define TIM_SR_CC3OF_Pos (11U)
13661#define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos)
13662#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk
13663#define TIM_SR_CC4OF_Pos (12U)
13664#define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos)
13665#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk
13666
13667/******************* Bit definition for TIM_EGR register ********************/
13668#define TIM_EGR_UG_Pos (0U)
13669#define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos)
13670#define TIM_EGR_UG TIM_EGR_UG_Msk
13671#define TIM_EGR_CC1G_Pos (1U)
13672#define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos)
13673#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk
13674#define TIM_EGR_CC2G_Pos (2U)
13675#define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos)
13676#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk
13677#define TIM_EGR_CC3G_Pos (3U)
13678#define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos)
13679#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk
13680#define TIM_EGR_CC4G_Pos (4U)
13681#define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos)
13682#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk
13683#define TIM_EGR_COMG_Pos (5U)
13684#define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos)
13685#define TIM_EGR_COMG TIM_EGR_COMG_Msk
13686#define TIM_EGR_TG_Pos (6U)
13687#define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos)
13688#define TIM_EGR_TG TIM_EGR_TG_Msk
13689#define TIM_EGR_BG_Pos (7U)
13690#define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos)
13691#define TIM_EGR_BG TIM_EGR_BG_Msk
13692
13693/****************** Bit definition for TIM_CCMR1 register *******************/
13694#define TIM_CCMR1_CC1S_Pos (0U)
13695#define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos)
13696#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk
13697#define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos)
13698#define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos)
13699
13700#define TIM_CCMR1_OC1FE_Pos (2U)
13701#define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos)
13702#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk
13703#define TIM_CCMR1_OC1PE_Pos (3U)
13704#define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos)
13705#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk
13706
13707#define TIM_CCMR1_OC1M_Pos (4U)
13708#define TIM_CCMR1_OC1M_Msk (0x7UL << TIM_CCMR1_OC1M_Pos)
13709#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk
13710#define TIM_CCMR1_OC1M_0 (0x1UL << TIM_CCMR1_OC1M_Pos)
13711#define TIM_CCMR1_OC1M_1 (0x2UL << TIM_CCMR1_OC1M_Pos)
13712#define TIM_CCMR1_OC1M_2 (0x4UL << TIM_CCMR1_OC1M_Pos)
13713
13714#define TIM_CCMR1_OC1CE_Pos (7U)
13715#define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos)
13716#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk
13717
13718#define TIM_CCMR1_CC2S_Pos (8U)
13719#define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos)
13720#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk
13721#define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos)
13722#define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos)
13723
13724#define TIM_CCMR1_OC2FE_Pos (10U)
13725#define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos)
13726#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk
13727#define TIM_CCMR1_OC2PE_Pos (11U)
13728#define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos)
13729#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk
13730
13731#define TIM_CCMR1_OC2M_Pos (12U)
13732#define TIM_CCMR1_OC2M_Msk (0x7UL << TIM_CCMR1_OC2M_Pos)
13733#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk
13734#define TIM_CCMR1_OC2M_0 (0x1UL << TIM_CCMR1_OC2M_Pos)
13735#define TIM_CCMR1_OC2M_1 (0x2UL << TIM_CCMR1_OC2M_Pos)
13736#define TIM_CCMR1_OC2M_2 (0x4UL << TIM_CCMR1_OC2M_Pos)
13737
13738#define TIM_CCMR1_OC2CE_Pos (15U)
13739#define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos)
13740#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk
13741
13742/*----------------------------------------------------------------------------*/
13743
13744#define TIM_CCMR1_IC1PSC_Pos (2U)
13745#define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos)
13746#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk
13747#define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos)
13748#define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos)
13749
13750#define TIM_CCMR1_IC1F_Pos (4U)
13751#define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos)
13752#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk
13753#define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos)
13754#define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos)
13755#define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos)
13756#define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos)
13757
13758#define TIM_CCMR1_IC2PSC_Pos (10U)
13759#define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos)
13760#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk
13761#define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos)
13762#define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos)
13763
13764#define TIM_CCMR1_IC2F_Pos (12U)
13765#define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos)
13766#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk
13767#define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos)
13768#define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos)
13769#define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos)
13770#define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos)
13771
13772/****************** Bit definition for TIM_CCMR2 register *******************/
13773#define TIM_CCMR2_CC3S_Pos (0U)
13774#define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos)
13775#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk
13776#define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos)
13777#define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos)
13778
13779#define TIM_CCMR2_OC3FE_Pos (2U)
13780#define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos)
13781#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk
13782#define TIM_CCMR2_OC3PE_Pos (3U)
13783#define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos)
13784#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk
13785
13786#define TIM_CCMR2_OC3M_Pos (4U)
13787#define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos)
13788#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk
13789#define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos)
13790#define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos)
13791#define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos)
13792
13793#define TIM_CCMR2_OC3CE_Pos (7U)
13794#define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos)
13795#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk
13796
13797#define TIM_CCMR2_CC4S_Pos (8U)
13798#define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos)
13799#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk
13800#define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos)
13801#define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos)
13802
13803#define TIM_CCMR2_OC4FE_Pos (10U)
13804#define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos)
13805#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk
13806#define TIM_CCMR2_OC4PE_Pos (11U)
13807#define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos)
13808#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk
13809
13810#define TIM_CCMR2_OC4M_Pos (12U)
13811#define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos)
13812#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk
13813#define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos)
13814#define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos)
13815#define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos)
13816
13817#define TIM_CCMR2_OC4CE_Pos (15U)
13818#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos)
13819#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk
13820
13821/*----------------------------------------------------------------------------*/
13822
13823#define TIM_CCMR2_IC3PSC_Pos (2U)
13824#define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos)
13825#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk
13826#define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos)
13827#define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos)
13828
13829#define TIM_CCMR2_IC3F_Pos (4U)
13830#define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos)
13831#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk
13832#define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos)
13833#define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos)
13834#define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos)
13835#define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos)
13836
13837#define TIM_CCMR2_IC4PSC_Pos (10U)
13838#define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos)
13839#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk
13840#define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos)
13841#define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos)
13842
13843#define TIM_CCMR2_IC4F_Pos (12U)
13844#define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos)
13845#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk
13846#define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos)
13847#define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos)
13848#define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos)
13849#define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos)
13850
13851/******************* Bit definition for TIM_CCER register *******************/
13852#define TIM_CCER_CC1E_Pos (0U)
13853#define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos)
13854#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk
13855#define TIM_CCER_CC1P_Pos (1U)
13856#define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos)
13857#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk
13858#define TIM_CCER_CC1NE_Pos (2U)
13859#define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos)
13860#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk
13861#define TIM_CCER_CC1NP_Pos (3U)
13862#define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos)
13863#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk
13864#define TIM_CCER_CC2E_Pos (4U)
13865#define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos)
13866#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk
13867#define TIM_CCER_CC2P_Pos (5U)
13868#define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos)
13869#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk
13870#define TIM_CCER_CC2NE_Pos (6U)
13871#define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos)
13872#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk
13873#define TIM_CCER_CC2NP_Pos (7U)
13874#define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos)
13875#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk
13876#define TIM_CCER_CC3E_Pos (8U)
13877#define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos)
13878#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk
13879#define TIM_CCER_CC3P_Pos (9U)
13880#define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos)
13881#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk
13882#define TIM_CCER_CC3NE_Pos (10U)
13883#define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos)
13884#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk
13885#define TIM_CCER_CC3NP_Pos (11U)
13886#define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos)
13887#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk
13888#define TIM_CCER_CC4E_Pos (12U)
13889#define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos)
13890#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk
13891#define TIM_CCER_CC4P_Pos (13U)
13892#define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos)
13893#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk
13894#define TIM_CCER_CC4NP_Pos (15U)
13895#define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos)
13896#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk
13897
13898/******************* Bit definition for TIM_CNT register ********************/
13899#define TIM_CNT_CNT_Pos (0U)
13900#define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)
13901#define TIM_CNT_CNT TIM_CNT_CNT_Msk
13902
13903/******************* Bit definition for TIM_PSC register ********************/
13904#define TIM_PSC_PSC_Pos (0U)
13905#define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos)
13906#define TIM_PSC_PSC TIM_PSC_PSC_Msk
13907
13908/******************* Bit definition for TIM_ARR register ********************/
13909#define TIM_ARR_ARR_Pos (0U)
13910#define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)
13911#define TIM_ARR_ARR TIM_ARR_ARR_Msk
13912
13913/******************* Bit definition for TIM_RCR register ********************/
13914#define TIM_RCR_REP_Pos (0U)
13915#define TIM_RCR_REP_Msk (0xFFUL << TIM_RCR_REP_Pos)
13916#define TIM_RCR_REP TIM_RCR_REP_Msk
13917
13918/******************* Bit definition for TIM_CCR1 register *******************/
13919#define TIM_CCR1_CCR1_Pos (0U)
13920#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos)
13921#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk
13922
13923/******************* Bit definition for TIM_CCR2 register *******************/
13924#define TIM_CCR2_CCR2_Pos (0U)
13925#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos)
13926#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk
13927
13928/******************* Bit definition for TIM_CCR3 register *******************/
13929#define TIM_CCR3_CCR3_Pos (0U)
13930#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos)
13931#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk
13932
13933/******************* Bit definition for TIM_CCR4 register *******************/
13934#define TIM_CCR4_CCR4_Pos (0U)
13935#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos)
13936#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk
13937
13938/******************* Bit definition for TIM_BDTR register *******************/
13939#define TIM_BDTR_DTG_Pos (0U)
13940#define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos)
13941#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk
13942#define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos)
13943#define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos)
13944#define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos)
13945#define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos)
13946#define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos)
13947#define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos)
13948#define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos)
13949#define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos)
13950
13951#define TIM_BDTR_LOCK_Pos (8U)
13952#define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos)
13953#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk
13954#define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos)
13955#define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos)
13956
13957#define TIM_BDTR_OSSI_Pos (10U)
13958#define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos)
13959#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk
13960#define TIM_BDTR_OSSR_Pos (11U)
13961#define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos)
13962#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk
13963#define TIM_BDTR_BKE_Pos (12U)
13964#define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos)
13965#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk
13966#define TIM_BDTR_BKP_Pos (13U)
13967#define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos)
13968#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk
13969#define TIM_BDTR_AOE_Pos (14U)
13970#define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos)
13971#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk
13972#define TIM_BDTR_MOE_Pos (15U)
13973#define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos)
13974#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk
13975
13976/******************* Bit definition for TIM_DCR register ********************/
13977#define TIM_DCR_DBA_Pos (0U)
13978#define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos)
13979#define TIM_DCR_DBA TIM_DCR_DBA_Msk
13980#define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos)
13981#define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos)
13982#define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos)
13983#define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos)
13984#define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos)
13985
13986#define TIM_DCR_DBL_Pos (8U)
13987#define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos)
13988#define TIM_DCR_DBL TIM_DCR_DBL_Msk
13989#define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos)
13990#define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos)
13991#define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos)
13992#define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos)
13993#define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos)
13994
13995/******************* Bit definition for TIM_DMAR register *******************/
13996#define TIM_DMAR_DMAB_Pos (0U)
13997#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos)
13998#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk
13999
14000/******************* Bit definition for TIM_OR register *********************/
14001#define TIM_OR_TI1_RMP_Pos (0U)
14002#define TIM_OR_TI1_RMP_Msk (0x3UL << TIM_OR_TI1_RMP_Pos)
14003#define TIM_OR_TI1_RMP TIM_OR_TI1_RMP_Msk
14004#define TIM_OR_TI1_RMP_0 (0x1UL << TIM_OR_TI1_RMP_Pos)
14005#define TIM_OR_TI1_RMP_1 (0x2UL << TIM_OR_TI1_RMP_Pos)
14006
14007#define TIM_OR_TI4_RMP_Pos (6U)
14008#define TIM_OR_TI4_RMP_Msk (0x3UL << TIM_OR_TI4_RMP_Pos)
14009#define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk
14010#define TIM_OR_TI4_RMP_0 (0x1UL << TIM_OR_TI4_RMP_Pos)
14011#define TIM_OR_TI4_RMP_1 (0x2UL << TIM_OR_TI4_RMP_Pos)
14012#define TIM_OR_ITR1_RMP_Pos (10U)
14013#define TIM_OR_ITR1_RMP_Msk (0x3UL << TIM_OR_ITR1_RMP_Pos)
14014#define TIM_OR_ITR1_RMP TIM_OR_ITR1_RMP_Msk
14015#define TIM_OR_ITR1_RMP_0 (0x1UL << TIM_OR_ITR1_RMP_Pos)
14016#define TIM_OR_ITR1_RMP_1 (0x2UL << TIM_OR_ITR1_RMP_Pos)
14017
14018
14019/******************************************************************************/
14020/* */
14021/* Universal Synchronous Asynchronous Receiver Transmitter */
14022/* */
14023/******************************************************************************/
14024/******************* Bit definition for USART_SR register *******************/
14025#define USART_SR_PE_Pos (0U)
14026#define USART_SR_PE_Msk (0x1UL << USART_SR_PE_Pos)
14027#define USART_SR_PE USART_SR_PE_Msk
14028#define USART_SR_FE_Pos (1U)
14029#define USART_SR_FE_Msk (0x1UL << USART_SR_FE_Pos)
14030#define USART_SR_FE USART_SR_FE_Msk
14031#define USART_SR_NE_Pos (2U)
14032#define USART_SR_NE_Msk (0x1UL << USART_SR_NE_Pos)
14033#define USART_SR_NE USART_SR_NE_Msk
14034#define USART_SR_ORE_Pos (3U)
14035#define USART_SR_ORE_Msk (0x1UL << USART_SR_ORE_Pos)
14036#define USART_SR_ORE USART_SR_ORE_Msk
14037#define USART_SR_IDLE_Pos (4U)
14038#define USART_SR_IDLE_Msk (0x1UL << USART_SR_IDLE_Pos)
14039#define USART_SR_IDLE USART_SR_IDLE_Msk
14040#define USART_SR_RXNE_Pos (5U)
14041#define USART_SR_RXNE_Msk (0x1UL << USART_SR_RXNE_Pos)
14042#define USART_SR_RXNE USART_SR_RXNE_Msk
14043#define USART_SR_TC_Pos (6U)
14044#define USART_SR_TC_Msk (0x1UL << USART_SR_TC_Pos)
14045#define USART_SR_TC USART_SR_TC_Msk
14046#define USART_SR_TXE_Pos (7U)
14047#define USART_SR_TXE_Msk (0x1UL << USART_SR_TXE_Pos)
14048#define USART_SR_TXE USART_SR_TXE_Msk
14049#define USART_SR_LBD_Pos (8U)
14050#define USART_SR_LBD_Msk (0x1UL << USART_SR_LBD_Pos)
14051#define USART_SR_LBD USART_SR_LBD_Msk
14052#define USART_SR_CTS_Pos (9U)
14053#define USART_SR_CTS_Msk (0x1UL << USART_SR_CTS_Pos)
14054#define USART_SR_CTS USART_SR_CTS_Msk
14055
14056/******************* Bit definition for USART_DR register *******************/
14057#define USART_DR_DR_Pos (0U)
14058#define USART_DR_DR_Msk (0x1FFUL << USART_DR_DR_Pos)
14059#define USART_DR_DR USART_DR_DR_Msk
14060
14061/****************** Bit definition for USART_BRR register *******************/
14062#define USART_BRR_DIV_Fraction_Pos (0U)
14063#define USART_BRR_DIV_Fraction_Msk (0xFUL << USART_BRR_DIV_Fraction_Pos)
14064#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk
14065#define USART_BRR_DIV_Mantissa_Pos (4U)
14066#define USART_BRR_DIV_Mantissa_Msk (0xFFFUL << USART_BRR_DIV_Mantissa_Pos)
14067#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk
14068
14069/****************** Bit definition for USART_CR1 register *******************/
14070#define USART_CR1_SBK_Pos (0U)
14071#define USART_CR1_SBK_Msk (0x1UL << USART_CR1_SBK_Pos)
14072#define USART_CR1_SBK USART_CR1_SBK_Msk
14073#define USART_CR1_RWU_Pos (1U)
14074#define USART_CR1_RWU_Msk (0x1UL << USART_CR1_RWU_Pos)
14075#define USART_CR1_RWU USART_CR1_RWU_Msk
14076#define USART_CR1_RE_Pos (2U)
14077#define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos)
14078#define USART_CR1_RE USART_CR1_RE_Msk
14079#define USART_CR1_TE_Pos (3U)
14080#define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos)
14081#define USART_CR1_TE USART_CR1_TE_Msk
14082#define USART_CR1_IDLEIE_Pos (4U)
14083#define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos)
14084#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk
14085#define USART_CR1_RXNEIE_Pos (5U)
14086#define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos)
14087#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk
14088#define USART_CR1_TCIE_Pos (6U)
14089#define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos)
14090#define USART_CR1_TCIE USART_CR1_TCIE_Msk
14091#define USART_CR1_TXEIE_Pos (7U)
14092#define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos)
14093#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk
14094#define USART_CR1_PEIE_Pos (8U)
14095#define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos)
14096#define USART_CR1_PEIE USART_CR1_PEIE_Msk
14097#define USART_CR1_PS_Pos (9U)
14098#define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos)
14099#define USART_CR1_PS USART_CR1_PS_Msk
14100#define USART_CR1_PCE_Pos (10U)
14101#define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos)
14102#define USART_CR1_PCE USART_CR1_PCE_Msk
14103#define USART_CR1_WAKE_Pos (11U)
14104#define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos)
14105#define USART_CR1_WAKE USART_CR1_WAKE_Msk
14106#define USART_CR1_M_Pos (12U)
14107#define USART_CR1_M_Msk (0x1UL << USART_CR1_M_Pos)
14108#define USART_CR1_M USART_CR1_M_Msk
14109#define USART_CR1_UE_Pos (13U)
14110#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos)
14111#define USART_CR1_UE USART_CR1_UE_Msk
14112#define USART_CR1_OVER8_Pos (15U)
14113#define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos)
14114#define USART_CR1_OVER8 USART_CR1_OVER8_Msk
14115
14116/****************** Bit definition for USART_CR2 register *******************/
14117#define USART_CR2_ADD_Pos (0U)
14118#define USART_CR2_ADD_Msk (0xFUL << USART_CR2_ADD_Pos)
14119#define USART_CR2_ADD USART_CR2_ADD_Msk
14120#define USART_CR2_LBDL_Pos (5U)
14121#define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos)
14122#define USART_CR2_LBDL USART_CR2_LBDL_Msk
14123#define USART_CR2_LBDIE_Pos (6U)
14124#define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos)
14125#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk
14126#define USART_CR2_LBCL_Pos (8U)
14127#define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos)
14128#define USART_CR2_LBCL USART_CR2_LBCL_Msk
14129#define USART_CR2_CPHA_Pos (9U)
14130#define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos)
14131#define USART_CR2_CPHA USART_CR2_CPHA_Msk
14132#define USART_CR2_CPOL_Pos (10U)
14133#define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos)
14134#define USART_CR2_CPOL USART_CR2_CPOL_Msk
14135#define USART_CR2_CLKEN_Pos (11U)
14136#define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos)
14137#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk
14138
14139#define USART_CR2_STOP_Pos (12U)
14140#define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos)
14141#define USART_CR2_STOP USART_CR2_STOP_Msk
14142#define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos)
14143#define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos)
14144
14145#define USART_CR2_LINEN_Pos (14U)
14146#define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos)
14147#define USART_CR2_LINEN USART_CR2_LINEN_Msk
14148
14149/****************** Bit definition for USART_CR3 register *******************/
14150#define USART_CR3_EIE_Pos (0U)
14151#define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos)
14152#define USART_CR3_EIE USART_CR3_EIE_Msk
14153#define USART_CR3_IREN_Pos (1U)
14154#define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos)
14155#define USART_CR3_IREN USART_CR3_IREN_Msk
14156#define USART_CR3_IRLP_Pos (2U)
14157#define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos)
14158#define USART_CR3_IRLP USART_CR3_IRLP_Msk
14159#define USART_CR3_HDSEL_Pos (3U)
14160#define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos)
14161#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk
14162#define USART_CR3_NACK_Pos (4U)
14163#define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos)
14164#define USART_CR3_NACK USART_CR3_NACK_Msk
14165#define USART_CR3_SCEN_Pos (5U)
14166#define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos)
14167#define USART_CR3_SCEN USART_CR3_SCEN_Msk
14168#define USART_CR3_DMAR_Pos (6U)
14169#define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos)
14170#define USART_CR3_DMAR USART_CR3_DMAR_Msk
14171#define USART_CR3_DMAT_Pos (7U)
14172#define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos)
14173#define USART_CR3_DMAT USART_CR3_DMAT_Msk
14174#define USART_CR3_RTSE_Pos (8U)
14175#define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos)
14176#define USART_CR3_RTSE USART_CR3_RTSE_Msk
14177#define USART_CR3_CTSE_Pos (9U)
14178#define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos)
14179#define USART_CR3_CTSE USART_CR3_CTSE_Msk
14180#define USART_CR3_CTSIE_Pos (10U)
14181#define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos)
14182#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk
14183#define USART_CR3_ONEBIT_Pos (11U)
14184#define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos)
14185#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk
14186
14187/****************** Bit definition for USART_GTPR register ******************/
14188#define USART_GTPR_PSC_Pos (0U)
14189#define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos)
14190#define USART_GTPR_PSC USART_GTPR_PSC_Msk
14191#define USART_GTPR_PSC_0 (0x01UL << USART_GTPR_PSC_Pos)
14192#define USART_GTPR_PSC_1 (0x02UL << USART_GTPR_PSC_Pos)
14193#define USART_GTPR_PSC_2 (0x04UL << USART_GTPR_PSC_Pos)
14194#define USART_GTPR_PSC_3 (0x08UL << USART_GTPR_PSC_Pos)
14195#define USART_GTPR_PSC_4 (0x10UL << USART_GTPR_PSC_Pos)
14196#define USART_GTPR_PSC_5 (0x20UL << USART_GTPR_PSC_Pos)
14197#define USART_GTPR_PSC_6 (0x40UL << USART_GTPR_PSC_Pos)
14198#define USART_GTPR_PSC_7 (0x80UL << USART_GTPR_PSC_Pos)
14199
14200#define USART_GTPR_GT_Pos (8U)
14201#define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos)
14202#define USART_GTPR_GT USART_GTPR_GT_Msk
14203
14204/******************************************************************************/
14205/* */
14206/* Window WATCHDOG */
14207/* */
14208/******************************************************************************/
14209/******************* Bit definition for WWDG_CR register ********************/
14210#define WWDG_CR_T_Pos (0U)
14211#define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos)
14212#define WWDG_CR_T WWDG_CR_T_Msk
14213#define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos)
14214#define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos)
14215#define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos)
14216#define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos)
14217#define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos)
14218#define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos)
14219#define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos)
14220/* Legacy defines */
14221#define WWDG_CR_T0 WWDG_CR_T_0
14222#define WWDG_CR_T1 WWDG_CR_T_1
14223#define WWDG_CR_T2 WWDG_CR_T_2
14224#define WWDG_CR_T3 WWDG_CR_T_3
14225#define WWDG_CR_T4 WWDG_CR_T_4
14226#define WWDG_CR_T5 WWDG_CR_T_5
14227#define WWDG_CR_T6 WWDG_CR_T_6
14228
14229#define WWDG_CR_WDGA_Pos (7U)
14230#define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos)
14231#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk
14232
14233/******************* Bit definition for WWDG_CFR register *******************/
14234#define WWDG_CFR_W_Pos (0U)
14235#define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos)
14236#define WWDG_CFR_W WWDG_CFR_W_Msk
14237#define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos)
14238#define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos)
14239#define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos)
14240#define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos)
14241#define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos)
14242#define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos)
14243#define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos)
14244/* Legacy defines */
14245#define WWDG_CFR_W0 WWDG_CFR_W_0
14246#define WWDG_CFR_W1 WWDG_CFR_W_1
14247#define WWDG_CFR_W2 WWDG_CFR_W_2
14248#define WWDG_CFR_W3 WWDG_CFR_W_3
14249#define WWDG_CFR_W4 WWDG_CFR_W_4
14250#define WWDG_CFR_W5 WWDG_CFR_W_5
14251#define WWDG_CFR_W6 WWDG_CFR_W_6
14252
14253#define WWDG_CFR_WDGTB_Pos (7U)
14254#define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos)
14255#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk
14256#define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos)
14257#define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos)
14258/* Legacy defines */
14259#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
14260#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
14261
14262#define WWDG_CFR_EWI_Pos (9U)
14263#define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos)
14264#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk
14265
14266/******************* Bit definition for WWDG_SR register ********************/
14267#define WWDG_SR_EWIF_Pos (0U)
14268#define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos)
14269#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk
14270
14271
14272/******************************************************************************/
14273/* */
14274/* DBG */
14275/* */
14276/******************************************************************************/
14277/******************** Bit definition for DBGMCU_IDCODE register *************/
14278#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
14279#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)
14280#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
14281#define DBGMCU_IDCODE_REV_ID_Pos (16U)
14282#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)
14283#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
14284
14285/******************** Bit definition for DBGMCU_CR register *****************/
14286#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
14287#define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)
14288#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
14289#define DBGMCU_CR_DBG_STOP_Pos (1U)
14290#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos)
14291#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
14292#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
14293#define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)
14294#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
14295#define DBGMCU_CR_TRACE_IOEN_Pos (5U)
14296#define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos)
14297#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
14298
14299#define DBGMCU_CR_TRACE_MODE_Pos (6U)
14300#define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos)
14301#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
14302#define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos)
14303#define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos)
14304
14305/******************** Bit definition for DBGMCU_APB1_FZ register ************/
14306#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
14307#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos)
14308#define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
14309#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
14310#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos)
14311#define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
14312#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)
14313#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos)
14314#define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
14315#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U)
14316#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos)
14317#define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
14318#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
14319#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos)
14320#define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
14321#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)
14322#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos)
14323#define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
14324#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos (6U)
14325#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos)
14326#define DBGMCU_APB1_FZ_DBG_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk
14327#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos (7U)
14328#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos)
14329#define DBGMCU_APB1_FZ_DBG_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk
14330#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U)
14331#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos)
14332#define DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk
14333#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
14334#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos)
14335#define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
14336#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
14337#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos)
14338#define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
14339#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
14340#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos)
14341#define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
14342#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
14343#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos)
14344#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
14345#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
14346#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos)
14347#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
14348#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (23U)
14349#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos)
14350#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk
14351#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos (25U)
14352#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos)
14353#define DBGMCU_APB1_FZ_DBG_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk
14354#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos (26U)
14355#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos)
14356#define DBGMCU_APB1_FZ_DBG_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk
14357/* Old IWDGSTOP bit definition, maintained for legacy purpose */
14358#define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
14359
14360/******************** Bit definition for DBGMCU_APB2_FZ register ************/
14361#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)
14362#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos)
14363#define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
14364#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos (1U)
14365#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos)
14366#define DBGMCU_APB2_FZ_DBG_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk
14367#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (16U)
14368#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos)
14369#define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
14370#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (17U)
14371#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos)
14372#define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk
14373#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (18U)
14374#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos)
14375#define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
14376
14377/******************************************************************************/
14378/* */
14379/* Ethernet MAC Registers bits definitions */
14380/* */
14381/******************************************************************************/
14382/* Bit definition for Ethernet MAC Control Register register */
14383#define ETH_MACCR_CSTF_Pos (25U)
14384#define ETH_MACCR_CSTF_Msk (0x1UL << ETH_MACCR_CSTF_Pos)
14385#define ETH_MACCR_CSTF ETH_MACCR_CSTF_Msk /* CRC stripping for Type frames */
14386#define ETH_MACCR_WD_Pos (23U)
14387#define ETH_MACCR_WD_Msk (0x1UL << ETH_MACCR_WD_Pos)
14388#define ETH_MACCR_WD ETH_MACCR_WD_Msk /* Watchdog disable */
14389#define ETH_MACCR_JD_Pos (22U)
14390#define ETH_MACCR_JD_Msk (0x1UL << ETH_MACCR_JD_Pos)
14391#define ETH_MACCR_JD ETH_MACCR_JD_Msk /* Jabber disable */
14392#define ETH_MACCR_IFG_Pos (17U)
14393#define ETH_MACCR_IFG_Msk (0x7UL << ETH_MACCR_IFG_Pos)
14394#define ETH_MACCR_IFG ETH_MACCR_IFG_Msk /* Inter-frame gap */
14395#define ETH_MACCR_IFG_96Bit 0x00000000U /* Minimum IFG between frames during transmission is 96Bit */
14396#define ETH_MACCR_IFG_88Bit 0x00020000U /* Minimum IFG between frames during transmission is 88Bit */
14397#define ETH_MACCR_IFG_80Bit 0x00040000U /* Minimum IFG between frames during transmission is 80Bit */
14398#define ETH_MACCR_IFG_72Bit 0x00060000U /* Minimum IFG between frames during transmission is 72Bit */
14399#define ETH_MACCR_IFG_64Bit 0x00080000U /* Minimum IFG between frames during transmission is 64Bit */
14400#define ETH_MACCR_IFG_56Bit 0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */
14401#define ETH_MACCR_IFG_48Bit 0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */
14402#define ETH_MACCR_IFG_40Bit 0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */
14403#define ETH_MACCR_CSD_Pos (16U)
14404#define ETH_MACCR_CSD_Msk (0x1UL << ETH_MACCR_CSD_Pos)
14405#define ETH_MACCR_CSD ETH_MACCR_CSD_Msk /* Carrier sense disable (during transmission) */
14406#define ETH_MACCR_FES_Pos (14U)
14407#define ETH_MACCR_FES_Msk (0x1UL << ETH_MACCR_FES_Pos)
14408#define ETH_MACCR_FES ETH_MACCR_FES_Msk /* Fast ethernet speed */
14409#define ETH_MACCR_ROD_Pos (13U)
14410#define ETH_MACCR_ROD_Msk (0x1UL << ETH_MACCR_ROD_Pos)
14411#define ETH_MACCR_ROD ETH_MACCR_ROD_Msk /* Receive own disable */
14412#define ETH_MACCR_LM_Pos (12U)
14413#define ETH_MACCR_LM_Msk (0x1UL << ETH_MACCR_LM_Pos)
14414#define ETH_MACCR_LM ETH_MACCR_LM_Msk /* loopback mode */
14415#define ETH_MACCR_DM_Pos (11U)
14416#define ETH_MACCR_DM_Msk (0x1UL << ETH_MACCR_DM_Pos)
14417#define ETH_MACCR_DM ETH_MACCR_DM_Msk /* Duplex mode */
14418#define ETH_MACCR_IPCO_Pos (10U)
14419#define ETH_MACCR_IPCO_Msk (0x1UL << ETH_MACCR_IPCO_Pos)
14420#define ETH_MACCR_IPCO ETH_MACCR_IPCO_Msk /* IP Checksum offload */
14421#define ETH_MACCR_RD_Pos (9U)
14422#define ETH_MACCR_RD_Msk (0x1UL << ETH_MACCR_RD_Pos)
14423#define ETH_MACCR_RD ETH_MACCR_RD_Msk /* Retry disable */
14424#define ETH_MACCR_APCS_Pos (7U)
14425#define ETH_MACCR_APCS_Msk (0x1UL << ETH_MACCR_APCS_Pos)
14426#define ETH_MACCR_APCS ETH_MACCR_APCS_Msk /* Automatic Pad/CRC stripping */
14427#define ETH_MACCR_BL_Pos (5U)
14428#define ETH_MACCR_BL_Msk (0x3UL << ETH_MACCR_BL_Pos)
14429#define ETH_MACCR_BL ETH_MACCR_BL_Msk /* Back-off limit: random integer number (r) of slot time delays before rescheduling
14430 a transmission attempt during retries after a collision: 0 =< r <2^k */
14431#define ETH_MACCR_BL_10 0x00000000U /* k = min (n, 10) */
14432#define ETH_MACCR_BL_8 0x00000020U /* k = min (n, 8) */
14433#define ETH_MACCR_BL_4 0x00000040U /* k = min (n, 4) */
14434#define ETH_MACCR_BL_1 0x00000060U /* k = min (n, 1) */
14435#define ETH_MACCR_DC_Pos (4U)
14436#define ETH_MACCR_DC_Msk (0x1UL << ETH_MACCR_DC_Pos)
14437#define ETH_MACCR_DC ETH_MACCR_DC_Msk /* Defferal check */
14438#define ETH_MACCR_TE_Pos (3U)
14439#define ETH_MACCR_TE_Msk (0x1UL << ETH_MACCR_TE_Pos)
14440#define ETH_MACCR_TE ETH_MACCR_TE_Msk /* Transmitter enable */
14441#define ETH_MACCR_RE_Pos (2U)
14442#define ETH_MACCR_RE_Msk (0x1UL << ETH_MACCR_RE_Pos)
14443#define ETH_MACCR_RE ETH_MACCR_RE_Msk /* Receiver enable */
14444
14445/* Bit definition for Ethernet MAC Frame Filter Register */
14446#define ETH_MACFFR_RA_Pos (31U)
14447#define ETH_MACFFR_RA_Msk (0x1UL << ETH_MACFFR_RA_Pos)
14448#define ETH_MACFFR_RA ETH_MACFFR_RA_Msk /* Receive all */
14449#define ETH_MACFFR_HPF_Pos (10U)
14450#define ETH_MACFFR_HPF_Msk (0x1UL << ETH_MACFFR_HPF_Pos)
14451#define ETH_MACFFR_HPF ETH_MACFFR_HPF_Msk /* Hash or perfect filter */
14452#define ETH_MACFFR_SAF_Pos (9U)
14453#define ETH_MACFFR_SAF_Msk (0x1UL << ETH_MACFFR_SAF_Pos)
14454#define ETH_MACFFR_SAF ETH_MACFFR_SAF_Msk /* Source address filter enable */
14455#define ETH_MACFFR_SAIF_Pos (8U)
14456#define ETH_MACFFR_SAIF_Msk (0x1UL << ETH_MACFFR_SAIF_Pos)
14457#define ETH_MACFFR_SAIF ETH_MACFFR_SAIF_Msk /* SA inverse filtering */
14458#define ETH_MACFFR_PCF_Pos (6U)
14459#define ETH_MACFFR_PCF_Msk (0x3UL << ETH_MACFFR_PCF_Pos)
14460#define ETH_MACFFR_PCF ETH_MACFFR_PCF_Msk /* Pass control frames: 3 cases */
14461#define ETH_MACFFR_PCF_BlockAll_Pos (6U)
14462#define ETH_MACFFR_PCF_BlockAll_Msk (0x1UL << ETH_MACFFR_PCF_BlockAll_Pos)
14463#define ETH_MACFFR_PCF_BlockAll ETH_MACFFR_PCF_BlockAll_Msk /* MAC filters all control frames from reaching the application */
14464#define ETH_MACFFR_PCF_ForwardAll_Pos (7U)
14465#define ETH_MACFFR_PCF_ForwardAll_Msk (0x1UL << ETH_MACFFR_PCF_ForwardAll_Pos)
14466#define ETH_MACFFR_PCF_ForwardAll ETH_MACFFR_PCF_ForwardAll_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */
14467#define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos (6U)
14468#define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk (0x3UL << ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos)
14469#define ETH_MACFFR_PCF_ForwardPassedAddrFilter ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk /* MAC forwards control frames that pass the Address Filter. */
14470#define ETH_MACFFR_BFD_Pos (5U)
14471#define ETH_MACFFR_BFD_Msk (0x1UL << ETH_MACFFR_BFD_Pos)
14472#define ETH_MACFFR_BFD ETH_MACFFR_BFD_Msk /* Broadcast frame disable */
14473#define ETH_MACFFR_PAM_Pos (4U)
14474#define ETH_MACFFR_PAM_Msk (0x1UL << ETH_MACFFR_PAM_Pos)
14475#define ETH_MACFFR_PAM ETH_MACFFR_PAM_Msk /* Pass all mutlicast */
14476#define ETH_MACFFR_DAIF_Pos (3U)
14477#define ETH_MACFFR_DAIF_Msk (0x1UL << ETH_MACFFR_DAIF_Pos)
14478#define ETH_MACFFR_DAIF ETH_MACFFR_DAIF_Msk /* DA Inverse filtering */
14479#define ETH_MACFFR_HM_Pos (2U)
14480#define ETH_MACFFR_HM_Msk (0x1UL << ETH_MACFFR_HM_Pos)
14481#define ETH_MACFFR_HM ETH_MACFFR_HM_Msk /* Hash multicast */
14482#define ETH_MACFFR_HU_Pos (1U)
14483#define ETH_MACFFR_HU_Msk (0x1UL << ETH_MACFFR_HU_Pos)
14484#define ETH_MACFFR_HU ETH_MACFFR_HU_Msk /* Hash unicast */
14485#define ETH_MACFFR_PM_Pos (0U)
14486#define ETH_MACFFR_PM_Msk (0x1UL << ETH_MACFFR_PM_Pos)
14487#define ETH_MACFFR_PM ETH_MACFFR_PM_Msk /* Promiscuous mode */
14488
14489/* Bit definition for Ethernet MAC Hash Table High Register */
14490#define ETH_MACHTHR_HTH_Pos (0U)
14491#define ETH_MACHTHR_HTH_Msk (0xFFFFFFFFUL << ETH_MACHTHR_HTH_Pos)
14492#define ETH_MACHTHR_HTH ETH_MACHTHR_HTH_Msk /* Hash table high */
14493
14494/* Bit definition for Ethernet MAC Hash Table Low Register */
14495#define ETH_MACHTLR_HTL_Pos (0U)
14496#define ETH_MACHTLR_HTL_Msk (0xFFFFFFFFUL << ETH_MACHTLR_HTL_Pos)
14497#define ETH_MACHTLR_HTL ETH_MACHTLR_HTL_Msk /* Hash table low */
14498
14499/* Bit definition for Ethernet MAC MII Address Register */
14500#define ETH_MACMIIAR_PA_Pos (11U)
14501#define ETH_MACMIIAR_PA_Msk (0x1FUL << ETH_MACMIIAR_PA_Pos)
14502#define ETH_MACMIIAR_PA ETH_MACMIIAR_PA_Msk /* Physical layer address */
14503#define ETH_MACMIIAR_MR_Pos (6U)
14504#define ETH_MACMIIAR_MR_Msk (0x1FUL << ETH_MACMIIAR_MR_Pos)
14505#define ETH_MACMIIAR_MR ETH_MACMIIAR_MR_Msk /* MII register in the selected PHY */
14506#define ETH_MACMIIAR_CR_Pos (2U)
14507#define ETH_MACMIIAR_CR_Msk (0x7UL << ETH_MACMIIAR_CR_Pos)
14508#define ETH_MACMIIAR_CR ETH_MACMIIAR_CR_Msk /* CR clock range: 6 cases */
14509#define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
14510#define ETH_MACMIIAR_CR_Div62_Pos (2U)
14511#define ETH_MACMIIAR_CR_Div62_Msk (0x1UL << ETH_MACMIIAR_CR_Div62_Pos)
14512#define ETH_MACMIIAR_CR_Div62 ETH_MACMIIAR_CR_Div62_Msk /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
14513#define ETH_MACMIIAR_CR_Div16_Pos (3U)
14514#define ETH_MACMIIAR_CR_Div16_Msk (0x1UL << ETH_MACMIIAR_CR_Div16_Pos)
14515#define ETH_MACMIIAR_CR_Div16 ETH_MACMIIAR_CR_Div16_Msk /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
14516#define ETH_MACMIIAR_CR_Div26_Pos (2U)
14517#define ETH_MACMIIAR_CR_Div26_Msk (0x3UL << ETH_MACMIIAR_CR_Div26_Pos)
14518#define ETH_MACMIIAR_CR_Div26 ETH_MACMIIAR_CR_Div26_Msk /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
14519#define ETH_MACMIIAR_CR_Div102_Pos (4U)
14520#define ETH_MACMIIAR_CR_Div102_Msk (0x1UL << ETH_MACMIIAR_CR_Div102_Pos)
14521#define ETH_MACMIIAR_CR_Div102 ETH_MACMIIAR_CR_Div102_Msk /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
14522#define ETH_MACMIIAR_MW_Pos (1U)
14523#define ETH_MACMIIAR_MW_Msk (0x1UL << ETH_MACMIIAR_MW_Pos)
14524#define ETH_MACMIIAR_MW ETH_MACMIIAR_MW_Msk /* MII write */
14525#define ETH_MACMIIAR_MB_Pos (0U)
14526#define ETH_MACMIIAR_MB_Msk (0x1UL << ETH_MACMIIAR_MB_Pos)
14527#define ETH_MACMIIAR_MB ETH_MACMIIAR_MB_Msk /* MII busy */
14528
14529/* Bit definition for Ethernet MAC MII Data Register */
14530#define ETH_MACMIIDR_MD_Pos (0U)
14531#define ETH_MACMIIDR_MD_Msk (0xFFFFUL << ETH_MACMIIDR_MD_Pos)
14532#define ETH_MACMIIDR_MD ETH_MACMIIDR_MD_Msk /* MII data: read/write data from/to PHY */
14533
14534/* Bit definition for Ethernet MAC Flow Control Register */
14535#define ETH_MACFCR_PT_Pos (16U)
14536#define ETH_MACFCR_PT_Msk (0xFFFFUL << ETH_MACFCR_PT_Pos)
14537#define ETH_MACFCR_PT ETH_MACFCR_PT_Msk /* Pause time */
14538#define ETH_MACFCR_ZQPD_Pos (7U)
14539#define ETH_MACFCR_ZQPD_Msk (0x1UL << ETH_MACFCR_ZQPD_Pos)
14540#define ETH_MACFCR_ZQPD ETH_MACFCR_ZQPD_Msk /* Zero-quanta pause disable */
14541#define ETH_MACFCR_PLT_Pos (4U)
14542#define ETH_MACFCR_PLT_Msk (0x3UL << ETH_MACFCR_PLT_Pos)
14543#define ETH_MACFCR_PLT ETH_MACFCR_PLT_Msk /* Pause low threshold: 4 cases */
14544#define ETH_MACFCR_PLT_Minus4 0x00000000U /* Pause time minus 4 slot times */
14545#define ETH_MACFCR_PLT_Minus28_Pos (4U)
14546#define ETH_MACFCR_PLT_Minus28_Msk (0x1UL << ETH_MACFCR_PLT_Minus28_Pos)
14547#define ETH_MACFCR_PLT_Minus28 ETH_MACFCR_PLT_Minus28_Msk /* Pause time minus 28 slot times */
14548#define ETH_MACFCR_PLT_Minus144_Pos (5U)
14549#define ETH_MACFCR_PLT_Minus144_Msk (0x1UL << ETH_MACFCR_PLT_Minus144_Pos)
14550#define ETH_MACFCR_PLT_Minus144 ETH_MACFCR_PLT_Minus144_Msk /* Pause time minus 144 slot times */
14551#define ETH_MACFCR_PLT_Minus256_Pos (4U)
14552#define ETH_MACFCR_PLT_Minus256_Msk (0x3UL << ETH_MACFCR_PLT_Minus256_Pos)
14553#define ETH_MACFCR_PLT_Minus256 ETH_MACFCR_PLT_Minus256_Msk /* Pause time minus 256 slot times */
14554#define ETH_MACFCR_UPFD_Pos (3U)
14555#define ETH_MACFCR_UPFD_Msk (0x1UL << ETH_MACFCR_UPFD_Pos)
14556#define ETH_MACFCR_UPFD ETH_MACFCR_UPFD_Msk /* Unicast pause frame detect */
14557#define ETH_MACFCR_RFCE_Pos (2U)
14558#define ETH_MACFCR_RFCE_Msk (0x1UL << ETH_MACFCR_RFCE_Pos)
14559#define ETH_MACFCR_RFCE ETH_MACFCR_RFCE_Msk /* Receive flow control enable */
14560#define ETH_MACFCR_TFCE_Pos (1U)
14561#define ETH_MACFCR_TFCE_Msk (0x1UL << ETH_MACFCR_TFCE_Pos)
14562#define ETH_MACFCR_TFCE ETH_MACFCR_TFCE_Msk /* Transmit flow control enable */
14563#define ETH_MACFCR_FCBBPA_Pos (0U)
14564#define ETH_MACFCR_FCBBPA_Msk (0x1UL << ETH_MACFCR_FCBBPA_Pos)
14565#define ETH_MACFCR_FCBBPA ETH_MACFCR_FCBBPA_Msk /* Flow control busy/backpressure activate */
14566
14567/* Bit definition for Ethernet MAC VLAN Tag Register */
14568#define ETH_MACVLANTR_VLANTC_Pos (16U)
14569#define ETH_MACVLANTR_VLANTC_Msk (0x1UL << ETH_MACVLANTR_VLANTC_Pos)
14570#define ETH_MACVLANTR_VLANTC ETH_MACVLANTR_VLANTC_Msk /* 12-bit VLAN tag comparison */
14571#define ETH_MACVLANTR_VLANTI_Pos (0U)
14572#define ETH_MACVLANTR_VLANTI_Msk (0xFFFFUL << ETH_MACVLANTR_VLANTI_Pos)
14573#define ETH_MACVLANTR_VLANTI ETH_MACVLANTR_VLANTI_Msk /* VLAN tag identifier (for receive frames) */
14574
14575/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
14576#define ETH_MACRWUFFR_D_Pos (0U)
14577#define ETH_MACRWUFFR_D_Msk (0xFFFFFFFFUL << ETH_MACRWUFFR_D_Pos)
14578#define ETH_MACRWUFFR_D ETH_MACRWUFFR_D_Msk /* Wake-up frame filter register data */
14579/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
14580 Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
14581/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
14582 Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
14583 Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
14584 Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
14585 Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
14586 RSVD - Filter1 Command - RSVD - Filter0 Command
14587 Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
14588 Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
14589 Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
14590
14591/* Bit definition for Ethernet MAC PMT Control and Status Register */
14592#define ETH_MACPMTCSR_WFFRPR_Pos (31U)
14593#define ETH_MACPMTCSR_WFFRPR_Msk (0x1UL << ETH_MACPMTCSR_WFFRPR_Pos)
14594#define ETH_MACPMTCSR_WFFRPR ETH_MACPMTCSR_WFFRPR_Msk /* Wake-Up Frame Filter Register Pointer Reset */
14595#define ETH_MACPMTCSR_GU_Pos (9U)
14596#define ETH_MACPMTCSR_GU_Msk (0x1UL << ETH_MACPMTCSR_GU_Pos)
14597#define ETH_MACPMTCSR_GU ETH_MACPMTCSR_GU_Msk /* Global Unicast */
14598#define ETH_MACPMTCSR_WFR_Pos (6U)
14599#define ETH_MACPMTCSR_WFR_Msk (0x1UL << ETH_MACPMTCSR_WFR_Pos)
14600#define ETH_MACPMTCSR_WFR ETH_MACPMTCSR_WFR_Msk /* Wake-Up Frame Received */
14601#define ETH_MACPMTCSR_MPR_Pos (5U)
14602#define ETH_MACPMTCSR_MPR_Msk (0x1UL << ETH_MACPMTCSR_MPR_Pos)
14603#define ETH_MACPMTCSR_MPR ETH_MACPMTCSR_MPR_Msk /* Magic Packet Received */
14604#define ETH_MACPMTCSR_WFE_Pos (2U)
14605#define ETH_MACPMTCSR_WFE_Msk (0x1UL << ETH_MACPMTCSR_WFE_Pos)
14606#define ETH_MACPMTCSR_WFE ETH_MACPMTCSR_WFE_Msk /* Wake-Up Frame Enable */
14607#define ETH_MACPMTCSR_MPE_Pos (1U)
14608#define ETH_MACPMTCSR_MPE_Msk (0x1UL << ETH_MACPMTCSR_MPE_Pos)
14609#define ETH_MACPMTCSR_MPE ETH_MACPMTCSR_MPE_Msk /* Magic Packet Enable */
14610#define ETH_MACPMTCSR_PD_Pos (0U)
14611#define ETH_MACPMTCSR_PD_Msk (0x1UL << ETH_MACPMTCSR_PD_Pos)
14612#define ETH_MACPMTCSR_PD ETH_MACPMTCSR_PD_Msk /* Power Down */
14613
14614/* Bit definition for Ethernet MAC debug Register */
14615#define ETH_MACDBGR_TFF_Pos (25U)
14616#define ETH_MACDBGR_TFF_Msk (0x1UL << ETH_MACDBGR_TFF_Pos)
14617#define ETH_MACDBGR_TFF ETH_MACDBGR_TFF_Msk /* Tx FIFO full */
14618#define ETH_MACDBGR_TFNE_Pos (24U)
14619#define ETH_MACDBGR_TFNE_Msk (0x1UL << ETH_MACDBGR_TFNE_Pos)
14620#define ETH_MACDBGR_TFNE ETH_MACDBGR_TFNE_Msk /* Tx FIFO not empty */
14621#define ETH_MACDBGR_TFWA_Pos (22U)
14622#define ETH_MACDBGR_TFWA_Msk (0x1UL << ETH_MACDBGR_TFWA_Pos)
14623#define ETH_MACDBGR_TFWA ETH_MACDBGR_TFWA_Msk /* Tx FIFO write active */
14624#define ETH_MACDBGR_TFRS_Pos (20U)
14625#define ETH_MACDBGR_TFRS_Msk (0x3UL << ETH_MACDBGR_TFRS_Pos)
14626#define ETH_MACDBGR_TFRS ETH_MACDBGR_TFRS_Msk /* Tx FIFO read status mask */
14627#define ETH_MACDBGR_TFRS_WRITING_Pos (20U)
14628#define ETH_MACDBGR_TFRS_WRITING_Msk (0x3UL << ETH_MACDBGR_TFRS_WRITING_Pos)
14629#define ETH_MACDBGR_TFRS_WRITING ETH_MACDBGR_TFRS_WRITING_Msk /* Writing the received TxStatus or flushing the TxFIFO */
14630#define ETH_MACDBGR_TFRS_WAITING_Pos (21U)
14631#define ETH_MACDBGR_TFRS_WAITING_Msk (0x1UL << ETH_MACDBGR_TFRS_WAITING_Pos)
14632#define ETH_MACDBGR_TFRS_WAITING ETH_MACDBGR_TFRS_WAITING_Msk /* Waiting for TxStatus from MAC transmitter */
14633#define ETH_MACDBGR_TFRS_READ_Pos (20U)
14634#define ETH_MACDBGR_TFRS_READ_Msk (0x1UL << ETH_MACDBGR_TFRS_READ_Pos)
14635#define ETH_MACDBGR_TFRS_READ ETH_MACDBGR_TFRS_READ_Msk /* Read state (transferring data to the MAC transmitter) */
14636#define ETH_MACDBGR_TFRS_IDLE 0x00000000U /* Idle state */
14637#define ETH_MACDBGR_MTP_Pos (19U)
14638#define ETH_MACDBGR_MTP_Msk (0x1UL << ETH_MACDBGR_MTP_Pos)
14639#define ETH_MACDBGR_MTP ETH_MACDBGR_MTP_Msk /* MAC transmitter in pause */
14640#define ETH_MACDBGR_MTFCS_Pos (17U)
14641#define ETH_MACDBGR_MTFCS_Msk (0x3UL << ETH_MACDBGR_MTFCS_Pos)
14642#define ETH_MACDBGR_MTFCS ETH_MACDBGR_MTFCS_Msk /* MAC transmit frame controller status mask */
14643#define ETH_MACDBGR_MTFCS_TRANSFERRING_Pos (17U)
14644#define ETH_MACDBGR_MTFCS_TRANSFERRING_Msk (0x3UL << ETH_MACDBGR_MTFCS_TRANSFERRING_Pos)
14645#define ETH_MACDBGR_MTFCS_TRANSFERRING ETH_MACDBGR_MTFCS_TRANSFERRING_Msk /* Transferring input frame for transmission */
14646#define ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos (18U)
14647#define ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk (0x1UL << ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos)
14648#define ETH_MACDBGR_MTFCS_GENERATINGPCF ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk /* Generating and transmitting a Pause control frame (in full duplex mode) */
14649#define ETH_MACDBGR_MTFCS_WAITING_Pos (17U)
14650#define ETH_MACDBGR_MTFCS_WAITING_Msk (0x1UL << ETH_MACDBGR_MTFCS_WAITING_Pos)
14651#define ETH_MACDBGR_MTFCS_WAITING ETH_MACDBGR_MTFCS_WAITING_Msk /* Waiting for Status of previous frame or IFG/backoff period to be over */
14652#define ETH_MACDBGR_MTFCS_IDLE 0x00000000U /* Idle */
14653#define ETH_MACDBGR_MMTEA_Pos (16U)
14654#define ETH_MACDBGR_MMTEA_Msk (0x1UL << ETH_MACDBGR_MMTEA_Pos)
14655#define ETH_MACDBGR_MMTEA ETH_MACDBGR_MMTEA_Msk /* MAC MII transmit engine active */
14656#define ETH_MACDBGR_RFFL_Pos (8U)
14657#define ETH_MACDBGR_RFFL_Msk (0x3UL << ETH_MACDBGR_RFFL_Pos)
14658#define ETH_MACDBGR_RFFL ETH_MACDBGR_RFFL_Msk /* Rx FIFO fill level mask */
14659#define ETH_MACDBGR_RFFL_FULL_Pos (8U)
14660#define ETH_MACDBGR_RFFL_FULL_Msk (0x3UL << ETH_MACDBGR_RFFL_FULL_Pos)
14661#define ETH_MACDBGR_RFFL_FULL ETH_MACDBGR_RFFL_FULL_Msk /* RxFIFO full */
14662#define ETH_MACDBGR_RFFL_ABOVEFCT_Pos (9U)
14663#define ETH_MACDBGR_RFFL_ABOVEFCT_Msk (0x1UL << ETH_MACDBGR_RFFL_ABOVEFCT_Pos)
14664#define ETH_MACDBGR_RFFL_ABOVEFCT ETH_MACDBGR_RFFL_ABOVEFCT_Msk /* RxFIFO fill-level above flow-control activate threshold */
14665#define ETH_MACDBGR_RFFL_BELOWFCT_Pos (8U)
14666#define ETH_MACDBGR_RFFL_BELOWFCT_Msk (0x1UL << ETH_MACDBGR_RFFL_BELOWFCT_Pos)
14667#define ETH_MACDBGR_RFFL_BELOWFCT ETH_MACDBGR_RFFL_BELOWFCT_Msk /* RxFIFO fill-level below flow-control de-activate threshold */
14668#define ETH_MACDBGR_RFFL_EMPTY 0x00000000U /* RxFIFO empty */
14669#define ETH_MACDBGR_RFRCS_Pos (5U)
14670#define ETH_MACDBGR_RFRCS_Msk (0x3UL << ETH_MACDBGR_RFRCS_Pos)
14671#define ETH_MACDBGR_RFRCS ETH_MACDBGR_RFRCS_Msk /* Rx FIFO read controller status mask */
14672#define ETH_MACDBGR_RFRCS_FLUSHING_Pos (5U)
14673#define ETH_MACDBGR_RFRCS_FLUSHING_Msk (0x3UL << ETH_MACDBGR_RFRCS_FLUSHING_Pos)
14674#define ETH_MACDBGR_RFRCS_FLUSHING ETH_MACDBGR_RFRCS_FLUSHING_Msk /* Flushing the frame data and status */
14675#define ETH_MACDBGR_RFRCS_STATUSREADING_Pos (6U)
14676#define ETH_MACDBGR_RFRCS_STATUSREADING_Msk (0x1UL << ETH_MACDBGR_RFRCS_STATUSREADING_Pos)
14677#define ETH_MACDBGR_RFRCS_STATUSREADING ETH_MACDBGR_RFRCS_STATUSREADING_Msk /* Reading frame status (or time-stamp) */
14678#define ETH_MACDBGR_RFRCS_DATAREADING_Pos (5U)
14679#define ETH_MACDBGR_RFRCS_DATAREADING_Msk (0x1UL << ETH_MACDBGR_RFRCS_DATAREADING_Pos)
14680#define ETH_MACDBGR_RFRCS_DATAREADING ETH_MACDBGR_RFRCS_DATAREADING_Msk /* Reading frame data */
14681#define ETH_MACDBGR_RFRCS_IDLE 0x00000000U /* IDLE state */
14682#define ETH_MACDBGR_RFWRA_Pos (4U)
14683#define ETH_MACDBGR_RFWRA_Msk (0x1UL << ETH_MACDBGR_RFWRA_Pos)
14684#define ETH_MACDBGR_RFWRA ETH_MACDBGR_RFWRA_Msk /* Rx FIFO write controller active */
14685#define ETH_MACDBGR_MSFRWCS_Pos (1U)
14686#define ETH_MACDBGR_MSFRWCS_Msk (0x3UL << ETH_MACDBGR_MSFRWCS_Pos)
14687#define ETH_MACDBGR_MSFRWCS ETH_MACDBGR_MSFRWCS_Msk /* MAC small FIFO read / write controllers status mask */
14688#define ETH_MACDBGR_MSFRWCS_1 (0x2UL << ETH_MACDBGR_MSFRWCS_Pos)
14689#define ETH_MACDBGR_MSFRWCS_0 (0x1UL << ETH_MACDBGR_MSFRWCS_Pos)
14690#define ETH_MACDBGR_MMRPEA_Pos (0U)
14691#define ETH_MACDBGR_MMRPEA_Msk (0x1UL << ETH_MACDBGR_MMRPEA_Pos)
14692#define ETH_MACDBGR_MMRPEA ETH_MACDBGR_MMRPEA_Msk /* MAC MII receive protocol engine active */
14693
14694/* Bit definition for Ethernet MAC Status Register */
14695#define ETH_MACSR_TSTS_Pos (9U)
14696#define ETH_MACSR_TSTS_Msk (0x1UL << ETH_MACSR_TSTS_Pos)
14697#define ETH_MACSR_TSTS ETH_MACSR_TSTS_Msk /* Time stamp trigger status */
14698#define ETH_MACSR_MMCTS_Pos (6U)
14699#define ETH_MACSR_MMCTS_Msk (0x1UL << ETH_MACSR_MMCTS_Pos)
14700#define ETH_MACSR_MMCTS ETH_MACSR_MMCTS_Msk /* MMC transmit status */
14701#define ETH_MACSR_MMMCRS_Pos (5U)
14702#define ETH_MACSR_MMMCRS_Msk (0x1UL << ETH_MACSR_MMMCRS_Pos)
14703#define ETH_MACSR_MMMCRS ETH_MACSR_MMMCRS_Msk /* MMC receive status */
14704#define ETH_MACSR_MMCS_Pos (4U)
14705#define ETH_MACSR_MMCS_Msk (0x1UL << ETH_MACSR_MMCS_Pos)
14706#define ETH_MACSR_MMCS ETH_MACSR_MMCS_Msk /* MMC status */
14707#define ETH_MACSR_PMTS_Pos (3U)
14708#define ETH_MACSR_PMTS_Msk (0x1UL << ETH_MACSR_PMTS_Pos)
14709#define ETH_MACSR_PMTS ETH_MACSR_PMTS_Msk /* PMT status */
14710
14711/* Bit definition for Ethernet MAC Interrupt Mask Register */
14712#define ETH_MACIMR_TSTIM_Pos (9U)
14713#define ETH_MACIMR_TSTIM_Msk (0x1UL << ETH_MACIMR_TSTIM_Pos)
14714#define ETH_MACIMR_TSTIM ETH_MACIMR_TSTIM_Msk /* Time stamp trigger interrupt mask */
14715#define ETH_MACIMR_PMTIM_Pos (3U)
14716#define ETH_MACIMR_PMTIM_Msk (0x1UL << ETH_MACIMR_PMTIM_Pos)
14717#define ETH_MACIMR_PMTIM ETH_MACIMR_PMTIM_Msk /* PMT interrupt mask */
14718
14719/* Bit definition for Ethernet MAC Address0 High Register */
14720#define ETH_MACA0HR_MACA0H_Pos (0U)
14721#define ETH_MACA0HR_MACA0H_Msk (0xFFFFUL << ETH_MACA0HR_MACA0H_Pos)
14722#define ETH_MACA0HR_MACA0H ETH_MACA0HR_MACA0H_Msk /* MAC address0 high */
14723
14724/* Bit definition for Ethernet MAC Address0 Low Register */
14725#define ETH_MACA0LR_MACA0L_Pos (0U)
14726#define ETH_MACA0LR_MACA0L_Msk (0xFFFFFFFFUL << ETH_MACA0LR_MACA0L_Pos)
14727#define ETH_MACA0LR_MACA0L ETH_MACA0LR_MACA0L_Msk /* MAC address0 low */
14728
14729/* Bit definition for Ethernet MAC Address1 High Register */
14730#define ETH_MACA1HR_AE_Pos (31U)
14731#define ETH_MACA1HR_AE_Msk (0x1UL << ETH_MACA1HR_AE_Pos)
14732#define ETH_MACA1HR_AE ETH_MACA1HR_AE_Msk /* Address enable */
14733#define ETH_MACA1HR_SA_Pos (30U)
14734#define ETH_MACA1HR_SA_Msk (0x1UL << ETH_MACA1HR_SA_Pos)
14735#define ETH_MACA1HR_SA ETH_MACA1HR_SA_Msk /* Source address */
14736#define ETH_MACA1HR_MBC_Pos (24U)
14737#define ETH_MACA1HR_MBC_Msk (0x3FUL << ETH_MACA1HR_MBC_Pos)
14738#define ETH_MACA1HR_MBC ETH_MACA1HR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
14739#define ETH_MACA1HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
14740#define ETH_MACA1HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
14741#define ETH_MACA1HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
14742#define ETH_MACA1HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
14743#define ETH_MACA1HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
14744#define ETH_MACA1HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [7:0] */
14745#define ETH_MACA1HR_MACA1H_Pos (0U)
14746#define ETH_MACA1HR_MACA1H_Msk (0xFFFFUL << ETH_MACA1HR_MACA1H_Pos)
14747#define ETH_MACA1HR_MACA1H ETH_MACA1HR_MACA1H_Msk /* MAC address1 high */
14748
14749/* Bit definition for Ethernet MAC Address1 Low Register */
14750#define ETH_MACA1LR_MACA1L_Pos (0U)
14751#define ETH_MACA1LR_MACA1L_Msk (0xFFFFFFFFUL << ETH_MACA1LR_MACA1L_Pos)
14752#define ETH_MACA1LR_MACA1L ETH_MACA1LR_MACA1L_Msk /* MAC address1 low */
14753
14754/* Bit definition for Ethernet MAC Address2 High Register */
14755#define ETH_MACA2HR_AE_Pos (31U)
14756#define ETH_MACA2HR_AE_Msk (0x1UL << ETH_MACA2HR_AE_Pos)
14757#define ETH_MACA2HR_AE ETH_MACA2HR_AE_Msk /* Address enable */
14758#define ETH_MACA2HR_SA_Pos (30U)
14759#define ETH_MACA2HR_SA_Msk (0x1UL << ETH_MACA2HR_SA_Pos)
14760#define ETH_MACA2HR_SA ETH_MACA2HR_SA_Msk /* Source address */
14761#define ETH_MACA2HR_MBC_Pos (24U)
14762#define ETH_MACA2HR_MBC_Msk (0x3FUL << ETH_MACA2HR_MBC_Pos)
14763#define ETH_MACA2HR_MBC ETH_MACA2HR_MBC_Msk /* Mask byte control */
14764#define ETH_MACA2HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
14765#define ETH_MACA2HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
14766#define ETH_MACA2HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
14767#define ETH_MACA2HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
14768#define ETH_MACA2HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
14769#define ETH_MACA2HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
14770#define ETH_MACA2HR_MACA2H_Pos (0U)
14771#define ETH_MACA2HR_MACA2H_Msk (0xFFFFUL << ETH_MACA2HR_MACA2H_Pos)
14772#define ETH_MACA2HR_MACA2H ETH_MACA2HR_MACA2H_Msk /* MAC address1 high */
14773
14774/* Bit definition for Ethernet MAC Address2 Low Register */
14775#define ETH_MACA2LR_MACA2L_Pos (0U)
14776#define ETH_MACA2LR_MACA2L_Msk (0xFFFFFFFFUL << ETH_MACA2LR_MACA2L_Pos)
14777#define ETH_MACA2LR_MACA2L ETH_MACA2LR_MACA2L_Msk /* MAC address2 low */
14778
14779/* Bit definition for Ethernet MAC Address3 High Register */
14780#define ETH_MACA3HR_AE_Pos (31U)
14781#define ETH_MACA3HR_AE_Msk (0x1UL << ETH_MACA3HR_AE_Pos)
14782#define ETH_MACA3HR_AE ETH_MACA3HR_AE_Msk /* Address enable */
14783#define ETH_MACA3HR_SA_Pos (30U)
14784#define ETH_MACA3HR_SA_Msk (0x1UL << ETH_MACA3HR_SA_Pos)
14785#define ETH_MACA3HR_SA ETH_MACA3HR_SA_Msk /* Source address */
14786#define ETH_MACA3HR_MBC_Pos (24U)
14787#define ETH_MACA3HR_MBC_Msk (0x3FUL << ETH_MACA3HR_MBC_Pos)
14788#define ETH_MACA3HR_MBC ETH_MACA3HR_MBC_Msk /* Mask byte control */
14789#define ETH_MACA3HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
14790#define ETH_MACA3HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
14791#define ETH_MACA3HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
14792#define ETH_MACA3HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
14793#define ETH_MACA3HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
14794#define ETH_MACA3HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
14795#define ETH_MACA3HR_MACA3H_Pos (0U)
14796#define ETH_MACA3HR_MACA3H_Msk (0xFFFFUL << ETH_MACA3HR_MACA3H_Pos)
14797#define ETH_MACA3HR_MACA3H ETH_MACA3HR_MACA3H_Msk /* MAC address3 high */
14798
14799/* Bit definition for Ethernet MAC Address3 Low Register */
14800#define ETH_MACA3LR_MACA3L_Pos (0U)
14801#define ETH_MACA3LR_MACA3L_Msk (0xFFFFFFFFUL << ETH_MACA3LR_MACA3L_Pos)
14802#define ETH_MACA3LR_MACA3L ETH_MACA3LR_MACA3L_Msk /* MAC address3 low */
14803
14804/******************************************************************************/
14805/* Ethernet MMC Registers bits definition */
14806/******************************************************************************/
14807
14808/* Bit definition for Ethernet MMC Control Register */
14809#define ETH_MMCCR_MCFHP_Pos (5U)
14810#define ETH_MMCCR_MCFHP_Msk (0x1UL << ETH_MMCCR_MCFHP_Pos)
14811#define ETH_MMCCR_MCFHP ETH_MMCCR_MCFHP_Msk /* MMC counter Full-Half preset */
14812#define ETH_MMCCR_MCP_Pos (4U)
14813#define ETH_MMCCR_MCP_Msk (0x1UL << ETH_MMCCR_MCP_Pos)
14814#define ETH_MMCCR_MCP ETH_MMCCR_MCP_Msk /* MMC counter preset */
14815#define ETH_MMCCR_MCF_Pos (3U)
14816#define ETH_MMCCR_MCF_Msk (0x1UL << ETH_MMCCR_MCF_Pos)
14817#define ETH_MMCCR_MCF ETH_MMCCR_MCF_Msk /* MMC Counter Freeze */
14818#define ETH_MMCCR_ROR_Pos (2U)
14819#define ETH_MMCCR_ROR_Msk (0x1UL << ETH_MMCCR_ROR_Pos)
14820#define ETH_MMCCR_ROR ETH_MMCCR_ROR_Msk /* Reset on Read */
14821#define ETH_MMCCR_CSR_Pos (1U)
14822#define ETH_MMCCR_CSR_Msk (0x1UL << ETH_MMCCR_CSR_Pos)
14823#define ETH_MMCCR_CSR ETH_MMCCR_CSR_Msk /* Counter Stop Rollover */
14824#define ETH_MMCCR_CR_Pos (0U)
14825#define ETH_MMCCR_CR_Msk (0x1UL << ETH_MMCCR_CR_Pos)
14826#define ETH_MMCCR_CR ETH_MMCCR_CR_Msk /* Counters Reset */
14827
14828/* Bit definition for Ethernet MMC Receive Interrupt Register */
14829#define ETH_MMCRIR_RGUFS_Pos (17U)
14830#define ETH_MMCRIR_RGUFS_Msk (0x1UL << ETH_MMCRIR_RGUFS_Pos)
14831#define ETH_MMCRIR_RGUFS ETH_MMCRIR_RGUFS_Msk /* Set when Rx good unicast frames counter reaches half the maximum value */
14832#define ETH_MMCRIR_RFAES_Pos (6U)
14833#define ETH_MMCRIR_RFAES_Msk (0x1UL << ETH_MMCRIR_RFAES_Pos)
14834#define ETH_MMCRIR_RFAES ETH_MMCRIR_RFAES_Msk /* Set when Rx alignment error counter reaches half the maximum value */
14835#define ETH_MMCRIR_RFCES_Pos (5U)
14836#define ETH_MMCRIR_RFCES_Msk (0x1UL << ETH_MMCRIR_RFCES_Pos)
14837#define ETH_MMCRIR_RFCES ETH_MMCRIR_RFCES_Msk /* Set when Rx crc error counter reaches half the maximum value */
14838
14839/* Bit definition for Ethernet MMC Transmit Interrupt Register */
14840#define ETH_MMCTIR_TGFS_Pos (21U)
14841#define ETH_MMCTIR_TGFS_Msk (0x1UL << ETH_MMCTIR_TGFS_Pos)
14842#define ETH_MMCTIR_TGFS ETH_MMCTIR_TGFS_Msk /* Set when Tx good frame count counter reaches half the maximum value */
14843#define ETH_MMCTIR_TGFMSCS_Pos (15U)
14844#define ETH_MMCTIR_TGFMSCS_Msk (0x1UL << ETH_MMCTIR_TGFMSCS_Pos)
14845#define ETH_MMCTIR_TGFMSCS ETH_MMCTIR_TGFMSCS_Msk /* Set when Tx good multi col counter reaches half the maximum value */
14846#define ETH_MMCTIR_TGFSCS_Pos (14U)
14847#define ETH_MMCTIR_TGFSCS_Msk (0x1UL << ETH_MMCTIR_TGFSCS_Pos)
14848#define ETH_MMCTIR_TGFSCS ETH_MMCTIR_TGFSCS_Msk /* Set when Tx good single col counter reaches half the maximum value */
14849
14850/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
14851#define ETH_MMCRIMR_RGUFM_Pos (17U)
14852#define ETH_MMCRIMR_RGUFM_Msk (0x1UL << ETH_MMCRIMR_RGUFM_Pos)
14853#define ETH_MMCRIMR_RGUFM ETH_MMCRIMR_RGUFM_Msk /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
14854#define ETH_MMCRIMR_RFAEM_Pos (6U)
14855#define ETH_MMCRIMR_RFAEM_Msk (0x1UL << ETH_MMCRIMR_RFAEM_Pos)
14856#define ETH_MMCRIMR_RFAEM ETH_MMCRIMR_RFAEM_Msk /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
14857#define ETH_MMCRIMR_RFCEM_Pos (5U)
14858#define ETH_MMCRIMR_RFCEM_Msk (0x1UL << ETH_MMCRIMR_RFCEM_Pos)
14859#define ETH_MMCRIMR_RFCEM ETH_MMCRIMR_RFCEM_Msk /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
14860
14861/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
14862#define ETH_MMCTIMR_TGFM_Pos (21U)
14863#define ETH_MMCTIMR_TGFM_Msk (0x1UL << ETH_MMCTIMR_TGFM_Pos)
14864#define ETH_MMCTIMR_TGFM ETH_MMCTIMR_TGFM_Msk /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
14865#define ETH_MMCTIMR_TGFMSCM_Pos (15U)
14866#define ETH_MMCTIMR_TGFMSCM_Msk (0x1UL << ETH_MMCTIMR_TGFMSCM_Pos)
14867#define ETH_MMCTIMR_TGFMSCM ETH_MMCTIMR_TGFMSCM_Msk /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
14868#define ETH_MMCTIMR_TGFSCM_Pos (14U)
14869#define ETH_MMCTIMR_TGFSCM_Msk (0x1UL << ETH_MMCTIMR_TGFSCM_Pos)
14870#define ETH_MMCTIMR_TGFSCM ETH_MMCTIMR_TGFSCM_Msk /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
14871
14872/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
14873#define ETH_MMCTGFSCCR_TGFSCC_Pos (0U)
14874#define ETH_MMCTGFSCCR_TGFSCC_Msk (0xFFFFFFFFUL << ETH_MMCTGFSCCR_TGFSCC_Pos)
14875#define ETH_MMCTGFSCCR_TGFSCC ETH_MMCTGFSCCR_TGFSCC_Msk /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
14876
14877/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
14878#define ETH_MMCTGFMSCCR_TGFMSCC_Pos (0U)
14879#define ETH_MMCTGFMSCCR_TGFMSCC_Msk (0xFFFFFFFFUL << ETH_MMCTGFMSCCR_TGFMSCC_Pos)
14880#define ETH_MMCTGFMSCCR_TGFMSCC ETH_MMCTGFMSCCR_TGFMSCC_Msk /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
14881
14882/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
14883#define ETH_MMCTGFCR_TGFC_Pos (0U)
14884#define ETH_MMCTGFCR_TGFC_Msk (0xFFFFFFFFUL << ETH_MMCTGFCR_TGFC_Pos)
14885#define ETH_MMCTGFCR_TGFC ETH_MMCTGFCR_TGFC_Msk /* Number of good frames transmitted. */
14886
14887/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
14888#define ETH_MMCRFCECR_RFCEC_Pos (0U)
14889#define ETH_MMCRFCECR_RFCEC_Msk (0xFFFFFFFFUL << ETH_MMCRFCECR_RFCEC_Pos)
14890#define ETH_MMCRFCECR_RFCEC ETH_MMCRFCECR_RFCEC_Msk /* Number of frames received with CRC error. */
14891
14892/* Bit definition for Ethernet MMC Received Frames with Alignment Error Counter Register */
14893#define ETH_MMCRFAECR_RFAEC_Pos (0U)
14894#define ETH_MMCRFAECR_RFAEC_Msk (0xFFFFFFFFUL << ETH_MMCRFAECR_RFAEC_Pos)
14895#define ETH_MMCRFAECR_RFAEC ETH_MMCRFAECR_RFAEC_Msk /* Number of frames received with alignment (dribble) error */
14896
14897/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
14898#define ETH_MMCRGUFCR_RGUFC_Pos (0U)
14899#define ETH_MMCRGUFCR_RGUFC_Msk (0xFFFFFFFFUL << ETH_MMCRGUFCR_RGUFC_Pos)
14900#define ETH_MMCRGUFCR_RGUFC ETH_MMCRGUFCR_RGUFC_Msk /* Number of good unicast frames received. */
14901
14902/******************************************************************************/
14903/* Ethernet PTP Registers bits definition */
14904/******************************************************************************/
14905
14906/* Bit definition for Ethernet PTP Time Stamp Control Register */
14907#define ETH_PTPTSCR_TSPFFMAE_Pos (18U)
14908#define ETH_PTPTSCR_TSPFFMAE_Msk (0x1UL << ETH_PTPTSCR_TSPFFMAE_Pos)
14909#define ETH_PTPTSCR_TSPFFMAE ETH_PTPTSCR_TSPFFMAE_Msk /* Time stamp PTP frame filtering MAC address enable */
14910#define ETH_PTPTSCR_TSCNT_Pos (16U)
14911#define ETH_PTPTSCR_TSCNT_Msk (0x3UL << ETH_PTPTSCR_TSCNT_Pos)
14912#define ETH_PTPTSCR_TSCNT ETH_PTPTSCR_TSCNT_Msk /* Time stamp clock node type */
14913#define ETH_PTPTSCR_TSSMRME_Pos (15U)
14914#define ETH_PTPTSCR_TSSMRME_Msk (0x1UL << ETH_PTPTSCR_TSSMRME_Pos)
14915#define ETH_PTPTSCR_TSSMRME ETH_PTPTSCR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */
14916#define ETH_PTPTSCR_TSSEME_Pos (14U)
14917#define ETH_PTPTSCR_TSSEME_Msk (0x1UL << ETH_PTPTSCR_TSSEME_Pos)
14918#define ETH_PTPTSCR_TSSEME ETH_PTPTSCR_TSSEME_Msk /* Time stamp snapshot for event message enable */
14919#define ETH_PTPTSCR_TSSIPV4FE_Pos (13U)
14920#define ETH_PTPTSCR_TSSIPV4FE_Msk (0x1UL << ETH_PTPTSCR_TSSIPV4FE_Pos)
14921#define ETH_PTPTSCR_TSSIPV4FE ETH_PTPTSCR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */
14922#define ETH_PTPTSCR_TSSIPV6FE_Pos (12U)
14923#define ETH_PTPTSCR_TSSIPV6FE_Msk (0x1UL << ETH_PTPTSCR_TSSIPV6FE_Pos)
14924#define ETH_PTPTSCR_TSSIPV6FE ETH_PTPTSCR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */
14925#define ETH_PTPTSCR_TSSPTPOEFE_Pos (11U)
14926#define ETH_PTPTSCR_TSSPTPOEFE_Msk (0x1UL << ETH_PTPTSCR_TSSPTPOEFE_Pos)
14927#define ETH_PTPTSCR_TSSPTPOEFE ETH_PTPTSCR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */
14928#define ETH_PTPTSCR_TSPTPPSV2E_Pos (10U)
14929#define ETH_PTPTSCR_TSPTPPSV2E_Msk (0x1UL << ETH_PTPTSCR_TSPTPPSV2E_Pos)
14930#define ETH_PTPTSCR_TSPTPPSV2E ETH_PTPTSCR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */
14931#define ETH_PTPTSCR_TSSSR_Pos (9U)
14932#define ETH_PTPTSCR_TSSSR_Msk (0x1UL << ETH_PTPTSCR_TSSSR_Pos)
14933#define ETH_PTPTSCR_TSSSR ETH_PTPTSCR_TSSSR_Msk /* Time stamp Sub-seconds rollover */
14934#define ETH_PTPTSCR_TSSARFE_Pos (8U)
14935#define ETH_PTPTSCR_TSSARFE_Msk (0x1UL << ETH_PTPTSCR_TSSARFE_Pos)
14936#define ETH_PTPTSCR_TSSARFE ETH_PTPTSCR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */
14938#define ETH_PTPTSCR_TSARU_Pos (5U)
14939#define ETH_PTPTSCR_TSARU_Msk (0x1UL << ETH_PTPTSCR_TSARU_Pos)
14940#define ETH_PTPTSCR_TSARU ETH_PTPTSCR_TSARU_Msk /* Addend register update */
14941#define ETH_PTPTSCR_TSITE_Pos (4U)
14942#define ETH_PTPTSCR_TSITE_Msk (0x1UL << ETH_PTPTSCR_TSITE_Pos)
14943#define ETH_PTPTSCR_TSITE ETH_PTPTSCR_TSITE_Msk /* Time stamp interrupt trigger enable */
14944#define ETH_PTPTSCR_TSSTU_Pos (3U)
14945#define ETH_PTPTSCR_TSSTU_Msk (0x1UL << ETH_PTPTSCR_TSSTU_Pos)
14946#define ETH_PTPTSCR_TSSTU ETH_PTPTSCR_TSSTU_Msk /* Time stamp update */
14947#define ETH_PTPTSCR_TSSTI_Pos (2U)
14948#define ETH_PTPTSCR_TSSTI_Msk (0x1UL << ETH_PTPTSCR_TSSTI_Pos)
14949#define ETH_PTPTSCR_TSSTI ETH_PTPTSCR_TSSTI_Msk /* Time stamp initialize */
14950#define ETH_PTPTSCR_TSFCU_Pos (1U)
14951#define ETH_PTPTSCR_TSFCU_Msk (0x1UL << ETH_PTPTSCR_TSFCU_Pos)
14952#define ETH_PTPTSCR_TSFCU ETH_PTPTSCR_TSFCU_Msk /* Time stamp fine or coarse update */
14953#define ETH_PTPTSCR_TSE_Pos (0U)
14954#define ETH_PTPTSCR_TSE_Msk (0x1UL << ETH_PTPTSCR_TSE_Pos)
14955#define ETH_PTPTSCR_TSE ETH_PTPTSCR_TSE_Msk /* Time stamp enable */
14956
14957/* Bit definition for Ethernet PTP Sub-Second Increment Register */
14958#define ETH_PTPSSIR_STSSI_Pos (0U)
14959#define ETH_PTPSSIR_STSSI_Msk (0xFFUL << ETH_PTPSSIR_STSSI_Pos)
14960#define ETH_PTPSSIR_STSSI ETH_PTPSSIR_STSSI_Msk /* System time Sub-second increment value */
14961
14962/* Bit definition for Ethernet PTP Time Stamp High Register */
14963#define ETH_PTPTSHR_STS_Pos (0U)
14964#define ETH_PTPTSHR_STS_Msk (0xFFFFFFFFUL << ETH_PTPTSHR_STS_Pos)
14965#define ETH_PTPTSHR_STS ETH_PTPTSHR_STS_Msk /* System Time second */
14966
14967/* Bit definition for Ethernet PTP Time Stamp Low Register */
14968#define ETH_PTPTSLR_STPNS_Pos (31U)
14969#define ETH_PTPTSLR_STPNS_Msk (0x1UL << ETH_PTPTSLR_STPNS_Pos)
14970#define ETH_PTPTSLR_STPNS ETH_PTPTSLR_STPNS_Msk /* System Time Positive or negative time */
14971#define ETH_PTPTSLR_STSS_Pos (0U)
14972#define ETH_PTPTSLR_STSS_Msk (0x7FFFFFFFUL << ETH_PTPTSLR_STSS_Pos)
14973#define ETH_PTPTSLR_STSS ETH_PTPTSLR_STSS_Msk /* System Time sub-seconds */
14974
14975/* Bit definition for Ethernet PTP Time Stamp High Update Register */
14976#define ETH_PTPTSHUR_TSUS_Pos (0U)
14977#define ETH_PTPTSHUR_TSUS_Msk (0xFFFFFFFFUL << ETH_PTPTSHUR_TSUS_Pos)
14978#define ETH_PTPTSHUR_TSUS ETH_PTPTSHUR_TSUS_Msk /* Time stamp update seconds */
14979
14980/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
14981#define ETH_PTPTSLUR_TSUPNS_Pos (31U)
14982#define ETH_PTPTSLUR_TSUPNS_Msk (0x1UL << ETH_PTPTSLUR_TSUPNS_Pos)
14983#define ETH_PTPTSLUR_TSUPNS ETH_PTPTSLUR_TSUPNS_Msk /* Time stamp update Positive or negative time */
14984#define ETH_PTPTSLUR_TSUSS_Pos (0U)
14985#define ETH_PTPTSLUR_TSUSS_Msk (0x7FFFFFFFUL << ETH_PTPTSLUR_TSUSS_Pos)
14986#define ETH_PTPTSLUR_TSUSS ETH_PTPTSLUR_TSUSS_Msk /* Time stamp update sub-seconds */
14987
14988/* Bit definition for Ethernet PTP Time Stamp Addend Register */
14989#define ETH_PTPTSAR_TSA_Pos (0U)
14990#define ETH_PTPTSAR_TSA_Msk (0xFFFFFFFFUL << ETH_PTPTSAR_TSA_Pos)
14991#define ETH_PTPTSAR_TSA ETH_PTPTSAR_TSA_Msk /* Time stamp addend */
14992
14993/* Bit definition for Ethernet PTP Target Time High Register */
14994#define ETH_PTPTTHR_TTSH_Pos (0U)
14995#define ETH_PTPTTHR_TTSH_Msk (0xFFFFFFFFUL << ETH_PTPTTHR_TTSH_Pos)
14996#define ETH_PTPTTHR_TTSH ETH_PTPTTHR_TTSH_Msk /* Target time stamp high */
14997
14998/* Bit definition for Ethernet PTP Target Time Low Register */
14999#define ETH_PTPTTLR_TTSL_Pos (0U)
15000#define ETH_PTPTTLR_TTSL_Msk (0xFFFFFFFFUL << ETH_PTPTTLR_TTSL_Pos)
15001#define ETH_PTPTTLR_TTSL ETH_PTPTTLR_TTSL_Msk /* Target time stamp low */
15002
15003/* Bit definition for Ethernet PTP Time Stamp Status Register */
15004#define ETH_PTPTSSR_TSTTR_Pos (5U)
15005#define ETH_PTPTSSR_TSTTR_Msk (0x1UL << ETH_PTPTSSR_TSTTR_Pos)
15006#define ETH_PTPTSSR_TSTTR ETH_PTPTSSR_TSTTR_Msk /* Time stamp target time reached */
15007#define ETH_PTPTSSR_TSSO_Pos (4U)
15008#define ETH_PTPTSSR_TSSO_Msk (0x1UL << ETH_PTPTSSR_TSSO_Pos)
15009#define ETH_PTPTSSR_TSSO ETH_PTPTSSR_TSSO_Msk /* Time stamp seconds overflow */
15010
15011/******************************************************************************/
15012/* Ethernet DMA Registers bits definition */
15013/******************************************************************************/
15014
15015/* Bit definition for Ethernet DMA Bus Mode Register */
15016#define ETH_DMABMR_MB_Pos (26U)
15017#define ETH_DMABMR_MB_Msk (0x1UL << ETH_DMABMR_MB_Pos)
15018#define ETH_DMABMR_MB ETH_DMABMR_MB_Msk /* Mixed Burst */
15019#define ETH_DMABMR_AAB_Pos (25U)
15020#define ETH_DMABMR_AAB_Msk (0x1UL << ETH_DMABMR_AAB_Pos)
15021#define ETH_DMABMR_AAB ETH_DMABMR_AAB_Msk /* Address-Aligned beats */
15022#define ETH_DMABMR_FPM_Pos (24U)
15023#define ETH_DMABMR_FPM_Msk (0x1UL << ETH_DMABMR_FPM_Pos)
15024#define ETH_DMABMR_FPM ETH_DMABMR_FPM_Msk /* 4xPBL mode */
15025#define ETH_DMABMR_USP_Pos (23U)
15026#define ETH_DMABMR_USP_Msk (0x1UL << ETH_DMABMR_USP_Pos)
15027#define ETH_DMABMR_USP ETH_DMABMR_USP_Msk /* Use separate PBL */
15028#define ETH_DMABMR_RDP_Pos (17U)
15029#define ETH_DMABMR_RDP_Msk (0x3FUL << ETH_DMABMR_RDP_Pos)
15030#define ETH_DMABMR_RDP ETH_DMABMR_RDP_Msk /* RxDMA PBL */
15031#define ETH_DMABMR_RDP_1Beat 0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
15032#define ETH_DMABMR_RDP_2Beat 0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
15033#define ETH_DMABMR_RDP_4Beat 0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
15034#define ETH_DMABMR_RDP_8Beat 0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
15035#define ETH_DMABMR_RDP_16Beat 0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
15036#define ETH_DMABMR_RDP_32Beat 0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
15037#define ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
15038#define ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
15039#define ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
15040#define ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
15041#define ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
15042#define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
15043#define ETH_DMABMR_FB_Pos (16U)
15044#define ETH_DMABMR_FB_Msk (0x1UL << ETH_DMABMR_FB_Pos)
15045#define ETH_DMABMR_FB ETH_DMABMR_FB_Msk /* Fixed Burst */
15046#define ETH_DMABMR_RTPR_Pos (14U)
15047#define ETH_DMABMR_RTPR_Msk (0x3UL << ETH_DMABMR_RTPR_Pos)
15048#define ETH_DMABMR_RTPR ETH_DMABMR_RTPR_Msk /* Rx Tx priority ratio */
15049#define ETH_DMABMR_RTPR_1_1 0x00000000U /* Rx Tx priority ratio */
15050#define ETH_DMABMR_RTPR_2_1 0x00004000U /* Rx Tx priority ratio */
15051#define ETH_DMABMR_RTPR_3_1 0x00008000U /* Rx Tx priority ratio */
15052#define ETH_DMABMR_RTPR_4_1 0x0000C000U /* Rx Tx priority ratio */
15053#define ETH_DMABMR_PBL_Pos (8U)
15054#define ETH_DMABMR_PBL_Msk (0x3FUL << ETH_DMABMR_PBL_Pos)
15055#define ETH_DMABMR_PBL ETH_DMABMR_PBL_Msk /* Programmable burst length */
15056#define ETH_DMABMR_PBL_1Beat 0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
15057#define ETH_DMABMR_PBL_2Beat 0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
15058#define ETH_DMABMR_PBL_4Beat 0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
15059#define ETH_DMABMR_PBL_8Beat 0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
15060#define ETH_DMABMR_PBL_16Beat 0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
15061#define ETH_DMABMR_PBL_32Beat 0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
15062#define ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
15063#define ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
15064#define ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
15065#define ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
15066#define ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
15067#define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
15068#define ETH_DMABMR_EDE_Pos (7U)
15069#define ETH_DMABMR_EDE_Msk (0x1UL << ETH_DMABMR_EDE_Pos)
15070#define ETH_DMABMR_EDE ETH_DMABMR_EDE_Msk /* Enhanced Descriptor Enable */
15071#define ETH_DMABMR_DSL_Pos (2U)
15072#define ETH_DMABMR_DSL_Msk (0x1FUL << ETH_DMABMR_DSL_Pos)
15073#define ETH_DMABMR_DSL ETH_DMABMR_DSL_Msk /* Descriptor Skip Length */
15074#define ETH_DMABMR_DA_Pos (1U)
15075#define ETH_DMABMR_DA_Msk (0x1UL << ETH_DMABMR_DA_Pos)
15076#define ETH_DMABMR_DA ETH_DMABMR_DA_Msk /* DMA arbitration scheme */
15077#define ETH_DMABMR_SR_Pos (0U)
15078#define ETH_DMABMR_SR_Msk (0x1UL << ETH_DMABMR_SR_Pos)
15079#define ETH_DMABMR_SR ETH_DMABMR_SR_Msk /* Software reset */
15080
15081/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
15082#define ETH_DMATPDR_TPD_Pos (0U)
15083#define ETH_DMATPDR_TPD_Msk (0xFFFFFFFFUL << ETH_DMATPDR_TPD_Pos)
15084#define ETH_DMATPDR_TPD ETH_DMATPDR_TPD_Msk /* Transmit poll demand */
15085
15086/* Bit definition for Ethernet DMA Receive Poll Demand Register */
15087#define ETH_DMARPDR_RPD_Pos (0U)
15088#define ETH_DMARPDR_RPD_Msk (0xFFFFFFFFUL << ETH_DMARPDR_RPD_Pos)
15089#define ETH_DMARPDR_RPD ETH_DMARPDR_RPD_Msk /* Receive poll demand */
15090
15091/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
15092#define ETH_DMARDLAR_SRL_Pos (0U)
15093#define ETH_DMARDLAR_SRL_Msk (0xFFFFFFFFUL << ETH_DMARDLAR_SRL_Pos)
15094#define ETH_DMARDLAR_SRL ETH_DMARDLAR_SRL_Msk /* Start of receive list */
15095
15096/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
15097#define ETH_DMATDLAR_STL_Pos (0U)
15098#define ETH_DMATDLAR_STL_Msk (0xFFFFFFFFUL << ETH_DMATDLAR_STL_Pos)
15099#define ETH_DMATDLAR_STL ETH_DMATDLAR_STL_Msk /* Start of transmit list */
15100
15101/* Bit definition for Ethernet DMA Status Register */
15102#define ETH_DMASR_TSTS_Pos (29U)
15103#define ETH_DMASR_TSTS_Msk (0x1UL << ETH_DMASR_TSTS_Pos)
15104#define ETH_DMASR_TSTS ETH_DMASR_TSTS_Msk /* Time-stamp trigger status */
15105#define ETH_DMASR_PMTS_Pos (28U)
15106#define ETH_DMASR_PMTS_Msk (0x1UL << ETH_DMASR_PMTS_Pos)
15107#define ETH_DMASR_PMTS ETH_DMASR_PMTS_Msk /* PMT status */
15108#define ETH_DMASR_MMCS_Pos (27U)
15109#define ETH_DMASR_MMCS_Msk (0x1UL << ETH_DMASR_MMCS_Pos)
15110#define ETH_DMASR_MMCS ETH_DMASR_MMCS_Msk /* MMC status */
15111#define ETH_DMASR_EBS_Pos (23U)
15112#define ETH_DMASR_EBS_Msk (0x7UL << ETH_DMASR_EBS_Pos)
15113#define ETH_DMASR_EBS ETH_DMASR_EBS_Msk /* Error bits status */
15114/* combination with EBS[2:0] for GetFlagStatus function */
15115#define ETH_DMASR_EBS_DescAccess_Pos (25U)
15116#define ETH_DMASR_EBS_DescAccess_Msk (0x1UL << ETH_DMASR_EBS_DescAccess_Pos)
15117#define ETH_DMASR_EBS_DescAccess ETH_DMASR_EBS_DescAccess_Msk /* Error bits 0-data buffer, 1-desc. access */
15118#define ETH_DMASR_EBS_ReadTransf_Pos (24U)
15119#define ETH_DMASR_EBS_ReadTransf_Msk (0x1UL << ETH_DMASR_EBS_ReadTransf_Pos)
15120#define ETH_DMASR_EBS_ReadTransf ETH_DMASR_EBS_ReadTransf_Msk /* Error bits 0-write trnsf, 1-read transfr */
15121#define ETH_DMASR_EBS_DataTransfTx_Pos (23U)
15122#define ETH_DMASR_EBS_DataTransfTx_Msk (0x1UL << ETH_DMASR_EBS_DataTransfTx_Pos)
15123#define ETH_DMASR_EBS_DataTransfTx ETH_DMASR_EBS_DataTransfTx_Msk /* Error bits 0-Rx DMA, 1-Tx DMA */
15124#define ETH_DMASR_TPS_Pos (20U)
15125#define ETH_DMASR_TPS_Msk (0x7UL << ETH_DMASR_TPS_Pos)
15126#define ETH_DMASR_TPS ETH_DMASR_TPS_Msk /* Transmit process state */
15127#define ETH_DMASR_TPS_Stopped 0x00000000U /* Stopped - Reset or Stop Tx Command issued */
15128#define ETH_DMASR_TPS_Fetching_Pos (20U)
15129#define ETH_DMASR_TPS_Fetching_Msk (0x1UL << ETH_DMASR_TPS_Fetching_Pos)
15130#define ETH_DMASR_TPS_Fetching ETH_DMASR_TPS_Fetching_Msk /* Running - fetching the Tx descriptor */
15131#define ETH_DMASR_TPS_Waiting_Pos (21U)
15132#define ETH_DMASR_TPS_Waiting_Msk (0x1UL << ETH_DMASR_TPS_Waiting_Pos)
15133#define ETH_DMASR_TPS_Waiting ETH_DMASR_TPS_Waiting_Msk /* Running - waiting for status */
15134#define ETH_DMASR_TPS_Reading_Pos (20U)
15135#define ETH_DMASR_TPS_Reading_Msk (0x3UL << ETH_DMASR_TPS_Reading_Pos)
15136#define ETH_DMASR_TPS_Reading ETH_DMASR_TPS_Reading_Msk /* Running - reading the data from host memory */
15137#define ETH_DMASR_TPS_Suspended_Pos (21U)
15138#define ETH_DMASR_TPS_Suspended_Msk (0x3UL << ETH_DMASR_TPS_Suspended_Pos)
15139#define ETH_DMASR_TPS_Suspended ETH_DMASR_TPS_Suspended_Msk /* Suspended - Tx Descriptor unavailable */
15140#define ETH_DMASR_TPS_Closing_Pos (20U)
15141#define ETH_DMASR_TPS_Closing_Msk (0x7UL << ETH_DMASR_TPS_Closing_Pos)
15142#define ETH_DMASR_TPS_Closing ETH_DMASR_TPS_Closing_Msk /* Running - closing Rx descriptor */
15143#define ETH_DMASR_RPS_Pos (17U)
15144#define ETH_DMASR_RPS_Msk (0x7UL << ETH_DMASR_RPS_Pos)
15145#define ETH_DMASR_RPS ETH_DMASR_RPS_Msk /* Receive process state */
15146#define ETH_DMASR_RPS_Stopped 0x00000000U /* Stopped - Reset or Stop Rx Command issued */
15147#define ETH_DMASR_RPS_Fetching_Pos (17U)
15148#define ETH_DMASR_RPS_Fetching_Msk (0x1UL << ETH_DMASR_RPS_Fetching_Pos)
15149#define ETH_DMASR_RPS_Fetching ETH_DMASR_RPS_Fetching_Msk /* Running - fetching the Rx descriptor */
15150#define ETH_DMASR_RPS_Waiting_Pos (17U)
15151#define ETH_DMASR_RPS_Waiting_Msk (0x3UL << ETH_DMASR_RPS_Waiting_Pos)
15152#define ETH_DMASR_RPS_Waiting ETH_DMASR_RPS_Waiting_Msk /* Running - waiting for packet */
15153#define ETH_DMASR_RPS_Suspended_Pos (19U)
15154#define ETH_DMASR_RPS_Suspended_Msk (0x1UL << ETH_DMASR_RPS_Suspended_Pos)
15155#define ETH_DMASR_RPS_Suspended ETH_DMASR_RPS_Suspended_Msk /* Suspended - Rx Descriptor unavailable */
15156#define ETH_DMASR_RPS_Closing_Pos (17U)
15157#define ETH_DMASR_RPS_Closing_Msk (0x5UL << ETH_DMASR_RPS_Closing_Pos)
15158#define ETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */
15159#define ETH_DMASR_RPS_Queuing_Pos (17U)
15160#define ETH_DMASR_RPS_Queuing_Msk (0x7UL << ETH_DMASR_RPS_Queuing_Pos)
15161#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the receive frame into host memory */
15162#define ETH_DMASR_NIS_Pos (16U)
15163#define ETH_DMASR_NIS_Msk (0x1UL << ETH_DMASR_NIS_Pos)
15164#define ETH_DMASR_NIS ETH_DMASR_NIS_Msk /* Normal interrupt summary */
15165#define ETH_DMASR_AIS_Pos (15U)
15166#define ETH_DMASR_AIS_Msk (0x1UL << ETH_DMASR_AIS_Pos)
15167#define ETH_DMASR_AIS ETH_DMASR_AIS_Msk /* Abnormal interrupt summary */
15168#define ETH_DMASR_ERS_Pos (14U)
15169#define ETH_DMASR_ERS_Msk (0x1UL << ETH_DMASR_ERS_Pos)
15170#define ETH_DMASR_ERS ETH_DMASR_ERS_Msk /* Early receive status */
15171#define ETH_DMASR_FBES_Pos (13U)
15172#define ETH_DMASR_FBES_Msk (0x1UL << ETH_DMASR_FBES_Pos)
15173#define ETH_DMASR_FBES ETH_DMASR_FBES_Msk /* Fatal bus error status */
15174#define ETH_DMASR_ETS_Pos (10U)
15175#define ETH_DMASR_ETS_Msk (0x1UL << ETH_DMASR_ETS_Pos)
15176#define ETH_DMASR_ETS ETH_DMASR_ETS_Msk /* Early transmit status */
15177#define ETH_DMASR_RWTS_Pos (9U)
15178#define ETH_DMASR_RWTS_Msk (0x1UL << ETH_DMASR_RWTS_Pos)
15179#define ETH_DMASR_RWTS ETH_DMASR_RWTS_Msk /* Receive watchdog timeout status */
15180#define ETH_DMASR_RPSS_Pos (8U)
15181#define ETH_DMASR_RPSS_Msk (0x1UL << ETH_DMASR_RPSS_Pos)
15182#define ETH_DMASR_RPSS ETH_DMASR_RPSS_Msk /* Receive process stopped status */
15183#define ETH_DMASR_RBUS_Pos (7U)
15184#define ETH_DMASR_RBUS_Msk (0x1UL << ETH_DMASR_RBUS_Pos)
15185#define ETH_DMASR_RBUS ETH_DMASR_RBUS_Msk /* Receive buffer unavailable status */
15186#define ETH_DMASR_RS_Pos (6U)
15187#define ETH_DMASR_RS_Msk (0x1UL << ETH_DMASR_RS_Pos)
15188#define ETH_DMASR_RS ETH_DMASR_RS_Msk /* Receive status */
15189#define ETH_DMASR_TUS_Pos (5U)
15190#define ETH_DMASR_TUS_Msk (0x1UL << ETH_DMASR_TUS_Pos)
15191#define ETH_DMASR_TUS ETH_DMASR_TUS_Msk /* Transmit underflow status */
15192#define ETH_DMASR_ROS_Pos (4U)
15193#define ETH_DMASR_ROS_Msk (0x1UL << ETH_DMASR_ROS_Pos)
15194#define ETH_DMASR_ROS ETH_DMASR_ROS_Msk /* Receive overflow status */
15195#define ETH_DMASR_TJTS_Pos (3U)
15196#define ETH_DMASR_TJTS_Msk (0x1UL << ETH_DMASR_TJTS_Pos)
15197#define ETH_DMASR_TJTS ETH_DMASR_TJTS_Msk /* Transmit jabber timeout status */
15198#define ETH_DMASR_TBUS_Pos (2U)
15199#define ETH_DMASR_TBUS_Msk (0x1UL << ETH_DMASR_TBUS_Pos)
15200#define ETH_DMASR_TBUS ETH_DMASR_TBUS_Msk /* Transmit buffer unavailable status */
15201#define ETH_DMASR_TPSS_Pos (1U)
15202#define ETH_DMASR_TPSS_Msk (0x1UL << ETH_DMASR_TPSS_Pos)
15203#define ETH_DMASR_TPSS ETH_DMASR_TPSS_Msk /* Transmit process stopped status */
15204#define ETH_DMASR_TS_Pos (0U)
15205#define ETH_DMASR_TS_Msk (0x1UL << ETH_DMASR_TS_Pos)
15206#define ETH_DMASR_TS ETH_DMASR_TS_Msk /* Transmit status */
15207
15208/* Bit definition for Ethernet DMA Operation Mode Register */
15209#define ETH_DMAOMR_DTCEFD_Pos (26U)
15210#define ETH_DMAOMR_DTCEFD_Msk (0x1UL << ETH_DMAOMR_DTCEFD_Pos)
15211#define ETH_DMAOMR_DTCEFD ETH_DMAOMR_DTCEFD_Msk /* Disable Dropping of TCP/IP checksum error frames */
15212#define ETH_DMAOMR_RSF_Pos (25U)
15213#define ETH_DMAOMR_RSF_Msk (0x1UL << ETH_DMAOMR_RSF_Pos)
15214#define ETH_DMAOMR_RSF ETH_DMAOMR_RSF_Msk /* Receive store and forward */
15215#define ETH_DMAOMR_DFRF_Pos (24U)
15216#define ETH_DMAOMR_DFRF_Msk (0x1UL << ETH_DMAOMR_DFRF_Pos)
15217#define ETH_DMAOMR_DFRF ETH_DMAOMR_DFRF_Msk /* Disable flushing of received frames */
15218#define ETH_DMAOMR_TSF_Pos (21U)
15219#define ETH_DMAOMR_TSF_Msk (0x1UL << ETH_DMAOMR_TSF_Pos)
15220#define ETH_DMAOMR_TSF ETH_DMAOMR_TSF_Msk /* Transmit store and forward */
15221#define ETH_DMAOMR_FTF_Pos (20U)
15222#define ETH_DMAOMR_FTF_Msk (0x1UL << ETH_DMAOMR_FTF_Pos)
15223#define ETH_DMAOMR_FTF ETH_DMAOMR_FTF_Msk /* Flush transmit FIFO */
15224#define ETH_DMAOMR_TTC_Pos (14U)
15225#define ETH_DMAOMR_TTC_Msk (0x7UL << ETH_DMAOMR_TTC_Pos)
15226#define ETH_DMAOMR_TTC ETH_DMAOMR_TTC_Msk /* Transmit threshold control */
15227#define ETH_DMAOMR_TTC_64Bytes 0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */
15228#define ETH_DMAOMR_TTC_128Bytes 0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */
15229#define ETH_DMAOMR_TTC_192Bytes 0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */
15230#define ETH_DMAOMR_TTC_256Bytes 0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */
15231#define ETH_DMAOMR_TTC_40Bytes 0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */
15232#define ETH_DMAOMR_TTC_32Bytes 0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */
15233#define ETH_DMAOMR_TTC_24Bytes 0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */
15234#define ETH_DMAOMR_TTC_16Bytes 0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */
15235#define ETH_DMAOMR_ST_Pos (13U)
15236#define ETH_DMAOMR_ST_Msk (0x1UL << ETH_DMAOMR_ST_Pos)
15237#define ETH_DMAOMR_ST ETH_DMAOMR_ST_Msk /* Start/stop transmission command */
15238#define ETH_DMAOMR_FEF_Pos (7U)
15239#define ETH_DMAOMR_FEF_Msk (0x1UL << ETH_DMAOMR_FEF_Pos)
15240#define ETH_DMAOMR_FEF ETH_DMAOMR_FEF_Msk /* Forward error frames */
15241#define ETH_DMAOMR_FUGF_Pos (6U)
15242#define ETH_DMAOMR_FUGF_Msk (0x1UL << ETH_DMAOMR_FUGF_Pos)
15243#define ETH_DMAOMR_FUGF ETH_DMAOMR_FUGF_Msk /* Forward undersized good frames */
15244#define ETH_DMAOMR_RTC_Pos (3U)
15245#define ETH_DMAOMR_RTC_Msk (0x3UL << ETH_DMAOMR_RTC_Pos)
15246#define ETH_DMAOMR_RTC ETH_DMAOMR_RTC_Msk /* receive threshold control */
15247#define ETH_DMAOMR_RTC_64Bytes 0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */
15248#define ETH_DMAOMR_RTC_32Bytes 0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */
15249#define ETH_DMAOMR_RTC_96Bytes 0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */
15250#define ETH_DMAOMR_RTC_128Bytes 0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */
15251#define ETH_DMAOMR_OSF_Pos (2U)
15252#define ETH_DMAOMR_OSF_Msk (0x1UL << ETH_DMAOMR_OSF_Pos)
15253#define ETH_DMAOMR_OSF ETH_DMAOMR_OSF_Msk /* operate on second frame */
15254#define ETH_DMAOMR_SR_Pos (1U)
15255#define ETH_DMAOMR_SR_Msk (0x1UL << ETH_DMAOMR_SR_Pos)
15256#define ETH_DMAOMR_SR ETH_DMAOMR_SR_Msk /* Start/stop receive */
15257
15258/* Bit definition for Ethernet DMA Interrupt Enable Register */
15259#define ETH_DMAIER_NISE_Pos (16U)
15260#define ETH_DMAIER_NISE_Msk (0x1UL << ETH_DMAIER_NISE_Pos)
15261#define ETH_DMAIER_NISE ETH_DMAIER_NISE_Msk /* Normal interrupt summary enable */
15262#define ETH_DMAIER_AISE_Pos (15U)
15263#define ETH_DMAIER_AISE_Msk (0x1UL << ETH_DMAIER_AISE_Pos)
15264#define ETH_DMAIER_AISE ETH_DMAIER_AISE_Msk /* Abnormal interrupt summary enable */
15265#define ETH_DMAIER_ERIE_Pos (14U)
15266#define ETH_DMAIER_ERIE_Msk (0x1UL << ETH_DMAIER_ERIE_Pos)
15267#define ETH_DMAIER_ERIE ETH_DMAIER_ERIE_Msk /* Early receive interrupt enable */
15268#define ETH_DMAIER_FBEIE_Pos (13U)
15269#define ETH_DMAIER_FBEIE_Msk (0x1UL << ETH_DMAIER_FBEIE_Pos)
15270#define ETH_DMAIER_FBEIE ETH_DMAIER_FBEIE_Msk /* Fatal bus error interrupt enable */
15271#define ETH_DMAIER_ETIE_Pos (10U)
15272#define ETH_DMAIER_ETIE_Msk (0x1UL << ETH_DMAIER_ETIE_Pos)
15273#define ETH_DMAIER_ETIE ETH_DMAIER_ETIE_Msk /* Early transmit interrupt enable */
15274#define ETH_DMAIER_RWTIE_Pos (9U)
15275#define ETH_DMAIER_RWTIE_Msk (0x1UL << ETH_DMAIER_RWTIE_Pos)
15276#define ETH_DMAIER_RWTIE ETH_DMAIER_RWTIE_Msk /* Receive watchdog timeout interrupt enable */
15277#define ETH_DMAIER_RPSIE_Pos (8U)
15278#define ETH_DMAIER_RPSIE_Msk (0x1UL << ETH_DMAIER_RPSIE_Pos)
15279#define ETH_DMAIER_RPSIE ETH_DMAIER_RPSIE_Msk /* Receive process stopped interrupt enable */
15280#define ETH_DMAIER_RBUIE_Pos (7U)
15281#define ETH_DMAIER_RBUIE_Msk (0x1UL << ETH_DMAIER_RBUIE_Pos)
15282#define ETH_DMAIER_RBUIE ETH_DMAIER_RBUIE_Msk /* Receive buffer unavailable interrupt enable */
15283#define ETH_DMAIER_RIE_Pos (6U)
15284#define ETH_DMAIER_RIE_Msk (0x1UL << ETH_DMAIER_RIE_Pos)
15285#define ETH_DMAIER_RIE ETH_DMAIER_RIE_Msk /* Receive interrupt enable */
15286#define ETH_DMAIER_TUIE_Pos (5U)
15287#define ETH_DMAIER_TUIE_Msk (0x1UL << ETH_DMAIER_TUIE_Pos)
15288#define ETH_DMAIER_TUIE ETH_DMAIER_TUIE_Msk /* Transmit Underflow interrupt enable */
15289#define ETH_DMAIER_ROIE_Pos (4U)
15290#define ETH_DMAIER_ROIE_Msk (0x1UL << ETH_DMAIER_ROIE_Pos)
15291#define ETH_DMAIER_ROIE ETH_DMAIER_ROIE_Msk /* Receive Overflow interrupt enable */
15292#define ETH_DMAIER_TJTIE_Pos (3U)
15293#define ETH_DMAIER_TJTIE_Msk (0x1UL << ETH_DMAIER_TJTIE_Pos)
15294#define ETH_DMAIER_TJTIE ETH_DMAIER_TJTIE_Msk /* Transmit jabber timeout interrupt enable */
15295#define ETH_DMAIER_TBUIE_Pos (2U)
15296#define ETH_DMAIER_TBUIE_Msk (0x1UL << ETH_DMAIER_TBUIE_Pos)
15297#define ETH_DMAIER_TBUIE ETH_DMAIER_TBUIE_Msk /* Transmit buffer unavailable interrupt enable */
15298#define ETH_DMAIER_TPSIE_Pos (1U)
15299#define ETH_DMAIER_TPSIE_Msk (0x1UL << ETH_DMAIER_TPSIE_Pos)
15300#define ETH_DMAIER_TPSIE ETH_DMAIER_TPSIE_Msk /* Transmit process stopped interrupt enable */
15301#define ETH_DMAIER_TIE_Pos (0U)
15302#define ETH_DMAIER_TIE_Msk (0x1UL << ETH_DMAIER_TIE_Pos)
15303#define ETH_DMAIER_TIE ETH_DMAIER_TIE_Msk /* Transmit interrupt enable */
15304
15305/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
15306#define ETH_DMAMFBOCR_OFOC_Pos (28U)
15307#define ETH_DMAMFBOCR_OFOC_Msk (0x1UL << ETH_DMAMFBOCR_OFOC_Pos)
15308#define ETH_DMAMFBOCR_OFOC ETH_DMAMFBOCR_OFOC_Msk /* Overflow bit for FIFO overflow counter */
15309#define ETH_DMAMFBOCR_MFA_Pos (17U)
15310#define ETH_DMAMFBOCR_MFA_Msk (0x7FFUL << ETH_DMAMFBOCR_MFA_Pos)
15311#define ETH_DMAMFBOCR_MFA ETH_DMAMFBOCR_MFA_Msk /* Number of frames missed by the application */
15312#define ETH_DMAMFBOCR_OMFC_Pos (16U)
15313#define ETH_DMAMFBOCR_OMFC_Msk (0x1UL << ETH_DMAMFBOCR_OMFC_Pos)
15314#define ETH_DMAMFBOCR_OMFC ETH_DMAMFBOCR_OMFC_Msk /* Overflow bit for missed frame counter */
15315#define ETH_DMAMFBOCR_MFC_Pos (0U)
15316#define ETH_DMAMFBOCR_MFC_Msk (0xFFFFUL << ETH_DMAMFBOCR_MFC_Pos)
15317#define ETH_DMAMFBOCR_MFC ETH_DMAMFBOCR_MFC_Msk /* Number of frames missed by the controller */
15318
15319/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
15320#define ETH_DMACHTDR_HTDAP_Pos (0U)
15321#define ETH_DMACHTDR_HTDAP_Msk (0xFFFFFFFFUL << ETH_DMACHTDR_HTDAP_Pos)
15322#define ETH_DMACHTDR_HTDAP ETH_DMACHTDR_HTDAP_Msk /* Host transmit descriptor address pointer */
15323
15324/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
15325#define ETH_DMACHRDR_HRDAP_Pos (0U)
15326#define ETH_DMACHRDR_HRDAP_Msk (0xFFFFFFFFUL << ETH_DMACHRDR_HRDAP_Pos)
15327#define ETH_DMACHRDR_HRDAP ETH_DMACHRDR_HRDAP_Msk /* Host receive descriptor address pointer */
15328
15329/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
15330#define ETH_DMACHTBAR_HTBAP_Pos (0U)
15331#define ETH_DMACHTBAR_HTBAP_Msk (0xFFFFFFFFUL << ETH_DMACHTBAR_HTBAP_Pos)
15332#define ETH_DMACHTBAR_HTBAP ETH_DMACHTBAR_HTBAP_Msk /* Host transmit buffer address pointer */
15333
15334/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
15335#define ETH_DMACHRBAR_HRBAP_Pos (0U)
15336#define ETH_DMACHRBAR_HRBAP_Msk (0xFFFFFFFFUL << ETH_DMACHRBAR_HRBAP_Pos)
15337#define ETH_DMACHRBAR_HRBAP ETH_DMACHRBAR_HRBAP_Msk /* Host receive buffer address pointer */
15338
15339/******************************************************************************/
15340/* */
15341/* USB_OTG */
15342/* */
15343/******************************************************************************/
15344/******************** Bit definition for USB_OTG_GOTGCTL register ***********/
15345#define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
15346#define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos)
15347#define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk
15348#define USB_OTG_GOTGCTL_SRQ_Pos (1U)
15349#define USB_OTG_GOTGCTL_SRQ_Msk (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos)
15350#define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk
15351#define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
15352#define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos)
15353#define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk
15354#define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
15355#define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos)
15356#define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk
15357#define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
15358#define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos)
15359#define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk
15360#define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
15361#define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos)
15362#define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk
15363#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
15364#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos)
15365#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk
15366#define USB_OTG_GOTGCTL_DBCT_Pos (17U)
15367#define USB_OTG_GOTGCTL_DBCT_Msk (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos)
15368#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk
15369#define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
15370#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos)
15371#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk
15372#define USB_OTG_GOTGCTL_BSVLD_Pos (19U)
15373#define USB_OTG_GOTGCTL_BSVLD_Msk (0x1UL << USB_OTG_GOTGCTL_BSVLD_Pos)
15374#define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk
15375
15376/******************** Bit definition forUSB_OTG_HCFG register ********************/
15378#define USB_OTG_HCFG_FSLSPCS_Pos (0U)
15379#define USB_OTG_HCFG_FSLSPCS_Msk (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos)
15380#define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk
15381#define USB_OTG_HCFG_FSLSPCS_0 (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos)
15382#define USB_OTG_HCFG_FSLSPCS_1 (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos)
15383#define USB_OTG_HCFG_FSLSS_Pos (2U)
15384#define USB_OTG_HCFG_FSLSS_Msk (0x1UL << USB_OTG_HCFG_FSLSS_Pos)
15385#define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk
15386
15387/******************** Bit definition for USB_OTG_DCFG register ********************/
15389#define USB_OTG_DCFG_DSPD_Pos (0U)
15390#define USB_OTG_DCFG_DSPD_Msk (0x3UL << USB_OTG_DCFG_DSPD_Pos)
15391#define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk
15392#define USB_OTG_DCFG_DSPD_0 (0x1UL << USB_OTG_DCFG_DSPD_Pos)
15393#define USB_OTG_DCFG_DSPD_1 (0x2UL << USB_OTG_DCFG_DSPD_Pos)
15394#define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
15395#define USB_OTG_DCFG_NZLSOHSK_Msk (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos)
15396#define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk
15398#define USB_OTG_DCFG_DAD_Pos (4U)
15399#define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos)
15400#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk
15401#define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos)
15402#define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos)
15403#define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos)
15404#define USB_OTG_DCFG_DAD_3 (0x08UL << USB_OTG_DCFG_DAD_Pos)
15405#define USB_OTG_DCFG_DAD_4 (0x10UL << USB_OTG_DCFG_DAD_Pos)
15406#define USB_OTG_DCFG_DAD_5 (0x20UL << USB_OTG_DCFG_DAD_Pos)
15407#define USB_OTG_DCFG_DAD_6 (0x40UL << USB_OTG_DCFG_DAD_Pos)
15409#define USB_OTG_DCFG_PFIVL_Pos (11U)
15410#define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos)
15411#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk
15412#define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos)
15413#define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos)
15415#define USB_OTG_DCFG_XCVRDLY_Pos (14U)
15416#define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos)
15417#define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk
15419#define USB_OTG_DCFG_ERRATIM_Pos (15U)
15420#define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos)
15421#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk
15423#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
15424#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos)
15425#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk
15426#define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos)
15427#define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos)
15428
15429/******************** Bit definition for USB_OTG_PCGCR register ********************/
15430#define USB_OTG_PCGCR_STPPCLK_Pos (0U)
15431#define USB_OTG_PCGCR_STPPCLK_Msk (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos)
15432#define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk
15433#define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
15434#define USB_OTG_PCGCR_GATEHCLK_Msk (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos)
15435#define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk
15436#define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
15437#define USB_OTG_PCGCR_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos)
15438#define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk
15439
15440/******************** Bit definition for USB_OTG_GOTGINT register ********************/
15441#define USB_OTG_GOTGINT_SEDET_Pos (2U)
15442#define USB_OTG_GOTGINT_SEDET_Msk (0x1UL << USB_OTG_GOTGINT_SEDET_Pos)
15443#define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk
15444#define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
15445#define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos)
15446#define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk
15447#define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
15448#define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos)
15449#define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk
15450#define USB_OTG_GOTGINT_HNGDET_Pos (17U)
15451#define USB_OTG_GOTGINT_HNGDET_Msk (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos)
15452#define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk
15453#define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
15454#define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos)
15455#define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk
15456#define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
15457#define USB_OTG_GOTGINT_DBCDNE_Msk (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos)
15458#define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk
15459
15460/******************** Bit definition for USB_OTG_DCTL register ********************/
15461#define USB_OTG_DCTL_RWUSIG_Pos (0U)
15462#define USB_OTG_DCTL_RWUSIG_Msk (0x1UL << USB_OTG_DCTL_RWUSIG_Pos)
15463#define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk
15464#define USB_OTG_DCTL_SDIS_Pos (1U)
15465#define USB_OTG_DCTL_SDIS_Msk (0x1UL << USB_OTG_DCTL_SDIS_Pos)
15466#define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk
15467#define USB_OTG_DCTL_GINSTS_Pos (2U)
15468#define USB_OTG_DCTL_GINSTS_Msk (0x1UL << USB_OTG_DCTL_GINSTS_Pos)
15469#define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk
15470#define USB_OTG_DCTL_GONSTS_Pos (3U)
15471#define USB_OTG_DCTL_GONSTS_Msk (0x1UL << USB_OTG_DCTL_GONSTS_Pos)
15472#define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk
15474#define USB_OTG_DCTL_TCTL_Pos (4U)
15475#define USB_OTG_DCTL_TCTL_Msk (0x7UL << USB_OTG_DCTL_TCTL_Pos)
15476#define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk
15477#define USB_OTG_DCTL_TCTL_0 (0x1UL << USB_OTG_DCTL_TCTL_Pos)
15478#define USB_OTG_DCTL_TCTL_1 (0x2UL << USB_OTG_DCTL_TCTL_Pos)
15479#define USB_OTG_DCTL_TCTL_2 (0x4UL << USB_OTG_DCTL_TCTL_Pos)
15480#define USB_OTG_DCTL_SGINAK_Pos (7U)
15481#define USB_OTG_DCTL_SGINAK_Msk (0x1UL << USB_OTG_DCTL_SGINAK_Pos)
15482#define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk
15483#define USB_OTG_DCTL_CGINAK_Pos (8U)
15484#define USB_OTG_DCTL_CGINAK_Msk (0x1UL << USB_OTG_DCTL_CGINAK_Pos)
15485#define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk
15486#define USB_OTG_DCTL_SGONAK_Pos (9U)
15487#define USB_OTG_DCTL_SGONAK_Msk (0x1UL << USB_OTG_DCTL_SGONAK_Pos)
15488#define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk
15489#define USB_OTG_DCTL_CGONAK_Pos (10U)
15490#define USB_OTG_DCTL_CGONAK_Msk (0x1UL << USB_OTG_DCTL_CGONAK_Pos)
15491#define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk
15492#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
15493#define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos)
15494#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk
15495
15496/******************** Bit definition for USB_OTG_HFIR register ********************/
15497#define USB_OTG_HFIR_FRIVL_Pos (0U)
15498#define USB_OTG_HFIR_FRIVL_Msk (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos)
15499#define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk
15500
15501/******************** Bit definition for USB_OTG_HFNUM register ********************/
15502#define USB_OTG_HFNUM_FRNUM_Pos (0U)
15503#define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos)
15504#define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk
15505#define USB_OTG_HFNUM_FTREM_Pos (16U)
15506#define USB_OTG_HFNUM_FTREM_Msk (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos)
15507#define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk
15508
15509/******************** Bit definition for USB_OTG_DSTS register ********************/
15510#define USB_OTG_DSTS_SUSPSTS_Pos (0U)
15511#define USB_OTG_DSTS_SUSPSTS_Msk (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos)
15512#define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk
15514#define USB_OTG_DSTS_ENUMSPD_Pos (1U)
15515#define USB_OTG_DSTS_ENUMSPD_Msk (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos)
15516#define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk
15517#define USB_OTG_DSTS_ENUMSPD_0 (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos)
15518#define USB_OTG_DSTS_ENUMSPD_1 (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos)
15519#define USB_OTG_DSTS_EERR_Pos (3U)
15520#define USB_OTG_DSTS_EERR_Msk (0x1UL << USB_OTG_DSTS_EERR_Pos)
15521#define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk
15522#define USB_OTG_DSTS_FNSOF_Pos (8U)
15523#define USB_OTG_DSTS_FNSOF_Msk (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos)
15524#define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk
15525
15526/******************** Bit definition for USB_OTG_GAHBCFG register ********************/
15527#define USB_OTG_GAHBCFG_GINT_Pos (0U)
15528#define USB_OTG_GAHBCFG_GINT_Msk (0x1UL << USB_OTG_GAHBCFG_GINT_Pos)
15529#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk
15530#define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
15531#define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
15532#define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk
15533#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
15534#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
15535#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
15536#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
15537#define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
15538#define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
15539#define USB_OTG_GAHBCFG_DMAEN_Msk (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos)
15540#define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk
15541#define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
15542#define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos)
15543#define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk
15544#define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
15545#define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos)
15546#define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk
15547
15548/******************** Bit definition for USB_OTG_GUSBCFG register ********************/
15550#define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
15551#define USB_OTG_GUSBCFG_TOCAL_Msk (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos)
15552#define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk
15553#define USB_OTG_GUSBCFG_TOCAL_0 (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos)
15554#define USB_OTG_GUSBCFG_TOCAL_1 (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos)
15555#define USB_OTG_GUSBCFG_TOCAL_2 (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos)
15556#define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
15557#define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos)
15558#define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk
15559#define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
15560#define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos)
15561#define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk
15562#define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
15563#define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos)
15564#define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk
15565#define USB_OTG_GUSBCFG_TRDT_Pos (10U)
15566#define USB_OTG_GUSBCFG_TRDT_Msk (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos)
15567#define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk
15568#define USB_OTG_GUSBCFG_TRDT_0 (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos)
15569#define USB_OTG_GUSBCFG_TRDT_1 (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos)
15570#define USB_OTG_GUSBCFG_TRDT_2 (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos)
15571#define USB_OTG_GUSBCFG_TRDT_3 (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos)
15572#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
15573#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos)
15574#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk
15575#define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
15576#define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos)
15577#define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk
15578#define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
15579#define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos)
15580#define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk
15581#define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
15582#define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos)
15583#define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk
15584#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
15585#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos)
15586#define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk
15587#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
15588#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos)
15589#define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk
15590#define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
15591#define USB_OTG_GUSBCFG_TSDPS_Msk (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos)
15592#define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk
15593#define USB_OTG_GUSBCFG_PCCI_Pos (23U)
15594#define USB_OTG_GUSBCFG_PCCI_Msk (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos)
15595#define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk
15596#define USB_OTG_GUSBCFG_PTCI_Pos (24U)
15597#define USB_OTG_GUSBCFG_PTCI_Msk (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos)
15598#define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk
15599#define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
15600#define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos)
15601#define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk
15602#define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
15603#define USB_OTG_GUSBCFG_FHMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos)
15604#define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk
15605#define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
15606#define USB_OTG_GUSBCFG_FDMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos)
15607#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk
15608#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
15609#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos)
15610#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk
15611
15612/******************** Bit definition for USB_OTG_GRSTCTL register ********************/
15613#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
15614#define USB_OTG_GRSTCTL_CSRST_Msk (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos)
15615#define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk
15616#define USB_OTG_GRSTCTL_HSRST_Pos (1U)
15617#define USB_OTG_GRSTCTL_HSRST_Msk (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos)
15618#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk
15619#define USB_OTG_GRSTCTL_FCRST_Pos (2U)
15620#define USB_OTG_GRSTCTL_FCRST_Msk (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos)
15621#define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk
15622#define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
15623#define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos)
15624#define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk
15625#define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
15626#define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos)
15627#define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk
15628
15630#define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
15631#define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos)
15632#define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk
15633#define USB_OTG_GRSTCTL_TXFNUM_0 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
15634#define USB_OTG_GRSTCTL_TXFNUM_1 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
15635#define USB_OTG_GRSTCTL_TXFNUM_2 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
15636#define USB_OTG_GRSTCTL_TXFNUM_3 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
15637#define USB_OTG_GRSTCTL_TXFNUM_4 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
15638#define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
15639#define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos)
15640#define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk
15641#define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
15642#define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos)
15643#define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk
15644
15645/******************** Bit definition for USB_OTG_DIEPMSK register ********************/
15646#define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
15647#define USB_OTG_DIEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos)
15648#define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk
15649#define USB_OTG_DIEPMSK_EPDM_Pos (1U)
15650#define USB_OTG_DIEPMSK_EPDM_Msk (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos)
15651#define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk
15652#define USB_OTG_DIEPMSK_TOM_Pos (3U)
15653#define USB_OTG_DIEPMSK_TOM_Msk (0x1UL << USB_OTG_DIEPMSK_TOM_Pos)
15654#define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk
15655#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
15656#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos)
15657#define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk
15658#define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
15659#define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos)
15660#define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk
15661#define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
15662#define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos)
15663#define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk
15664#define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
15665#define USB_OTG_DIEPMSK_TXFURM_Msk (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos)
15666#define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk
15667#define USB_OTG_DIEPMSK_NAKM_Pos (13U)
15668#define USB_OTG_DIEPMSK_NAKM_Msk (0x1UL << USB_OTG_DIEPMSK_NAKM_Pos)
15669#define USB_OTG_DIEPMSK_NAKM USB_OTG_DIEPMSK_NAKM_Msk
15670
15671/******************** Bit definition for USB_OTG_HPTXSTS register ********************/
15672#define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
15673#define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos)
15674#define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk
15675#define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
15676#define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
15677#define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk
15678#define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
15679#define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
15680#define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
15681#define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
15682#define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
15683#define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
15684#define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
15685#define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
15687#define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
15688#define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
15689#define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk
15690#define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
15691#define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
15692#define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
15693#define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
15694#define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
15695#define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
15696#define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
15697#define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
15698
15699/******************** Bit definition for USB_OTG_HAINT register ********************/
15700#define USB_OTG_HAINT_HAINT_Pos (0U)
15701#define USB_OTG_HAINT_HAINT_Msk (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos)
15702#define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk
15703
15704/******************** Bit definition for USB_OTG_DOEPMSK register ********************/
15705#define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
15706#define USB_OTG_DOEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos)
15707#define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk
15708#define USB_OTG_DOEPMSK_EPDM_Pos (1U)
15709#define USB_OTG_DOEPMSK_EPDM_Msk (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos)
15710#define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk
15711#define USB_OTG_DOEPMSK_AHBERRM_Pos (2U)
15712#define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos)
15713#define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk
15714#define USB_OTG_DOEPMSK_STUPM_Pos (3U)
15715#define USB_OTG_DOEPMSK_STUPM_Msk (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos)
15716#define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk
15717#define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
15718#define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos)
15719#define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk
15720#define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U)
15721#define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos)
15722#define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk
15723#define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
15724#define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos)
15725#define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk
15726#define USB_OTG_DOEPMSK_OPEM_Pos (8U)
15727#define USB_OTG_DOEPMSK_OPEM_Msk (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos)
15728#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk
15729#define USB_OTG_DOEPMSK_BOIM_Pos (9U)
15730#define USB_OTG_DOEPMSK_BOIM_Msk (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos)
15731#define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk
15732#define USB_OTG_DOEPMSK_BERRM_Pos (12U)
15733#define USB_OTG_DOEPMSK_BERRM_Msk (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos)
15734#define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk
15735#define USB_OTG_DOEPMSK_NAKM_Pos (13U)
15736#define USB_OTG_DOEPMSK_NAKM_Msk (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos)
15737#define USB_OTG_DOEPMSK_NAKM USB_OTG_DOEPMSK_NAKM_Msk
15738#define USB_OTG_DOEPMSK_NYETM_Pos (14U)
15739#define USB_OTG_DOEPMSK_NYETM_Msk (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos)
15740#define USB_OTG_DOEPMSK_NYETM USB_OTG_DOEPMSK_NYETM_Msk
15741/******************** Bit definition for USB_OTG_GINTSTS register ********************/
15742#define USB_OTG_GINTSTS_CMOD_Pos (0U)
15743#define USB_OTG_GINTSTS_CMOD_Msk (0x1UL << USB_OTG_GINTSTS_CMOD_Pos)
15744#define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk
15745#define USB_OTG_GINTSTS_MMIS_Pos (1U)
15746#define USB_OTG_GINTSTS_MMIS_Msk (0x1UL << USB_OTG_GINTSTS_MMIS_Pos)
15747#define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk
15748#define USB_OTG_GINTSTS_OTGINT_Pos (2U)
15749#define USB_OTG_GINTSTS_OTGINT_Msk (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos)
15750#define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk
15751#define USB_OTG_GINTSTS_SOF_Pos (3U)
15752#define USB_OTG_GINTSTS_SOF_Msk (0x1UL << USB_OTG_GINTSTS_SOF_Pos)
15753#define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk
15754#define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
15755#define USB_OTG_GINTSTS_RXFLVL_Msk (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos)
15756#define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk
15757#define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
15758#define USB_OTG_GINTSTS_NPTXFE_Msk (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos)
15759#define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk
15760#define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
15761#define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos)
15762#define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk
15763#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
15764#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos)
15765#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk
15766#define USB_OTG_GINTSTS_ESUSP_Pos (10U)
15767#define USB_OTG_GINTSTS_ESUSP_Msk (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos)
15768#define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk
15769#define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
15770#define USB_OTG_GINTSTS_USBSUSP_Msk (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos)
15771#define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk
15772#define USB_OTG_GINTSTS_USBRST_Pos (12U)
15773#define USB_OTG_GINTSTS_USBRST_Msk (0x1UL << USB_OTG_GINTSTS_USBRST_Pos)
15774#define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk
15775#define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
15776#define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos)
15777#define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk
15778#define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
15779#define USB_OTG_GINTSTS_ISOODRP_Msk (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos)
15780#define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk
15781#define USB_OTG_GINTSTS_EOPF_Pos (15U)
15782#define USB_OTG_GINTSTS_EOPF_Msk (0x1UL << USB_OTG_GINTSTS_EOPF_Pos)
15783#define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk
15784#define USB_OTG_GINTSTS_IEPINT_Pos (18U)
15785#define USB_OTG_GINTSTS_IEPINT_Msk (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos)
15786#define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk
15787#define USB_OTG_GINTSTS_OEPINT_Pos (19U)
15788#define USB_OTG_GINTSTS_OEPINT_Msk (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos)
15789#define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk
15790#define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
15791#define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos)
15792#define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk
15793#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
15794#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos)
15795#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk
15796#define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
15797#define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos)
15798#define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk
15799#define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
15800#define USB_OTG_GINTSTS_HPRTINT_Msk (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos)
15801#define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk
15802#define USB_OTG_GINTSTS_HCINT_Pos (25U)
15803#define USB_OTG_GINTSTS_HCINT_Msk (0x1UL << USB_OTG_GINTSTS_HCINT_Pos)
15804#define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk
15805#define USB_OTG_GINTSTS_PTXFE_Pos (26U)
15806#define USB_OTG_GINTSTS_PTXFE_Msk (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos)
15807#define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk
15808#define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
15809#define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos)
15810#define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk
15811#define USB_OTG_GINTSTS_DISCINT_Pos (29U)
15812#define USB_OTG_GINTSTS_DISCINT_Msk (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos)
15813#define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk
15814#define USB_OTG_GINTSTS_SRQINT_Pos (30U)
15815#define USB_OTG_GINTSTS_SRQINT_Msk (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos)
15816#define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk
15817#define USB_OTG_GINTSTS_WKUINT_Pos (31U)
15818#define USB_OTG_GINTSTS_WKUINT_Msk (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos)
15819#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk
15820
15821/******************** Bit definition for USB_OTG_GINTMSK register ********************/
15822#define USB_OTG_GINTMSK_MMISM_Pos (1U)
15823#define USB_OTG_GINTMSK_MMISM_Msk (0x1UL << USB_OTG_GINTMSK_MMISM_Pos)
15824#define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk
15825#define USB_OTG_GINTMSK_OTGINT_Pos (2U)
15826#define USB_OTG_GINTMSK_OTGINT_Msk (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos)
15827#define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk
15828#define USB_OTG_GINTMSK_SOFM_Pos (3U)
15829#define USB_OTG_GINTMSK_SOFM_Msk (0x1UL << USB_OTG_GINTMSK_SOFM_Pos)
15830#define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk
15831#define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
15832#define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos)
15833#define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk
15834#define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
15835#define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos)
15836#define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk
15837#define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
15838#define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos)
15839#define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk
15840#define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
15841#define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos)
15842#define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk
15843#define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
15844#define USB_OTG_GINTMSK_ESUSPM_Msk (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos)
15845#define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk
15846#define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
15847#define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos)
15848#define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk
15849#define USB_OTG_GINTMSK_USBRST_Pos (12U)
15850#define USB_OTG_GINTMSK_USBRST_Msk (0x1UL << USB_OTG_GINTMSK_USBRST_Pos)
15851#define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk
15852#define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
15853#define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos)
15854#define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk
15855#define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
15856#define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos)
15857#define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk
15858#define USB_OTG_GINTMSK_EOPFM_Pos (15U)
15859#define USB_OTG_GINTMSK_EOPFM_Msk (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos)
15860#define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk
15861#define USB_OTG_GINTMSK_EPMISM_Pos (17U)
15862#define USB_OTG_GINTMSK_EPMISM_Msk (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos)
15863#define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk
15864#define USB_OTG_GINTMSK_IEPINT_Pos (18U)
15865#define USB_OTG_GINTMSK_IEPINT_Msk (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos)
15866#define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk
15867#define USB_OTG_GINTMSK_OEPINT_Pos (19U)
15868#define USB_OTG_GINTMSK_OEPINT_Msk (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos)
15869#define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk
15870#define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
15871#define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos)
15872#define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk
15873#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
15874#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos)
15875#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk
15876#define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
15877#define USB_OTG_GINTMSK_FSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos)
15878#define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk
15879#define USB_OTG_GINTMSK_PRTIM_Pos (24U)
15880#define USB_OTG_GINTMSK_PRTIM_Msk (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos)
15881#define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk
15882#define USB_OTG_GINTMSK_HCIM_Pos (25U)
15883#define USB_OTG_GINTMSK_HCIM_Msk (0x1UL << USB_OTG_GINTMSK_HCIM_Pos)
15884#define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk
15885#define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
15886#define USB_OTG_GINTMSK_PTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos)
15887#define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk
15888#define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
15889#define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos)
15890#define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk
15891#define USB_OTG_GINTMSK_DISCINT_Pos (29U)
15892#define USB_OTG_GINTMSK_DISCINT_Msk (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos)
15893#define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk
15894#define USB_OTG_GINTMSK_SRQIM_Pos (30U)
15895#define USB_OTG_GINTMSK_SRQIM_Msk (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos)
15896#define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk
15897#define USB_OTG_GINTMSK_WUIM_Pos (31U)
15898#define USB_OTG_GINTMSK_WUIM_Msk (0x1UL << USB_OTG_GINTMSK_WUIM_Pos)
15899#define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk
15900
15901/******************** Bit definition for USB_OTG_DAINT register ********************/
15902#define USB_OTG_DAINT_IEPINT_Pos (0U)
15903#define USB_OTG_DAINT_IEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos)
15904#define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk
15905#define USB_OTG_DAINT_OEPINT_Pos (16U)
15906#define USB_OTG_DAINT_OEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos)
15907#define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk
15908
15909/******************** Bit definition for USB_OTG_HAINTMSK register ********************/
15910#define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
15911#define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos)
15912#define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk
15913
15914/******************** Bit definition for USB_OTG_GRXSTSP register ********************/
15915#define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
15916#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos)
15917#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk
15918#define USB_OTG_GRXSTSP_BCNT_Pos (4U)
15919#define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos)
15920#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk
15921#define USB_OTG_GRXSTSP_DPID_Pos (15U)
15922#define USB_OTG_GRXSTSP_DPID_Msk (0x3UL << USB_OTG_GRXSTSP_DPID_Pos)
15923#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk
15924#define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
15925#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos)
15926#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk
15927
15928/******************** Bit definition for USB_OTG_DAINTMSK register ********************/
15929#define USB_OTG_DAINTMSK_IEPM_Pos (0U)
15930#define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos)
15931#define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk
15932#define USB_OTG_DAINTMSK_OEPM_Pos (16U)
15933#define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos)
15934#define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk
15935
15936/******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
15937#define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
15938#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos)
15939#define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk
15940
15941/******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
15942#define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
15943#define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos)
15944#define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk
15945
15946/******************** Bit definition for OTG register ********************/
15947#define USB_OTG_NPTXFSA_Pos (0U)
15948#define USB_OTG_NPTXFSA_Msk (0xFFFFUL << USB_OTG_NPTXFSA_Pos)
15949#define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk
15950#define USB_OTG_NPTXFD_Pos (16U)
15951#define USB_OTG_NPTXFD_Msk (0xFFFFUL << USB_OTG_NPTXFD_Pos)
15952#define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk
15953#define USB_OTG_TX0FSA_Pos (0U)
15954#define USB_OTG_TX0FSA_Msk (0xFFFFUL << USB_OTG_TX0FSA_Pos)
15955#define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk
15956#define USB_OTG_TX0FD_Pos (16U)
15957#define USB_OTG_TX0FD_Msk (0xFFFFUL << USB_OTG_TX0FD_Pos)
15958#define USB_OTG_TX0FD USB_OTG_TX0FD_Msk
15959
15960/******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
15961#define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
15962#define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos)
15963#define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk
15964
15965/******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
15966#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
15967#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos)
15968#define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk
15970#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
15971#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
15972#define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk
15973#define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
15974#define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
15975#define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
15976#define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
15977#define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
15978#define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
15979#define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
15980#define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
15982#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
15983#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
15984#define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk
15985#define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
15986#define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
15987#define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
15988#define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
15989#define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
15990#define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
15991#define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
15992
15993/******************** Bit definition for USB_OTG_DTHRCTL register ********************/
15994#define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
15995#define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos)
15996#define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk
15997#define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
15998#define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos)
15999#define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk
16001#define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
16002#define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
16003#define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk
16004#define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
16005#define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
16006#define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
16007#define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
16008#define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
16009#define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
16010#define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
16011#define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
16012#define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
16013#define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
16014#define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos)
16015#define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk
16017#define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
16018#define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
16019#define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk
16020#define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
16021#define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
16022#define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
16023#define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
16024#define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
16025#define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
16026#define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
16027#define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
16028#define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
16029#define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
16030#define USB_OTG_DTHRCTL_ARPEN_Msk (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos)
16031#define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk
16032
16033/******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
16034#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
16035#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos)
16036#define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk
16037
16038/******************** Bit definition for USB_OTG_DEACHINT register ********************/
16039#define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
16040#define USB_OTG_DEACHINT_IEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos)
16041#define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk
16042#define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
16043#define USB_OTG_DEACHINT_OEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos)
16044#define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk
16045
16046/******************** Bit definition for USB_OTG_GCCFG register ********************/
16047#define USB_OTG_GCCFG_PWRDWN_Pos (16U)
16048#define USB_OTG_GCCFG_PWRDWN_Msk (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos)
16049#define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk
16050#define USB_OTG_GCCFG_I2CPADEN_Pos (17U)
16051#define USB_OTG_GCCFG_I2CPADEN_Msk (0x1UL << USB_OTG_GCCFG_I2CPADEN_Pos)
16052#define USB_OTG_GCCFG_I2CPADEN USB_OTG_GCCFG_I2CPADEN_Msk
16053#define USB_OTG_GCCFG_VBUSASEN_Pos (18U)
16054#define USB_OTG_GCCFG_VBUSASEN_Msk (0x1UL << USB_OTG_GCCFG_VBUSASEN_Pos)
16055#define USB_OTG_GCCFG_VBUSASEN USB_OTG_GCCFG_VBUSASEN_Msk
16056#define USB_OTG_GCCFG_VBUSBSEN_Pos (19U)
16057#define USB_OTG_GCCFG_VBUSBSEN_Msk (0x1UL << USB_OTG_GCCFG_VBUSBSEN_Pos)
16058#define USB_OTG_GCCFG_VBUSBSEN USB_OTG_GCCFG_VBUSBSEN_Msk
16059#define USB_OTG_GCCFG_SOFOUTEN_Pos (20U)
16060#define USB_OTG_GCCFG_SOFOUTEN_Msk (0x1UL << USB_OTG_GCCFG_SOFOUTEN_Pos)
16061#define USB_OTG_GCCFG_SOFOUTEN USB_OTG_GCCFG_SOFOUTEN_Msk
16062#define USB_OTG_GCCFG_NOVBUSSENS_Pos (21U)
16063#define USB_OTG_GCCFG_NOVBUSSENS_Msk (0x1UL << USB_OTG_GCCFG_NOVBUSSENS_Pos)
16064#define USB_OTG_GCCFG_NOVBUSSENS USB_OTG_GCCFG_NOVBUSSENS_Msk
16065
16066/******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
16067#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
16068#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos)
16069#define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk
16070#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
16071#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos)
16072#define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk
16073
16074/******************** Bit definition for USB_OTG_CID register ********************/
16075#define USB_OTG_CID_PRODUCT_ID_Pos (0U)
16076#define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos)
16077#define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk
16078
16079/******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
16080#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
16081#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos)
16082#define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk
16083#define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
16084#define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos)
16085#define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk
16086#define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
16087#define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos)
16088#define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk
16089#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
16090#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos)
16091#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk
16092#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
16093#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos)
16094#define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk
16095#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
16096#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos)
16097#define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk
16098#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
16099#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos)
16100#define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk
16101#define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
16102#define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos)
16103#define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk
16104#define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
16105#define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos)
16106#define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk
16107
16108/******************** Bit definition for USB_OTG_HPRT register ********************/
16109#define USB_OTG_HPRT_PCSTS_Pos (0U)
16110#define USB_OTG_HPRT_PCSTS_Msk (0x1UL << USB_OTG_HPRT_PCSTS_Pos)
16111#define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk
16112#define USB_OTG_HPRT_PCDET_Pos (1U)
16113#define USB_OTG_HPRT_PCDET_Msk (0x1UL << USB_OTG_HPRT_PCDET_Pos)
16114#define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk
16115#define USB_OTG_HPRT_PENA_Pos (2U)
16116#define USB_OTG_HPRT_PENA_Msk (0x1UL << USB_OTG_HPRT_PENA_Pos)
16117#define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk
16118#define USB_OTG_HPRT_PENCHNG_Pos (3U)
16119#define USB_OTG_HPRT_PENCHNG_Msk (0x1UL << USB_OTG_HPRT_PENCHNG_Pos)
16120#define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk
16121#define USB_OTG_HPRT_POCA_Pos (4U)
16122#define USB_OTG_HPRT_POCA_Msk (0x1UL << USB_OTG_HPRT_POCA_Pos)
16123#define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk
16124#define USB_OTG_HPRT_POCCHNG_Pos (5U)
16125#define USB_OTG_HPRT_POCCHNG_Msk (0x1UL << USB_OTG_HPRT_POCCHNG_Pos)
16126#define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk
16127#define USB_OTG_HPRT_PRES_Pos (6U)
16128#define USB_OTG_HPRT_PRES_Msk (0x1UL << USB_OTG_HPRT_PRES_Pos)
16129#define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk
16130#define USB_OTG_HPRT_PSUSP_Pos (7U)
16131#define USB_OTG_HPRT_PSUSP_Msk (0x1UL << USB_OTG_HPRT_PSUSP_Pos)
16132#define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk
16133#define USB_OTG_HPRT_PRST_Pos (8U)
16134#define USB_OTG_HPRT_PRST_Msk (0x1UL << USB_OTG_HPRT_PRST_Pos)
16135#define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk
16137#define USB_OTG_HPRT_PLSTS_Pos (10U)
16138#define USB_OTG_HPRT_PLSTS_Msk (0x3UL << USB_OTG_HPRT_PLSTS_Pos)
16139#define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk
16140#define USB_OTG_HPRT_PLSTS_0 (0x1UL << USB_OTG_HPRT_PLSTS_Pos)
16141#define USB_OTG_HPRT_PLSTS_1 (0x2UL << USB_OTG_HPRT_PLSTS_Pos)
16142#define USB_OTG_HPRT_PPWR_Pos (12U)
16143#define USB_OTG_HPRT_PPWR_Msk (0x1UL << USB_OTG_HPRT_PPWR_Pos)
16144#define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk
16146#define USB_OTG_HPRT_PTCTL_Pos (13U)
16147#define USB_OTG_HPRT_PTCTL_Msk (0xFUL << USB_OTG_HPRT_PTCTL_Pos)
16148#define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk
16149#define USB_OTG_HPRT_PTCTL_0 (0x1UL << USB_OTG_HPRT_PTCTL_Pos)
16150#define USB_OTG_HPRT_PTCTL_1 (0x2UL << USB_OTG_HPRT_PTCTL_Pos)
16151#define USB_OTG_HPRT_PTCTL_2 (0x4UL << USB_OTG_HPRT_PTCTL_Pos)
16152#define USB_OTG_HPRT_PTCTL_3 (0x8UL << USB_OTG_HPRT_PTCTL_Pos)
16154#define USB_OTG_HPRT_PSPD_Pos (17U)
16155#define USB_OTG_HPRT_PSPD_Msk (0x3UL << USB_OTG_HPRT_PSPD_Pos)
16156#define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk
16157#define USB_OTG_HPRT_PSPD_0 (0x1UL << USB_OTG_HPRT_PSPD_Pos)
16158#define USB_OTG_HPRT_PSPD_1 (0x2UL << USB_OTG_HPRT_PSPD_Pos)
16159
16160/******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
16161#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
16162#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos)
16163#define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk
16164#define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
16165#define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos)
16166#define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk
16167#define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
16168#define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos)
16169#define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk
16170#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
16171#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos)
16172#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk
16173#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
16174#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos)
16175#define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk
16176#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
16177#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos)
16178#define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk
16179#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
16180#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos)
16181#define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk
16182#define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
16183#define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos)
16184#define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk
16185#define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
16186#define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos)
16187#define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk
16188#define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
16189#define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos)
16190#define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk
16191#define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
16192#define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos)
16193#define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk
16194
16195/******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
16196#define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
16197#define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos)
16198#define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk
16199#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
16200#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos)
16201#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk
16202
16203/******************** Bit definition for USB_OTG_DIEPCTL register ********************/
16204#define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
16205#define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos)
16206#define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk
16207#define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
16208#define USB_OTG_DIEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos)
16209#define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk
16210#define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
16211#define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos)
16212#define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk
16213#define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
16214#define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos)
16215#define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk
16217#define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
16218#define USB_OTG_DIEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos)
16219#define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk
16220#define USB_OTG_DIEPCTL_EPTYP_0 (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos)
16221#define USB_OTG_DIEPCTL_EPTYP_1 (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos)
16222#define USB_OTG_DIEPCTL_STALL_Pos (21U)
16223#define USB_OTG_DIEPCTL_STALL_Msk (0x1UL << USB_OTG_DIEPCTL_STALL_Pos)
16224#define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk
16226#define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
16227#define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos)
16228#define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk
16229#define USB_OTG_DIEPCTL_TXFNUM_0 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
16230#define USB_OTG_DIEPCTL_TXFNUM_1 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
16231#define USB_OTG_DIEPCTL_TXFNUM_2 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
16232#define USB_OTG_DIEPCTL_TXFNUM_3 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
16233#define USB_OTG_DIEPCTL_CNAK_Pos (26U)
16234#define USB_OTG_DIEPCTL_CNAK_Msk (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos)
16235#define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk
16236#define USB_OTG_DIEPCTL_SNAK_Pos (27U)
16237#define USB_OTG_DIEPCTL_SNAK_Msk (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos)
16238#define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk
16239#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
16240#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos)
16241#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk
16242#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
16243#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos)
16244#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk
16245#define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
16246#define USB_OTG_DIEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos)
16247#define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk
16248#define USB_OTG_DIEPCTL_EPENA_Pos (31U)
16249#define USB_OTG_DIEPCTL_EPENA_Msk (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos)
16250#define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk
16251
16252/******************** Bit definition for USB_OTG_HCCHAR register ********************/
16253#define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
16254#define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos)
16255#define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk
16257#define USB_OTG_HCCHAR_EPNUM_Pos (11U)
16258#define USB_OTG_HCCHAR_EPNUM_Msk (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos)
16259#define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk
16260#define USB_OTG_HCCHAR_EPNUM_0 (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos)
16261#define USB_OTG_HCCHAR_EPNUM_1 (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos)
16262#define USB_OTG_HCCHAR_EPNUM_2 (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos)
16263#define USB_OTG_HCCHAR_EPNUM_3 (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos)
16264#define USB_OTG_HCCHAR_EPDIR_Pos (15U)
16265#define USB_OTG_HCCHAR_EPDIR_Msk (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos)
16266#define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk
16267#define USB_OTG_HCCHAR_LSDEV_Pos (17U)
16268#define USB_OTG_HCCHAR_LSDEV_Msk (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos)
16269#define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk
16271#define USB_OTG_HCCHAR_EPTYP_Pos (18U)
16272#define USB_OTG_HCCHAR_EPTYP_Msk (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos)
16273#define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk
16274#define USB_OTG_HCCHAR_EPTYP_0 (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos)
16275#define USB_OTG_HCCHAR_EPTYP_1 (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos)
16277#define USB_OTG_HCCHAR_MC_Pos (20U)
16278#define USB_OTG_HCCHAR_MC_Msk (0x3UL << USB_OTG_HCCHAR_MC_Pos)
16279#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk
16280#define USB_OTG_HCCHAR_MC_0 (0x1UL << USB_OTG_HCCHAR_MC_Pos)
16281#define USB_OTG_HCCHAR_MC_1 (0x2UL << USB_OTG_HCCHAR_MC_Pos)
16283#define USB_OTG_HCCHAR_DAD_Pos (22U)
16284#define USB_OTG_HCCHAR_DAD_Msk (0x7FUL << USB_OTG_HCCHAR_DAD_Pos)
16285#define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk
16286#define USB_OTG_HCCHAR_DAD_0 (0x01UL << USB_OTG_HCCHAR_DAD_Pos)
16287#define USB_OTG_HCCHAR_DAD_1 (0x02UL << USB_OTG_HCCHAR_DAD_Pos)
16288#define USB_OTG_HCCHAR_DAD_2 (0x04UL << USB_OTG_HCCHAR_DAD_Pos)
16289#define USB_OTG_HCCHAR_DAD_3 (0x08UL << USB_OTG_HCCHAR_DAD_Pos)
16290#define USB_OTG_HCCHAR_DAD_4 (0x10UL << USB_OTG_HCCHAR_DAD_Pos)
16291#define USB_OTG_HCCHAR_DAD_5 (0x20UL << USB_OTG_HCCHAR_DAD_Pos)
16292#define USB_OTG_HCCHAR_DAD_6 (0x40UL << USB_OTG_HCCHAR_DAD_Pos)
16293#define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
16294#define USB_OTG_HCCHAR_ODDFRM_Msk (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos)
16295#define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk
16296#define USB_OTG_HCCHAR_CHDIS_Pos (30U)
16297#define USB_OTG_HCCHAR_CHDIS_Msk (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos)
16298#define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk
16299#define USB_OTG_HCCHAR_CHENA_Pos (31U)
16300#define USB_OTG_HCCHAR_CHENA_Msk (0x1UL << USB_OTG_HCCHAR_CHENA_Pos)
16301#define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk
16302
16303/******************** Bit definition for USB_OTG_HCSPLT register ********************/
16305#define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
16306#define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos)
16307#define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk
16308#define USB_OTG_HCSPLT_PRTADDR_0 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos)
16309#define USB_OTG_HCSPLT_PRTADDR_1 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos)
16310#define USB_OTG_HCSPLT_PRTADDR_2 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos)
16311#define USB_OTG_HCSPLT_PRTADDR_3 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos)
16312#define USB_OTG_HCSPLT_PRTADDR_4 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos)
16313#define USB_OTG_HCSPLT_PRTADDR_5 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos)
16314#define USB_OTG_HCSPLT_PRTADDR_6 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos)
16316#define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
16317#define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos)
16318#define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk
16319#define USB_OTG_HCSPLT_HUBADDR_0 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos)
16320#define USB_OTG_HCSPLT_HUBADDR_1 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos)
16321#define USB_OTG_HCSPLT_HUBADDR_2 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos)
16322#define USB_OTG_HCSPLT_HUBADDR_3 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos)
16323#define USB_OTG_HCSPLT_HUBADDR_4 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos)
16324#define USB_OTG_HCSPLT_HUBADDR_5 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos)
16325#define USB_OTG_HCSPLT_HUBADDR_6 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos)
16327#define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
16328#define USB_OTG_HCSPLT_XACTPOS_Msk (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos)
16329#define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk
16330#define USB_OTG_HCSPLT_XACTPOS_0 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos)
16331#define USB_OTG_HCSPLT_XACTPOS_1 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos)
16332#define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
16333#define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos)
16334#define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk
16335#define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
16336#define USB_OTG_HCSPLT_SPLITEN_Msk (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos)
16337#define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk
16338
16339/******************** Bit definition for USB_OTG_HCINT register ********************/
16340#define USB_OTG_HCINT_XFRC_Pos (0U)
16341#define USB_OTG_HCINT_XFRC_Msk (0x1UL << USB_OTG_HCINT_XFRC_Pos)
16342#define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk
16343#define USB_OTG_HCINT_CHH_Pos (1U)
16344#define USB_OTG_HCINT_CHH_Msk (0x1UL << USB_OTG_HCINT_CHH_Pos)
16345#define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk
16346#define USB_OTG_HCINT_AHBERR_Pos (2U)
16347#define USB_OTG_HCINT_AHBERR_Msk (0x1UL << USB_OTG_HCINT_AHBERR_Pos)
16348#define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk
16349#define USB_OTG_HCINT_STALL_Pos (3U)
16350#define USB_OTG_HCINT_STALL_Msk (0x1UL << USB_OTG_HCINT_STALL_Pos)
16351#define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk
16352#define USB_OTG_HCINT_NAK_Pos (4U)
16353#define USB_OTG_HCINT_NAK_Msk (0x1UL << USB_OTG_HCINT_NAK_Pos)
16354#define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk
16355#define USB_OTG_HCINT_ACK_Pos (5U)
16356#define USB_OTG_HCINT_ACK_Msk (0x1UL << USB_OTG_HCINT_ACK_Pos)
16357#define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk
16358#define USB_OTG_HCINT_NYET_Pos (6U)
16359#define USB_OTG_HCINT_NYET_Msk (0x1UL << USB_OTG_HCINT_NYET_Pos)
16360#define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk
16361#define USB_OTG_HCINT_TXERR_Pos (7U)
16362#define USB_OTG_HCINT_TXERR_Msk (0x1UL << USB_OTG_HCINT_TXERR_Pos)
16363#define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk
16364#define USB_OTG_HCINT_BBERR_Pos (8U)
16365#define USB_OTG_HCINT_BBERR_Msk (0x1UL << USB_OTG_HCINT_BBERR_Pos)
16366#define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk
16367#define USB_OTG_HCINT_FRMOR_Pos (9U)
16368#define USB_OTG_HCINT_FRMOR_Msk (0x1UL << USB_OTG_HCINT_FRMOR_Pos)
16369#define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk
16370#define USB_OTG_HCINT_DTERR_Pos (10U)
16371#define USB_OTG_HCINT_DTERR_Msk (0x1UL << USB_OTG_HCINT_DTERR_Pos)
16372#define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk
16373
16374/******************** Bit definition for USB_OTG_DIEPINT register ********************/
16375#define USB_OTG_DIEPINT_XFRC_Pos (0U)
16376#define USB_OTG_DIEPINT_XFRC_Msk (0x1UL << USB_OTG_DIEPINT_XFRC_Pos)
16377#define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk
16378#define USB_OTG_DIEPINT_EPDISD_Pos (1U)
16379#define USB_OTG_DIEPINT_EPDISD_Msk (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos)
16380#define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk
16381#define USB_OTG_DIEPINT_AHBERR_Pos (2U)
16382#define USB_OTG_DIEPINT_AHBERR_Msk (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos)
16383#define USB_OTG_DIEPINT_AHBERR USB_OTG_DIEPINT_AHBERR_Msk
16384#define USB_OTG_DIEPINT_TOC_Pos (3U)
16385#define USB_OTG_DIEPINT_TOC_Msk (0x1UL << USB_OTG_DIEPINT_TOC_Pos)
16386#define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk
16387#define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
16388#define USB_OTG_DIEPINT_ITTXFE_Msk (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos)
16389#define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk
16390#define USB_OTG_DIEPINT_INEPNM_Pos (5U)
16391#define USB_OTG_DIEPINT_INEPNM_Msk (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos)
16392#define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk
16393#define USB_OTG_DIEPINT_INEPNE_Pos (6U)
16394#define USB_OTG_DIEPINT_INEPNE_Msk (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos)
16395#define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk
16396#define USB_OTG_DIEPINT_TXFE_Pos (7U)
16397#define USB_OTG_DIEPINT_TXFE_Msk (0x1UL << USB_OTG_DIEPINT_TXFE_Pos)
16398#define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk
16399#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
16400#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos)
16401#define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk
16402#define USB_OTG_DIEPINT_BNA_Pos (9U)
16403#define USB_OTG_DIEPINT_BNA_Msk (0x1UL << USB_OTG_DIEPINT_BNA_Pos)
16404#define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk
16405#define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
16406#define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos)
16407#define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk
16408#define USB_OTG_DIEPINT_BERR_Pos (12U)
16409#define USB_OTG_DIEPINT_BERR_Msk (0x1UL << USB_OTG_DIEPINT_BERR_Pos)
16410#define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk
16411#define USB_OTG_DIEPINT_NAK_Pos (13U)
16412#define USB_OTG_DIEPINT_NAK_Msk (0x1UL << USB_OTG_DIEPINT_NAK_Pos)
16413#define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk
16414
16415/******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
16416#define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
16417#define USB_OTG_HCINTMSK_XFRCM_Msk (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos)
16418#define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk
16419#define USB_OTG_HCINTMSK_CHHM_Pos (1U)
16420#define USB_OTG_HCINTMSK_CHHM_Msk (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos)
16421#define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk
16422#define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
16423#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos)
16424#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk
16425#define USB_OTG_HCINTMSK_STALLM_Pos (3U)
16426#define USB_OTG_HCINTMSK_STALLM_Msk (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos)
16427#define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk
16428#define USB_OTG_HCINTMSK_NAKM_Pos (4U)
16429#define USB_OTG_HCINTMSK_NAKM_Msk (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos)
16430#define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk
16431#define USB_OTG_HCINTMSK_ACKM_Pos (5U)
16432#define USB_OTG_HCINTMSK_ACKM_Msk (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos)
16433#define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk
16434#define USB_OTG_HCINTMSK_NYET_Pos (6U)
16435#define USB_OTG_HCINTMSK_NYET_Msk (0x1UL << USB_OTG_HCINTMSK_NYET_Pos)
16436#define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk
16437#define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
16438#define USB_OTG_HCINTMSK_TXERRM_Msk (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos)
16439#define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk
16440#define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
16441#define USB_OTG_HCINTMSK_BBERRM_Msk (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos)
16442#define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk
16443#define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
16444#define USB_OTG_HCINTMSK_FRMORM_Msk (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos)
16445#define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk
16446#define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
16447#define USB_OTG_HCINTMSK_DTERRM_Msk (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos)
16448#define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk
16449
16450/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
16452#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
16453#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos)
16454#define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk
16455#define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
16456#define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos)
16457#define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk
16458#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
16459#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos)
16460#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk
16461/******************** Bit definition for USB_OTG_HCTSIZ register ********************/
16462#define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
16463#define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos)
16464#define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk
16465#define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
16466#define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos)
16467#define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk
16468#define USB_OTG_HCTSIZ_DOPING_Pos (31U)
16469#define USB_OTG_HCTSIZ_DOPING_Msk (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos)
16470#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk
16471#define USB_OTG_HCTSIZ_DPID_Pos (29U)
16472#define USB_OTG_HCTSIZ_DPID_Msk (0x3UL << USB_OTG_HCTSIZ_DPID_Pos)
16473#define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk
16474#define USB_OTG_HCTSIZ_DPID_0 (0x1UL << USB_OTG_HCTSIZ_DPID_Pos)
16475#define USB_OTG_HCTSIZ_DPID_1 (0x2UL << USB_OTG_HCTSIZ_DPID_Pos)
16476
16477/******************** Bit definition for USB_OTG_DIEPDMA register ********************/
16478#define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
16479#define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos)
16480#define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk
16481
16482/******************** Bit definition for USB_OTG_HCDMA register ********************/
16483#define USB_OTG_HCDMA_DMAADDR_Pos (0U)
16484#define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos)
16485#define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk
16486
16487/******************** Bit definition for USB_OTG_DTXFSTS register ********************/
16488#define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
16489#define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos)
16490#define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk
16491
16492/******************** Bit definition for USB_OTG_DIEPTXF register ********************/
16493#define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
16494#define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos)
16495#define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk
16496#define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
16497#define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos)
16498#define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk
16499
16500/******************** Bit definition for USB_OTG_DOEPCTL register ********************/
16502#define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
16503#define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos)
16504#define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk
16505#define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
16506#define USB_OTG_DOEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos)
16507#define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk
16508#define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
16509#define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos)
16510#define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk
16511#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
16512#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos)
16513#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk
16514#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
16515#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos)
16516#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk
16517#define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
16518#define USB_OTG_DOEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos)
16519#define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk
16520#define USB_OTG_DOEPCTL_EPTYP_0 (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos)
16521#define USB_OTG_DOEPCTL_EPTYP_1 (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos)
16522#define USB_OTG_DOEPCTL_SNPM_Pos (20U)
16523#define USB_OTG_DOEPCTL_SNPM_Msk (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos)
16524#define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk
16525#define USB_OTG_DOEPCTL_STALL_Pos (21U)
16526#define USB_OTG_DOEPCTL_STALL_Msk (0x1UL << USB_OTG_DOEPCTL_STALL_Pos)
16527#define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk
16528#define USB_OTG_DOEPCTL_CNAK_Pos (26U)
16529#define USB_OTG_DOEPCTL_CNAK_Msk (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos)
16530#define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk
16531#define USB_OTG_DOEPCTL_SNAK_Pos (27U)
16532#define USB_OTG_DOEPCTL_SNAK_Msk (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos)
16533#define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk
16534#define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
16535#define USB_OTG_DOEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos)
16536#define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk
16537#define USB_OTG_DOEPCTL_EPENA_Pos (31U)
16538#define USB_OTG_DOEPCTL_EPENA_Msk (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos)
16539#define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk
16540
16541/******************** Bit definition for USB_OTG_DOEPINT register ********************/
16542#define USB_OTG_DOEPINT_XFRC_Pos (0U)
16543#define USB_OTG_DOEPINT_XFRC_Msk (0x1UL << USB_OTG_DOEPINT_XFRC_Pos)
16544#define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk
16545#define USB_OTG_DOEPINT_EPDISD_Pos (1U)
16546#define USB_OTG_DOEPINT_EPDISD_Msk (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos)
16547#define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk
16548#define USB_OTG_DOEPINT_AHBERR_Pos (2U)
16549#define USB_OTG_DOEPINT_AHBERR_Msk (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos)
16550#define USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk
16551#define USB_OTG_DOEPINT_STUP_Pos (3U)
16552#define USB_OTG_DOEPINT_STUP_Msk (0x1UL << USB_OTG_DOEPINT_STUP_Pos)
16553#define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk
16554#define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
16555#define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos)
16556#define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk
16557#define USB_OTG_DOEPINT_OTEPSPR_Pos (5U)
16558#define USB_OTG_DOEPINT_OTEPSPR_Msk (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos)
16559#define USB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_Msk
16560#define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
16561#define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos)
16562#define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk
16563#define USB_OTG_DOEPINT_OUTPKTERR_Pos (8U)
16564#define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos)
16565#define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk
16566#define USB_OTG_DOEPINT_NAK_Pos (13U)
16567#define USB_OTG_DOEPINT_NAK_Msk (0x1UL << USB_OTG_DOEPINT_NAK_Pos)
16568#define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk
16569#define USB_OTG_DOEPINT_NYET_Pos (14U)
16570#define USB_OTG_DOEPINT_NYET_Msk (0x1UL << USB_OTG_DOEPINT_NYET_Pos)
16571#define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk
16572#define USB_OTG_DOEPINT_STPKTRX_Pos (15U)
16573#define USB_OTG_DOEPINT_STPKTRX_Msk (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos)
16574#define USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk
16575/******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
16577#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
16578#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos)
16579#define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk
16580#define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
16581#define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos)
16582#define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk
16584#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
16585#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
16586#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk
16587#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
16588#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
16589
16590/******************** Bit definition for PCGCCTL register ********************/
16591#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
16592#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos)
16593#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk
16594#define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
16595#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos)
16596#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk
16597#define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
16598#define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos)
16599#define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk
16600
16601/* Legacy define */
16602/******************** Bit definition for OTG register ********************/
16603#define USB_OTG_CHNUM_Pos (0U)
16604#define USB_OTG_CHNUM_Msk (0xFUL << USB_OTG_CHNUM_Pos)
16605#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk
16606#define USB_OTG_CHNUM_0 (0x1UL << USB_OTG_CHNUM_Pos)
16607#define USB_OTG_CHNUM_1 (0x2UL << USB_OTG_CHNUM_Pos)
16608#define USB_OTG_CHNUM_2 (0x4UL << USB_OTG_CHNUM_Pos)
16609#define USB_OTG_CHNUM_3 (0x8UL << USB_OTG_CHNUM_Pos)
16610#define USB_OTG_BCNT_Pos (4U)
16611#define USB_OTG_BCNT_Msk (0x7FFUL << USB_OTG_BCNT_Pos)
16612#define USB_OTG_BCNT USB_OTG_BCNT_Msk
16614#define USB_OTG_DPID_Pos (15U)
16615#define USB_OTG_DPID_Msk (0x3UL << USB_OTG_DPID_Pos)
16616#define USB_OTG_DPID USB_OTG_DPID_Msk
16617#define USB_OTG_DPID_0 (0x1UL << USB_OTG_DPID_Pos)
16618#define USB_OTG_DPID_1 (0x2UL << USB_OTG_DPID_Pos)
16620#define USB_OTG_PKTSTS_Pos (17U)
16621#define USB_OTG_PKTSTS_Msk (0xFUL << USB_OTG_PKTSTS_Pos)
16622#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk
16623#define USB_OTG_PKTSTS_0 (0x1UL << USB_OTG_PKTSTS_Pos)
16624#define USB_OTG_PKTSTS_1 (0x2UL << USB_OTG_PKTSTS_Pos)
16625#define USB_OTG_PKTSTS_2 (0x4UL << USB_OTG_PKTSTS_Pos)
16626#define USB_OTG_PKTSTS_3 (0x8UL << USB_OTG_PKTSTS_Pos)
16628#define USB_OTG_EPNUM_Pos (0U)
16629#define USB_OTG_EPNUM_Msk (0xFUL << USB_OTG_EPNUM_Pos)
16630#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk
16631#define USB_OTG_EPNUM_0 (0x1UL << USB_OTG_EPNUM_Pos)
16632#define USB_OTG_EPNUM_1 (0x2UL << USB_OTG_EPNUM_Pos)
16633#define USB_OTG_EPNUM_2 (0x4UL << USB_OTG_EPNUM_Pos)
16634#define USB_OTG_EPNUM_3 (0x8UL << USB_OTG_EPNUM_Pos)
16636#define USB_OTG_FRMNUM_Pos (21U)
16637#define USB_OTG_FRMNUM_Msk (0xFUL << USB_OTG_FRMNUM_Pos)
16638#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk
16639#define USB_OTG_FRMNUM_0 (0x1UL << USB_OTG_FRMNUM_Pos)
16640#define USB_OTG_FRMNUM_1 (0x2UL << USB_OTG_FRMNUM_Pos)
16641#define USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos)
16642#define USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos)
16646
16650
16654
16655/******************************* ADC Instances ********************************/
16656#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
16657 ((INSTANCE) == ADC2) || \
16658 ((INSTANCE) == ADC3))
16660#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
16662#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)
16663
16664/******************************* CAN Instances ********************************/
16665#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
16666 ((INSTANCE) == CAN2))
16667/******************************* CRC Instances ********************************/
16668#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
16669
16670/******************************* DAC Instances ********************************/
16671#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
16672
16673/******************************* DCMI Instances *******************************/
16674#define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
16675
16676/******************************* DMA2D Instances *******************************/
16677#define IS_DMA2D_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMA2D)
16678
16679/******************************** DMA Instances *******************************/
16680#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
16681 ((INSTANCE) == DMA1_Stream1) || \
16682 ((INSTANCE) == DMA1_Stream2) || \
16683 ((INSTANCE) == DMA1_Stream3) || \
16684 ((INSTANCE) == DMA1_Stream4) || \
16685 ((INSTANCE) == DMA1_Stream5) || \
16686 ((INSTANCE) == DMA1_Stream6) || \
16687 ((INSTANCE) == DMA1_Stream7) || \
16688 ((INSTANCE) == DMA2_Stream0) || \
16689 ((INSTANCE) == DMA2_Stream1) || \
16690 ((INSTANCE) == DMA2_Stream2) || \
16691 ((INSTANCE) == DMA2_Stream3) || \
16692 ((INSTANCE) == DMA2_Stream4) || \
16693 ((INSTANCE) == DMA2_Stream5) || \
16694 ((INSTANCE) == DMA2_Stream6) || \
16695 ((INSTANCE) == DMA2_Stream7))
16696
16697/******************************* GPIO Instances *******************************/
16698#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
16699 ((INSTANCE) == GPIOB) || \
16700 ((INSTANCE) == GPIOC) || \
16701 ((INSTANCE) == GPIOD) || \
16702 ((INSTANCE) == GPIOE) || \
16703 ((INSTANCE) == GPIOF) || \
16704 ((INSTANCE) == GPIOG) || \
16705 ((INSTANCE) == GPIOH) || \
16706 ((INSTANCE) == GPIOI) || \
16707 ((INSTANCE) == GPIOJ) || \
16708 ((INSTANCE) == GPIOK))
16709
16710/******************************** I2C Instances *******************************/
16711#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
16712 ((INSTANCE) == I2C2) || \
16713 ((INSTANCE) == I2C3))
16714
16715/******************************* SMBUS Instances ******************************/
16716#define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
16717
16718/******************************** I2S Instances *******************************/
16720#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
16721 ((INSTANCE) == SPI3))
16722
16723/*************************** I2S Extended Instances ***************************/
16724#define IS_I2S_EXT_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2S2ext)|| \
16725 ((INSTANCE) == I2S3ext))
16726/* Legacy Defines */
16727#define IS_I2S_ALL_INSTANCE_EXT IS_I2S_EXT_ALL_INSTANCE
16728
16729/****************************** LTDC Instances ********************************/
16730#define IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC)
16731/******************************* RNG Instances ********************************/
16732#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
16733
16734/****************************** RTC Instances *********************************/
16735#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
16736
16737/******************************* SAI Instances ********************************/
16738#define IS_SAI_ALL_INSTANCE(PERIPH) (((PERIPH) == SAI1_Block_A) || \
16739 ((PERIPH) == SAI1_Block_B))
16740/* Legacy define */
16742#define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
16743
16744/******************************** SPI Instances *******************************/
16745#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
16746 ((INSTANCE) == SPI2) || \
16747 ((INSTANCE) == SPI3) || \
16748 ((INSTANCE) == SPI4) || \
16749 ((INSTANCE) == SPI5) || \
16750 ((INSTANCE) == SPI6))
16751
16752
16753/****************** TIM Instances : All supported instances *******************/
16754#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16755 ((INSTANCE) == TIM2) || \
16756 ((INSTANCE) == TIM3) || \
16757 ((INSTANCE) == TIM4) || \
16758 ((INSTANCE) == TIM5) || \
16759 ((INSTANCE) == TIM6) || \
16760 ((INSTANCE) == TIM7) || \
16761 ((INSTANCE) == TIM8) || \
16762 ((INSTANCE) == TIM9) || \
16763 ((INSTANCE) == TIM10)|| \
16764 ((INSTANCE) == TIM11)|| \
16765 ((INSTANCE) == TIM12)|| \
16766 ((INSTANCE) == TIM13)|| \
16767 ((INSTANCE) == TIM14))
16768
16769/************* TIM Instances : at least 1 capture/compare channel *************/
16770#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16771 ((INSTANCE) == TIM2) || \
16772 ((INSTANCE) == TIM3) || \
16773 ((INSTANCE) == TIM4) || \
16774 ((INSTANCE) == TIM5) || \
16775 ((INSTANCE) == TIM8) || \
16776 ((INSTANCE) == TIM9) || \
16777 ((INSTANCE) == TIM10) || \
16778 ((INSTANCE) == TIM11) || \
16779 ((INSTANCE) == TIM12) || \
16780 ((INSTANCE) == TIM13) || \
16781 ((INSTANCE) == TIM14))
16782
16783/************ TIM Instances : at least 2 capture/compare channels *************/
16784#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16785 ((INSTANCE) == TIM2) || \
16786 ((INSTANCE) == TIM3) || \
16787 ((INSTANCE) == TIM4) || \
16788 ((INSTANCE) == TIM5) || \
16789 ((INSTANCE) == TIM8) || \
16790 ((INSTANCE) == TIM9) || \
16791 ((INSTANCE) == TIM12))
16792
16793/************ TIM Instances : at least 3 capture/compare channels *************/
16794#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16795 ((INSTANCE) == TIM2) || \
16796 ((INSTANCE) == TIM3) || \
16797 ((INSTANCE) == TIM4) || \
16798 ((INSTANCE) == TIM5) || \
16799 ((INSTANCE) == TIM8))
16800
16801/************ TIM Instances : at least 4 capture/compare channels *************/
16802#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16803 ((INSTANCE) == TIM2) || \
16804 ((INSTANCE) == TIM3) || \
16805 ((INSTANCE) == TIM4) || \
16806 ((INSTANCE) == TIM5) || \
16807 ((INSTANCE) == TIM8))
16808
16809/******************** TIM Instances : Advanced-control timers *****************/
16810#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16811 ((INSTANCE) == TIM8))
16812
16813/******************* TIM Instances : Timer input XOR function *****************/
16814#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16815 ((INSTANCE) == TIM2) || \
16816 ((INSTANCE) == TIM3) || \
16817 ((INSTANCE) == TIM4) || \
16818 ((INSTANCE) == TIM5) || \
16819 ((INSTANCE) == TIM8))
16820
16821/****************** TIM Instances : DMA requests generation (UDE) *************/
16822#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16823 ((INSTANCE) == TIM2) || \
16824 ((INSTANCE) == TIM3) || \
16825 ((INSTANCE) == TIM4) || \
16826 ((INSTANCE) == TIM5) || \
16827 ((INSTANCE) == TIM6) || \
16828 ((INSTANCE) == TIM7) || \
16829 ((INSTANCE) == TIM8))
16830
16831/************ TIM Instances : DMA requests generation (CCxDE) *****************/
16832#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16833 ((INSTANCE) == TIM2) || \
16834 ((INSTANCE) == TIM3) || \
16835 ((INSTANCE) == TIM4) || \
16836 ((INSTANCE) == TIM5) || \
16837 ((INSTANCE) == TIM8))
16838
16839/************ TIM Instances : DMA requests generation (COMDE) *****************/
16840#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16841 ((INSTANCE) == TIM2) || \
16842 ((INSTANCE) == TIM3) || \
16843 ((INSTANCE) == TIM4) || \
16844 ((INSTANCE) == TIM5) || \
16845 ((INSTANCE) == TIM8))
16846
16847/******************** TIM Instances : DMA burst feature ***********************/
16848#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16849 ((INSTANCE) == TIM2) || \
16850 ((INSTANCE) == TIM3) || \
16851 ((INSTANCE) == TIM4) || \
16852 ((INSTANCE) == TIM5) || \
16853 ((INSTANCE) == TIM8))
16854
16855/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
16856#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16857 ((INSTANCE) == TIM2) || \
16858 ((INSTANCE) == TIM3) || \
16859 ((INSTANCE) == TIM4) || \
16860 ((INSTANCE) == TIM5) || \
16861 ((INSTANCE) == TIM6) || \
16862 ((INSTANCE) == TIM7) || \
16863 ((INSTANCE) == TIM8))
16864
16865/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
16866#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16867 ((INSTANCE) == TIM2) || \
16868 ((INSTANCE) == TIM3) || \
16869 ((INSTANCE) == TIM4) || \
16870 ((INSTANCE) == TIM5) || \
16871 ((INSTANCE) == TIM8) || \
16872 ((INSTANCE) == TIM9) || \
16873 ((INSTANCE) == TIM12))
16874/********************** TIM Instances : 32 bit Counter ************************/
16875#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
16876 ((INSTANCE) == TIM5))
16877
16878/***************** TIM Instances : external trigger input available ************/
16879#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16880 ((INSTANCE) == TIM2) || \
16881 ((INSTANCE) == TIM3) || \
16882 ((INSTANCE) == TIM4) || \
16883 ((INSTANCE) == TIM5) || \
16884 ((INSTANCE) == TIM8))
16885
16886/****************** TIM Instances : remapping capability **********************/
16887#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
16888 ((INSTANCE) == TIM5) || \
16889 ((INSTANCE) == TIM11))
16890
16891/******************* TIM Instances : output(s) available **********************/
16892#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
16893 ((((INSTANCE) == TIM1) && \
16894 (((CHANNEL) == TIM_CHANNEL_1) || \
16895 ((CHANNEL) == TIM_CHANNEL_2) || \
16896 ((CHANNEL) == TIM_CHANNEL_3) || \
16897 ((CHANNEL) == TIM_CHANNEL_4))) \
16898 || \
16899 (((INSTANCE) == TIM2) && \
16900 (((CHANNEL) == TIM_CHANNEL_1) || \
16901 ((CHANNEL) == TIM_CHANNEL_2) || \
16902 ((CHANNEL) == TIM_CHANNEL_3) || \
16903 ((CHANNEL) == TIM_CHANNEL_4))) \
16904 || \
16905 (((INSTANCE) == TIM3) && \
16906 (((CHANNEL) == TIM_CHANNEL_1) || \
16907 ((CHANNEL) == TIM_CHANNEL_2) || \
16908 ((CHANNEL) == TIM_CHANNEL_3) || \
16909 ((CHANNEL) == TIM_CHANNEL_4))) \
16910 || \
16911 (((INSTANCE) == TIM4) && \
16912 (((CHANNEL) == TIM_CHANNEL_1) || \
16913 ((CHANNEL) == TIM_CHANNEL_2) || \
16914 ((CHANNEL) == TIM_CHANNEL_3) || \
16915 ((CHANNEL) == TIM_CHANNEL_4))) \
16916 || \
16917 (((INSTANCE) == TIM5) && \
16918 (((CHANNEL) == TIM_CHANNEL_1) || \
16919 ((CHANNEL) == TIM_CHANNEL_2) || \
16920 ((CHANNEL) == TIM_CHANNEL_3) || \
16921 ((CHANNEL) == TIM_CHANNEL_4))) \
16922 || \
16923 (((INSTANCE) == TIM8) && \
16924 (((CHANNEL) == TIM_CHANNEL_1) || \
16925 ((CHANNEL) == TIM_CHANNEL_2) || \
16926 ((CHANNEL) == TIM_CHANNEL_3) || \
16927 ((CHANNEL) == TIM_CHANNEL_4))) \
16928 || \
16929 (((INSTANCE) == TIM9) && \
16930 (((CHANNEL) == TIM_CHANNEL_1) || \
16931 ((CHANNEL) == TIM_CHANNEL_2))) \
16932 || \
16933 (((INSTANCE) == TIM10) && \
16934 (((CHANNEL) == TIM_CHANNEL_1))) \
16935 || \
16936 (((INSTANCE) == TIM11) && \
16937 (((CHANNEL) == TIM_CHANNEL_1))) \
16938 || \
16939 (((INSTANCE) == TIM12) && \
16940 (((CHANNEL) == TIM_CHANNEL_1) || \
16941 ((CHANNEL) == TIM_CHANNEL_2))) \
16942 || \
16943 (((INSTANCE) == TIM13) && \
16944 (((CHANNEL) == TIM_CHANNEL_1))) \
16945 || \
16946 (((INSTANCE) == TIM14) && \
16947 (((CHANNEL) == TIM_CHANNEL_1))))
16948
16949/************ TIM Instances : complementary output(s) available ***************/
16950#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
16951 ((((INSTANCE) == TIM1) && \
16952 (((CHANNEL) == TIM_CHANNEL_1) || \
16953 ((CHANNEL) == TIM_CHANNEL_2) || \
16954 ((CHANNEL) == TIM_CHANNEL_3))) \
16955 || \
16956 (((INSTANCE) == TIM8) && \
16957 (((CHANNEL) == TIM_CHANNEL_1) || \
16958 ((CHANNEL) == TIM_CHANNEL_2) || \
16959 ((CHANNEL) == TIM_CHANNEL_3))))
16960
16961/****************** TIM Instances : supporting counting mode selection ********/
16962#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16963 ((INSTANCE) == TIM2) || \
16964 ((INSTANCE) == TIM3) || \
16965 ((INSTANCE) == TIM4) || \
16966 ((INSTANCE) == TIM5) || \
16967 ((INSTANCE) == TIM8))
16968
16969/****************** TIM Instances : supporting clock division *****************/
16970#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16971 ((INSTANCE) == TIM2) || \
16972 ((INSTANCE) == TIM3) || \
16973 ((INSTANCE) == TIM4) || \
16974 ((INSTANCE) == TIM5) || \
16975 ((INSTANCE) == TIM8) || \
16976 ((INSTANCE) == TIM9) || \
16977 ((INSTANCE) == TIM10)|| \
16978 ((INSTANCE) == TIM11)|| \
16979 ((INSTANCE) == TIM12)|| \
16980 ((INSTANCE) == TIM13)|| \
16981 ((INSTANCE) == TIM14))
16982
16983/****************** TIM Instances : supporting commutation event generation ***/
16984#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)|| \
16985 ((INSTANCE) == TIM8))
16986
16987
16988/****************** TIM Instances : supporting OCxREF clear *******************/
16989#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16990 ((INSTANCE) == TIM2) || \
16991 ((INSTANCE) == TIM3) || \
16992 ((INSTANCE) == TIM4) || \
16993 ((INSTANCE) == TIM5) || \
16994 ((INSTANCE) == TIM8))
16995
16996/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
16997#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16998 ((INSTANCE) == TIM2) || \
16999 ((INSTANCE) == TIM3) || \
17000 ((INSTANCE) == TIM4) || \
17001 ((INSTANCE) == TIM5) || \
17002 ((INSTANCE) == TIM8) || \
17003 ((INSTANCE) == TIM9) || \
17004 ((INSTANCE) == TIM12))
17005
17006/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
17007#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17008 ((INSTANCE) == TIM2) || \
17009 ((INSTANCE) == TIM3) || \
17010 ((INSTANCE) == TIM4) || \
17011 ((INSTANCE) == TIM5) || \
17012 ((INSTANCE) == TIM8))
17013
17014/****** TIM Instances : supporting external clock mode 1 for TIX inputs ******/
17015#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17016 ((INSTANCE) == TIM2) || \
17017 ((INSTANCE) == TIM3) || \
17018 ((INSTANCE) == TIM4) || \
17019 ((INSTANCE) == TIM5) || \
17020 ((INSTANCE) == TIM8) || \
17021 ((INSTANCE) == TIM9) || \
17022 ((INSTANCE) == TIM12))
17023
17024/********** TIM Instances : supporting internal trigger inputs(ITRX) *********/
17025#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17026 ((INSTANCE) == TIM2) || \
17027 ((INSTANCE) == TIM3) || \
17028 ((INSTANCE) == TIM4) || \
17029 ((INSTANCE) == TIM5) || \
17030 ((INSTANCE) == TIM8) || \
17031 ((INSTANCE) == TIM9) || \
17032 ((INSTANCE) == TIM12))
17033
17034/****************** TIM Instances : supporting repetition counter *************/
17035#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17036 ((INSTANCE) == TIM8))
17037
17038/****************** TIM Instances : supporting encoder interface **************/
17039#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17040 ((INSTANCE) == TIM2) || \
17041 ((INSTANCE) == TIM3) || \
17042 ((INSTANCE) == TIM4) || \
17043 ((INSTANCE) == TIM5) || \
17044 ((INSTANCE) == TIM8) || \
17045 ((INSTANCE) == TIM9) || \
17046 ((INSTANCE) == TIM12))
17047/****************** TIM Instances : supporting Hall sensor interface **********/
17048#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17049 ((INSTANCE) == TIM2) || \
17050 ((INSTANCE) == TIM3) || \
17051 ((INSTANCE) == TIM4) || \
17052 ((INSTANCE) == TIM5) || \
17053 ((INSTANCE) == TIM8))
17054/****************** TIM Instances : supporting the break function *************/
17055#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17056 ((INSTANCE) == TIM8))
17057
17058/******************** USART Instances : Synchronous mode **********************/
17059#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
17060 ((INSTANCE) == USART2) || \
17061 ((INSTANCE) == USART3) || \
17062 ((INSTANCE) == USART6))
17063
17064/******************** UART Instances : Half-Duplex mode **********************/
17065#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
17066 ((INSTANCE) == USART2) || \
17067 ((INSTANCE) == USART3) || \
17068 ((INSTANCE) == UART4) || \
17069 ((INSTANCE) == UART5) || \
17070 ((INSTANCE) == USART6) || \
17071 ((INSTANCE) == UART7) || \
17072 ((INSTANCE) == UART8))
17073
17074/* Legacy defines */
17075#define IS_UART_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
17076
17077/****************** UART Instances : Hardware Flow control ********************/
17078#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
17079 ((INSTANCE) == USART2) || \
17080 ((INSTANCE) == USART3) || \
17081 ((INSTANCE) == USART6))
17082/******************** UART Instances : LIN mode **********************/
17083#define IS_UART_LIN_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
17084
17085/********************* UART Instances : Smart card mode ***********************/
17086#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
17087 ((INSTANCE) == USART2) || \
17088 ((INSTANCE) == USART3) || \
17089 ((INSTANCE) == USART6))
17090
17091/*********************** UART Instances : IRDA mode ***************************/
17092#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
17093 ((INSTANCE) == USART2) || \
17094 ((INSTANCE) == USART3) || \
17095 ((INSTANCE) == UART4) || \
17096 ((INSTANCE) == UART5) || \
17097 ((INSTANCE) == USART6) || \
17098 ((INSTANCE) == UART7) || \
17099 ((INSTANCE) == UART8))
17100
17101/*********************** PCD Instances ****************************************/
17102#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
17103 ((INSTANCE) == USB_OTG_HS))
17104
17105/*********************** HCD Instances ****************************************/
17106#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
17107 ((INSTANCE) == USB_OTG_HS))
17108
17109/****************************** SDIO Instances ********************************/
17110#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
17111
17112/****************************** IWDG Instances ********************************/
17113#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
17114
17115/****************************** WWDG Instances ********************************/
17116#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
17117
17118/****************************** USB Exported Constants ************************/
17119#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8U
17120#define USB_OTG_FS_MAX_IN_ENDPOINTS 4U /* Including EP0 */
17121#define USB_OTG_FS_MAX_OUT_ENDPOINTS 4U /* Including EP0 */
17122#define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
17123
17124/*
17125 * @brief Specific devices reset values definitions
17127#define RCC_PLLCFGR_RST_VALUE 0x24003010U
17128#define RCC_PLLI2SCFGR_RST_VALUE 0x24003000U
17129#define RCC_PLLSAICFGR_RST_VALUE 0x24003000U
17131#define RCC_MAX_FREQUENCY 180000000U
17132#define RCC_MAX_FREQUENCY_SCALE1 RCC_MAX_FREQUENCY
17133#define RCC_MAX_FREQUENCY_SCALE2 168000000U
17134#define RCC_MAX_FREQUENCY_SCALE3 120000000U
17135#define RCC_PLLVCO_OUTPUT_MIN 100000000U
17136#define RCC_PLLVCO_INPUT_MIN 950000U
17137#define RCC_PLLVCO_INPUT_MAX 2100000U
17138#define RCC_PLLVCO_OUTPUT_MAX 432000000U
17140#define RCC_PLLN_MIN_VALUE 50U
17141#define RCC_PLLN_MAX_VALUE 432U
17143#define FLASH_SCALE1_LATENCY1_FREQ 30000000U
17144#define FLASH_SCALE1_LATENCY2_FREQ 60000000U
17145#define FLASH_SCALE1_LATENCY3_FREQ 90000000U
17146#define FLASH_SCALE1_LATENCY4_FREQ 120000000U
17147#define FLASH_SCALE1_LATENCY5_FREQ 150000000U
17149#define FLASH_SCALE2_LATENCY1_FREQ 30000000U
17150#define FLASH_SCALE2_LATENCY2_FREQ 60000000U
17151#define FLASH_SCALE2_LATENCY3_FREQ 90000000U
17152#define FLASH_SCALE2_LATENCY4_FREQ 120000000U
17153#define FLASH_SCALE2_LATENCY5_FREQ 150000000U
17155#define FLASH_SCALE3_LATENCY1_FREQ 30000000U
17156#define FLASH_SCALE3_LATENCY2_FREQ 60000000U
17157#define FLASH_SCALE3_LATENCY3_FREQ 90000000U
17159#define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 12U
17160#define USB_OTG_HS_MAX_IN_ENDPOINTS 6U /* Including EP0 */
17161#define USB_OTG_HS_MAX_OUT_ENDPOINTS 6U /* Including EP0 */
17162#define USB_OTG_HS_TOTAL_FIFO_SIZE 4096U /* in Bytes */
17163/******************************************************************************/
17164/* For a painless codes migration between the STM32F4xx device product */
17165/* lines, the aliases defined below are put in place to overcome the */
17166/* differences in the interrupt handlers and IRQn definitions. */
17167/* No need to update developed interrupt code when moving across */
17168/* product lines within the same STM32F4 Family */
17169/******************************************************************************/
17170/* Aliases for __IRQn */
17171#define FSMC_IRQn FMC_IRQn
17172
17173/* Aliases for __IRQHandler */
17174#define FSMC_IRQHandler FMC_IRQHandler
17175
17179
17183
17187
17188#ifdef __cplusplus
17189}
17190#endif /* __cplusplus */
17191
17192#endif /* __STM32F429xx_H */
#define __IO
#define RESERVED(N, T)
Definition core_ca.h:179
#define FMC_IRQn
#define HASH_RNG_IRQn
IRQn_Type
STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition stm32f401xc.h:66
@ PendSV_IRQn
Definition stm32f401xc.h:74
@ ETH_WKUP_IRQn
@ EXTI2_IRQn
Definition stm32f401xc.h:85
@ DMA1_Stream2_IRQn
Definition stm32f401xc.h:90
@ CAN1_SCE_IRQn
Definition stm32f405xx.h:99
@ SDIO_IRQn
@ RTC_WKUP_IRQn
Definition stm32f401xc.h:80
@ OTG_HS_EP1_IN_IRQn
@ DMA2_Stream0_IRQn
@ DMA2_Stream6_IRQn
@ UART7_IRQn
@ I2C1_ER_IRQn
@ I2C2_EV_IRQn
@ MemoryManagement_IRQn
Definition stm32f401xc.h:69
@ SAI1_IRQn
@ TIM4_IRQn
@ TIM2_IRQn
@ LTDC_ER_IRQn
@ DMA2_Stream7_IRQn
@ TIM8_BRK_TIM12_IRQn
@ USART2_IRQn
@ DMA2_Stream3_IRQn
@ SVCall_IRQn
Definition stm32f401xc.h:72
@ ADC_IRQn
Definition stm32f401xc.h:95
@ SPI3_IRQn
@ SPI2_IRQn
@ TIM7_IRQn
@ UART8_IRQn
@ CAN2_SCE_IRQn
@ RCC_IRQn
Definition stm32f401xc.h:82
@ TIM6_DAC_IRQn
@ OTG_HS_EP1_OUT_IRQn
@ I2C2_ER_IRQn
@ TIM8_CC_IRQn
@ UsageFault_IRQn
Definition stm32f401xc.h:71
@ SysTick_IRQn
Definition stm32f401xc.h:75
@ I2C3_ER_IRQn
@ I2C3_EV_IRQn
@ CAN2_RX0_IRQn
@ BusFault_IRQn
Definition stm32f401xc.h:70
@ SPI5_IRQn
@ DebugMonitor_IRQn
Definition stm32f401xc.h:73
@ FLASH_IRQn
Definition stm32f401xc.h:81
@ DMA2_Stream5_IRQn
@ WWDG_IRQn
Definition stm32f401xc.h:77
@ I2C1_EV_IRQn
@ TIM3_IRQn
@ DMA2_Stream1_IRQn
@ CAN1_TX_IRQn
Definition stm32f405xx.h:96
@ OTG_HS_WKUP_IRQn
@ DMA1_Stream0_IRQn
Definition stm32f401xc.h:88
@ EXTI15_10_IRQn
@ SPI4_IRQn
@ TIM1_UP_TIM10_IRQn
Definition stm32f401xc.h:98
@ EXTI9_5_IRQn
Definition stm32f401xc.h:96
@ DMA1_Stream1_IRQn
Definition stm32f401xc.h:89
@ SPI6_IRQn
@ OTG_FS_IRQn
@ OTG_FS_WKUP_IRQn
@ FPU_IRQn
@ TIM8_UP_TIM13_IRQn
@ USART6_IRQn
@ SPI1_IRQn
@ OTG_HS_IRQn
@ PVD_IRQn
Definition stm32f401xc.h:78
@ TIM1_TRG_COM_TIM11_IRQn
Definition stm32f401xc.h:99
@ TIM1_BRK_TIM9_IRQn
Definition stm32f401xc.h:97
@ CAN2_RX1_IRQn
@ EXTI0_IRQn
Definition stm32f401xc.h:83
@ CAN1_RX0_IRQn
Definition stm32f405xx.h:97
@ EXTI4_IRQn
Definition stm32f401xc.h:87
@ DMA2_Stream2_IRQn
@ TAMP_STAMP_IRQn
Definition stm32f401xc.h:79
@ UART5_IRQn
@ DMA1_Stream5_IRQn
Definition stm32f401xc.h:93
@ DMA2D_IRQn
@ DCMI_IRQn
@ ETH_IRQn
@ USART1_IRQn
@ EXTI3_IRQn
Definition stm32f401xc.h:86
@ NonMaskableInt_IRQn
Definition stm32f401xc.h:68
@ UART4_IRQn
@ TIM8_TRG_COM_TIM14_IRQn
@ EXTI1_IRQn
Definition stm32f401xc.h:84
@ DMA2_Stream4_IRQn
@ TIM5_IRQn
@ DMA1_Stream7_IRQn
@ DMA1_Stream4_IRQn
Definition stm32f401xc.h:92
@ DMA1_Stream6_IRQn
Definition stm32f401xc.h:94
@ TIM1_CC_IRQn
@ LTDC_IRQn
@ CAN2_TX_IRQn
@ CAN1_RX1_IRQn
Definition stm32f405xx.h:98
@ DMA1_Stream3_IRQn
Definition stm32f401xc.h:91
@ USART3_IRQn
@ RTC_Alarm_IRQn
Analog to Digital Converter.
Controller Area Network FIFOMailBox.
Controller Area Network FilterRegister.
Controller Area Network TxMailBox.
Controller Area Network.
CRC calculation unit.
Digital to Analog Converter.
Debug MCU.
DMA2D Controller.
DMA Controller.
Ethernet MAC.
External Interrupt/Event Controller.
FLASH Registers.
Flexible Memory Controller.
Flexible Memory Controller Bank1E.
Flexible Memory Controller Bank2.
Flexible Memory Controller Bank4.
Flexible Memory Controller Bank5_6.
General Purpose I/O.
Inter-integrated Circuit Interface.
Independent WATCHDOG.
LCD-TFT Display layer x Controller.
__IO uint32_t CFBAR
__IO uint32_t CFBLR
uint32_t RESERVED1[3]
__IO uint32_t PFCR
__IO uint32_t WHPCR
__IO uint32_t CACR
__IO uint32_t CLUTWR
__IO uint32_t CKCR
__IO uint32_t BFCR
__IO uint32_t DCCR
__IO uint32_t WVPCR
__IO uint32_t CR
__IO uint32_t CFBLNR
uint32_t RESERVED0[2]
LCD-TFT Display Controller.
__IO uint32_t ICR
__IO uint32_t CPSR
__IO uint32_t AWCR
__IO uint32_t SSCR
uint32_t RESERVED1[2]
uint32_t RESERVED3[1]
__IO uint32_t CDSR
__IO uint32_t IER
__IO uint32_t BCCR
__IO uint32_t LIPCR
__IO uint32_t SRCR
uint32_t RESERVED2[1]
__IO uint32_t GCR
__IO uint32_t ISR
__IO uint32_t BPCR
__IO uint32_t TWCR
uint32_t RESERVED0[2]
Power Control.
Reset and Clock Control.
Real-Time Clock.
Serial Audio Interface.
SD host Interface.
Serial Peripheral Interface.
System configuration controller.
Universal Synchronous Asynchronous Receiver Transmitter.
USB_OTG_device_Registers.
USB_OTG_Core_Registers.
USB_OTG_Host_Channel_Specific_Registers.
USB_OTG_Host_Mode_Register_Structures.
USB_OTG_IN_Endpoint-Specific_Register.
USB_OTG_OUT_Endpoint-Specific_Registers.
Window WATCHDOG.
CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.